TW200539345A - Dual doped polysilicon and silicon germanium etch - Google Patents
Dual doped polysilicon and silicon germanium etch Download PDFInfo
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- TW200539345A TW200539345A TW094107721A TW94107721A TW200539345A TW 200539345 A TW200539345 A TW 200539345A TW 094107721 A TW094107721 A TW 094107721A TW 94107721 A TW94107721 A TW 94107721A TW 200539345 A TW200539345 A TW 200539345A
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- layer
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- polycrystalline silicon
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- 229910000577 Silicon-germanium Inorganic materials 0.000 title claims abstract description 48
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims description 51
- 229920005591 polysilicon Polymers 0.000 title claims description 5
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 title abstract description 5
- 230000009977 dual effect Effects 0.000 title 1
- 238000005530 etching Methods 0.000 claims abstract description 79
- 238000000034 method Methods 0.000 claims abstract description 47
- 238000012545 processing Methods 0.000 claims abstract description 40
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 239000003701 inert diluent Substances 0.000 claims abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 26
- 229910052710 silicon Inorganic materials 0.000 claims description 26
- 239000010703 silicon Substances 0.000 claims description 26
- 229920002120 photoresistant polymer Polymers 0.000 claims description 16
- 229910052770 Uranium Inorganic materials 0.000 claims description 12
- JFALSRSLKYAFGM-UHFFFAOYSA-N uranium(0) Chemical compound [U] JFALSRSLKYAFGM-UHFFFAOYSA-N 0.000 claims description 11
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 claims description 8
- RWRIWBAIICGTTQ-UHFFFAOYSA-N difluoromethane Chemical compound FCF RWRIWBAIICGTTQ-UHFFFAOYSA-N 0.000 claims description 8
- 238000001816 cooling Methods 0.000 claims description 7
- 239000004576 sand Substances 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 5
- 239000003795 chemical substances by application Substances 0.000 claims description 3
- 241000238631 Hexapoda Species 0.000 claims 1
- 239000002689 soil Substances 0.000 claims 1
- 210000002784 stomach Anatomy 0.000 claims 1
- 239000007789 gas Substances 0.000 description 38
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 6
- 239000010409 thin film Substances 0.000 description 5
- 238000009966 trimming Methods 0.000 description 5
- 238000002161 passivation Methods 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 238000002474 experimental method Methods 0.000 description 3
- 239000001307 helium Substances 0.000 description 3
- 229910052734 helium Inorganic materials 0.000 description 3
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- -1 at least one of (C2 Substances 0.000 description 2
- 239000002826 coolant Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000012530 fluid Substances 0.000 description 2
- 230000006698 induction Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 101710117064 Trimethylamine corrinoid protein 1 Proteins 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 1
- 125000005842 heteroatom Chemical group 0.000 description 1
- 230000000423 heterosexual effect Effects 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000011378 penetrating method Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 239000003504 photosensitizing agent Substances 0.000 description 1
- 238000004549 pulsed laser deposition Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 239000000344 soap Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
- H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/82345—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
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- H—ELECTRICITY
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
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- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Drying Of Semiconductors (AREA)
- Electrodes Of Semiconductors (AREA)
Description
200539345 (1) 九、發明說明 【發明所屬之技術領域】 本發明係有關半導體裝置。更特定言之,本發明係有 關具有經摻雜的多晶矽和矽化鍺堆疊之半導體裝置。 【先前技術】 使用有經摻雜和未摻雜的多晶矽和矽化鍺(Si Ge )區 φ 之薄膜堆疊的形成來形成半導體裝置用之閘電極。 【發明內容】 爲了達到前述且根據本發明目的,提供一種在一處理 室內蝕刻在一基板上有至少一矽鍺層的堆疊之方法。提供 一種對矽化鍺之蝕刻。於處理室中提供蝕刻劑氣體,其中 該蝕刻劑氣體包括HBr,一惰性稀釋劑,和在02與N2中的 至少一者。該基板係經冷卻到低於40 °C的溫度。該蝕刻氣 φ 體係經轉換成電漿以鈾刻該矽化鍺層。 於本發明另一顯示例中,提供一種蝕刻在基板上的多 晶之方法,其中該基板係經置放於一處理室內。於該處理 室內提供一蝕刻劑氣體,其中該蝕刻劑氣包括N2,SF6, 和在CHF3與CH2F2中的至少一者。該蝕刻劑經轉換爲電漿 以触刻該多晶砂層。 於本發明另一顯示例中,提供一種蝕刻在一基板上具 有至少一矽化鍺層的堆疊所用裝置。該裝置包括一處理室 ,一氣體源,一供能源,一溫度控制裝置用以控制該基板 -5- (2) 200539345 的溫度,和一控制器。該控制器包括電腦可讀媒體,內含 電腦可讀代碼用以從氣體源提供鈾刻劑氣體到該處理室內 ,其中該鈾刻劑氣體包括HBr,惰性稀釋劑,與在02和N2 中的至少一者;電腦可讀代碼用以將基板冷卻到低於40 之溫度;及電腦可讀代碼用來使用該供源將該蝕刻氣體轉 換成電漿以蝕刻該矽化鍺層。
【實施方式】 較佳具體實例之詳細說明 至此要參照一些如附圖中示範出的本發明較佳具體實 例來詳細說明本發明。於下面的說明中,列出許多特定的 細部以提供對本發明的徹底了解。不過,對於諳於此技者 明顯可知本發明可以不需要某些或全部此等特定細部即實 施。於其他情況中,沒有詳述熟知程序步驟及/或結構以 免不必要地混淆本發明。 爲了幫助了解,圖1爲形成可用爲閘電極的經蝕刻薄 膜堆疊所示出之高水平流程圖。形成一有諸多層的堆疊( 步驟104 )。蝕刻該諸層的堆疊(步驟108 )。圖2爲形成 諸多層的堆疊之更詳細流程圖(步驟204 )。圖3A爲具有 在基板3 08上面形成的閘氧化物層3 04之薄膜堆疊的橫斷面 圖。於閘氧化物層3 04上面形成一矽晶種層312 (步驟208 )。於閘氧化物層3 04上面形成一矽化鍺(Si Ge)層316 ( 步驟212 )。於該Si Ge層3 16上面形成一多晶矽層320 (步 驟2 1 6 )。該多晶矽層3 2 0包括雙重摻雜層和一未摻雜層 -6 - 200539345 (3) 3 0 4。該雙重摻雜層包括經摻雜區3 2 8和未摻雜區3 2 2。可 以使用摻雜區和未摻雜區之各種組態。通常,多晶矽層 3 2 0的經最濃摻雜區可靠近摻雜區3 2 8的頂部,而形成從具 有最濃摻雜區的頂部到具有最少摻雜區或未摻雜區的多晶 矽層頂部之梯度。經濃摻雜區係位於多晶矽層的頂部。摻 雜水平隨著愈深遞減且於最後該多晶矽在更深處變成未摻 雜。於該經雙重摻雜多晶矽層3 2 0上面放置一防反射塗層 鲁 (ARC ) 3 32,例如底部防反射層(BARC層)(步驟220 )。於該ARC層332上面形成一光阻劑罩336 (步驟224) 〇 於堆疊的一例子中,該鬧氧化物層3 0 4可爲約1 . 5奈米 厚。該矽晶種層3 1 2可爲約1 0奈米厚。該S i G e層3 1 6可爲約 20奈米厚。該經雙重摻雜多晶矽層3 20可爲約100奈米厚。 該經雙重摻雜多晶矽層3 20的最濃摻雜區32 8可具有50 - 70 奈米之深度。該ARC層332可爲約100奈米厚。該193奈米 φ 只阻劑罩可爲約190奈米厚。 此等堆疊的蝕刻具有加添的困難性,在於經摻雜多晶 矽區的蝕刻特性不同於蝕刻未摻雜多晶矽區之特性。其結 果使可在未摻雜多晶矽區提供垂直蝕刻劑面的蝕刻方法可 能在摻雜多晶矽區中提供倒切(under cutting )。於另一 例子中’可對經摻雜多晶矽區提供垂直蝕刻剖面的蝕刻可 能對未摻雜多晶矽區提供漸細的輪廓或底部(footers )。 在經雙重摻雜的多晶矽層3 20下面的SiGe層3 16具有不 同於經雙重摻雜多晶矽層3 2 0之之蝕刻性質。不同於矽晶 (4) (4)200539345 種層3 1 2的S i G e層3 1 6蝕刻性質和S i G e層3 1 6薄度更添加額 外的蝕刻困難性。於此等困難性中,可以對經雙重摻雜多 晶矽3 20提供垂直蝕刻之蝕刻程序可能在Si Ge層3 16中造成 倒切或在矽晶種層3 1 2中形成底腳。由S i G e層和晶種層的 薄度所造成的困難性之部份原因在於對於此等薄層更難以 具有分開的蝕刻步驟。其中係使用單一蝕刻步驟來同時蝕 刻S i G e層的晶種矽層。垂直蝕刻係重要者,且甚至更重要 者爲靠近堆疊的底部者,係因爲靠近堆疊底部的尺寸有助 於界定閘長度之故。所以,倒切或底腳的形成都會改變閘 長度。 此外,該光阻劑較佳者爲1 9 3奈米或更後面世代的阻 劑,其比較早世代阻劑更爲柔軟。因此,本發明蝕刻必須 更具選擇性且提供等些鈍化作用以保護光阻劑飩刻罩而不 提供太多的可能促成蝕刻停止之鈍化。 圖4爲蝕刻層堆疊的步驟(步驟1 0 8 )之更詳細流程圖 。首先修整光阻劑罩(步驟4 0 4 )。於此可以使用如下所 述之新穎修整程序以減小光阻劑罩的臨界尺寸。接著蝕刻 ARC層,於此具體實例中爲一 BARC層(步驟408)。於此 可以使用習用的BARC蝕刻法來蝕穿該BARC層。 然後使用貫穿.蝕刻來蝕穿由多晶矽層3 2 0的未摻雜區 3 22和摻雜區32 8所形成的經雙重摻雜區之至少部份(步驟 412 )。在多晶矽層頂部的未摻雜區322和摻雜區3 2 8係同 時予以蝕刻。於此具體實例中,該貫穿蝕刻係提供包括U2 ,SF6,和在CHF3與CH2F2中的至少一者之鈾刻劑氣體。 200539345 (5) 將蝕刻劑氣體經轉換爲電漿,該電漿係用來蝕穿該 層3 20的摻雜區3 2 8和未摻雜區3 22。雖然貫穿蝕刻 穿過在多晶矽上形成的天然氧化物,不過於此步驟 的貫穿蝕刻係用來蝕穿在經雙重摻雜多晶矽上形成 氧化物及該經雙重摻雜多晶矽層的最濃摻雜區。本 穿鈾刻可提供最低的摻雜/未摻雜輪廓負載結果, 摻雜區和未摻雜區都以相同的蝕刻特性予以蝕刻, 雜和未摻雜輪廓看起來相似。 貫穿蝕刻後面接著爲第一主蝕刻,係用來蝕穿 多晶矽層3 24 (步驟4 1 6 )。於此具體實例中,該穿 雜多晶矽層的第一主蝕刻係使用包括(C2,HBr CF4中至少'一者的蝕刻劑氣體。此蝕刻步驟可以 Si Ge層3 16蝕刻出一特件。業經發現者,此種蝕刻 閘氧化物具有低選擇性,所以宜於在蝕刻特性達到 物之前停止貫穿蝕刻。可以使用一干涉儀終點來蝕 到距閘氧化物層3 0 4約4 0奈米的距離處。此外,可 光學發散終點在多晶矽/Si Ge介面停止蝕刻。 該第一主蝕刻之後接著對蝕刻停止更高選擇性 主蝕刻(步驟420 ),其係針對閘氧化物層者。於 實例中,該第二主蝕刻係使用HBr和02作爲蝕刻劑 該第二主蝕刻係用來高度選擇性地蝕刻多晶矽層, ,和砂晶種層。 於第二主蝕刻到達蝕刻停止之後,實施一過鈾 (步驟424 )以完成SiGe層和矽晶種層的蝕刻。所 多晶矽 意謂著 中所用 的天然 發明貫 使得經 使得摻 未摻雜 過未摻 ,〇2和 用來對 方法對 閘氧化 刻特件 以使用 之第二 此具體 氣體。 SiGe 層 刻步驟 以,於 -9- 200539345 (6) 此具體實例中,係使用S i G e餓刻作爲多晶砂過蝕刻步騾以 完成對多晶矽層3 2 0,S i G e層和矽晶種層之蝕刻。於此具 體實例中,S i G e層和矽晶種層的蝕刻係使用Η B r,H e和U 2 之蝕刻劑氣體。此過飩刻係用來完成蝕刻及淸除殘渣。業 經發現者,經由在低於4 0 °C的溫度實施此蝕刻可提供意外 的結果,可對Si Ge層和矽晶種層兩者都提供垂直鈾刻輪廓 而沒有倒切,弓形,或形成底腳。 進行數個的期間的實驗以期找到在蝕刻經雙重摻雜的 多晶矽層,Si Ge層和晶種層的提供垂直蝕刻輪廓之方法。 所嘗試的蝕刻方法沒有一者經發現可提供合意的結果,直 到在Si Ge蝕刻中使用採用低於40 °C的較低處理溫度之實驗 意外地提供合意的輪而沒有倒切,弓形,或形戶底腳爲止 〇 通常,對每一触刻步驟都提供一過蝕刻步驟。若使用 蝕刻監視器來測定何時到達終點之時,可以使用過蝕刻步 驟在要蝕刻超過終點一預定量之時提供額外的蝕刻。 實施例1 於本發明一實施例中,係形成層合堆疊。該層合堆疊 可以使用圖.2中所述諸步驟形成爲圖3A中所示層堆疊。於 此實施例中’該閘氧化物層3 0 4爲1 . 5奈米厚。矽晶種層 3 12爲10奈米厚。該。(36層316爲2〇奈米厚。該經雙重摻雜 多晶矽層爲100奈米厚。ARC層332爲100奈米厚。該193光 劑劑罩3 3 6爲1 9 0奈米厚。然後將基板放到處理室內。 -10- (7) 200539345 圖5爲可用於本發明較佳具體實例中的處理室5 00之示 意圖。於此實施例中,該處理室包括Lam Research Corporation of Fremont, Caloforma ,的 23 00 Versys Silicon。該電漿處理室500可包括一感應線圈504,一下電 極5 0 8,一氧體流510,和一排放泵520。於該電漿處理室 5 00之內,基板3 08係經放置在下電極5 0 8之上。該下電極 5 08倂有一適當的基板扣定機構(如靜電,機械夾取,或 # 類似者)用以支撐該基板3 08。反應器頂部528倂有一介電 性窗。該室頂5 2 8,室壁5 5 2,和下電極5 0 8 —起界定一侷 限的電漿體積540。氣體係由氣體源透過氣體入口 543供給 到侷限電漿體積且由排放泵5 20從該侷限電漿體積排放出 。排放泵520形成該電漿處理室的氣體出口。一第一 RF源 5 44係經電連接到該線圈504。一第二RF源548係經電連接 到到下電極508。於本具體實例中,該第一和第二RF源 544,548都包括一 13,56MHz功率源。可有不同的RF源連 # 到電極之組合。一控制器5 3 5經可控制地連接到第一 RF源 544,該第二RF源548,排放泵520,和氣體源510。基板 冷卻系統包括一冷卻一冷卻器用之冷卻器5 5 2和一將冷卻 劑從該冷卻器5 5 2通到且穿過該下電源5 08 (靜電卡盤)然 後回到冷卻器5 5 2所用之流體輸送裝置5 5 6。經冷卻的下電 極508可冷卻該基板。此外,在下電極內部裝有加熱器560 用以加熱基板5 8 0。加熱器5 6 0和基板冷卻系統及控制器 5 3 5可以將溫度控制到可以在不同步驟提供不词的基板溫 度,如在下面諸實施例中所提出者。 -11 - 200539345 (8) 圖6A和6B闡明出一電腦系統840,其適合用來執行本 發明具體實例中所用的控制器5 3 5。圖6A顯示出該電腦系 統的一可能的物理形式。當然,該電腦系統可具有許多物 理形式,從積體電路,印刷電路板,和小型手持裝置到巨 型超電腦。電腦系統8 00包括一監視器8 02,一顯示器804 ,一外殼806,一磁碟機8 0 8,一鍵盤810,和一滑鼠812。 磁碟814爲一種電腦可讀式媒體,用以從電腦系統800存取 資料。 圖6B爲電腦系統8 〇0方塊圖之一例子。接到系統母線 820者爲廣多種子系統。處理器822 (也稱中央處理單元或 (PUS )係經耦接到儲存裝置,包括記憶體8 24。記憶體 824包括隨機存取記憶體(ram)和唯讀記憶體(ROM) 。如技藝中所熟知者,ROM的作用爲將資料和指令單向地 傳送到CPU而RAM典型地係用來將資料和指令以雙向方式 傳送。這兩種類型的記憶體可包括任何種適當的下述電腦 可讀媒體。一固定磁碟82 6也雙向地耦接到CPU822 ;其可 提供額外的資料儲存容量且也可包括任何種下述電腦可讀 媒體。固定磁碟826可用來儲存程式,數據,和類似者且 典型地爲一種比初級儲存較爲慢之二次儲存媒體(例如硬 碟)·。要了解者,保留在固定磁碟826內的資訊可,於恰 當情況中,係以標準方式在記憶體824內倂組成虛擬記憶 體。可取出的磁碟8 1 4可採取任何下述電腦可讀媒體之形 式。 CPU 8 2 2也經耦接到多種輸入/輸出裝置,例如顯示器 -12- (9) 200539345 8 04,鍵盤810,滑鼠812和揚聲器8 3 0。通常 出裝置可爲下列中任何一者:視訊顯示器,磁 ,鍵盤,微音器,觸感式顯示器,傳感器卡讀 紙帶讀器,或其他的電腦。CPU 822視需要可 一電腦或使用網路介面840接到遠端通信網路 網路介面,可擬及者,該CPU可接收來自網路 可在實施上面方法步驟的過程中將資訊輸出到 Φ ,本發明方法的具體實例可以僅在CPU 82 2上 共有處理部份的遠端CPU配合而在網路上執行 此外,本發明的具體實例進一步有關具有 體的電腦儲存產品,其上可具有電腦代碼以實 執行操作。該媒體和電腦代碼可針對本發明目 設計和構成,或彼等可爲諳於電腦軟體技藝者 去用之類型。電腦可讀媒體的例子包括,但不 媒體例如硬碟,軟碟,和磁帶;光學媒體例如 Φ 和全息影像裝置;磁一光學媒體例如軟式光碟 置,其係經特別構組以儲存和執行程式代碼, 異性積體電路(ASICs ),可編程邏輯裝置 ROM和RAM裝置。電腦代碼的例子包括機器 編譯器所產生者,和包含更高層次要由電腦使 執行的檔。電腦可讀媒體也可爲由埋置於載波 可由處理器執行的指令序列之電腦資料信號所 代碼。 光阻劑修整可在處理室5 00內完成或在將: ,一輸入/輸 軌球,滑鼠 器,磁帶或 以耦接到另 。使用此種 的資訊,或 網路。另外 執行或可與 〇 電腦可讀媒 施各種電腦 的而特定地 所熟知且可 限於:磁性 CD-ROMs ;及硬體裝 例如應用特 (PLDs)及 代碼,例如 用解釋程式 中且呈現一 傳遞之電腦 基板放置在 -13- (10) 200539345 處理室5 00內部之前完成。於修整程式(步驟404 )的一較 佳具體實例中,係提供HBr,02和CHF3以在處理室內修整 阻劑。於此實施例中,修整氣體爲30sccm HBr,30sccm 02,和40sccm CHF3。處理室內的壓力爲5mTo:rr。供應到 處理室的TCP功率爲25 0瓦(Watts )。偏壓爲70伏。於靜 電卡盤中提供8Tori·的氮氣背側壓力。提供60t的靜電卡 盤溫度。此步驟係維持44秒。此較佳具體實例提供一改良 φ 的光阻劑修整。 然後開放BARC層。可以使用習用的BARC開放步驟。 B ARC鈾刻可在處理室500之內完成,或在將基板放到處理 室5 0 0內之前完成。此等B ARC開放程序(步驟4 0 8 )可以 ‘ 使用Cl2,02,和He來蝕刻BARC。 用於貫穿步驟(步驟412 )時,係提供包括N2,SF6, 和在CHF3和CH2F2中的至少一者。於此實施例中,蝕刻劑 氣體爲 lOOsccm CHF3,50sccm N2,和 20sccm SF6。處理 # 室中的壓力爲5mT〇rr。供給到處理室的TCP功率爲275瓦 。偏壓爲135伏。於靜電卡盤提供8T〇rr皂氦氣背側壓力。 提供6 0 °C的靜電卡盤溫度。此步驟經維持2 5秒鐘。 對於第一主蝕刻步驟(步驟4 1 6 ),係提供包括C】2, HBr,02,和CF4中至少一者的鈾刻劑氣體·。於此實施例 中,該蝕刻劑氣爲 50sccm Cl2,250sccm HBr,50sccm CF4,和5sccm 02。處理室中的壓力爲1 OmTorr。供給到處 理室的TCP功率爲600瓦。偏壓爲125伏。提供8Torr的氦氣 背側壓力。提供6(TC的靜電卡盤溫度。此步驟經維持7秒 -14- (11) (11)200539345 鐘。 對於第二主蝕刻步驟(步驟4 2 0 ),係提供包括Η B r ,一惰性稀釋劑,與在〇 2和N 2中的至少一者之蝕刻劑氣體 。於此實施例中,該蝕刻劑氣體爲l80sccm HBr與 〇2。處理室中的壓力爲6m Torr。供給到處理室的TCP功率 爲3 5 0瓦。偏壓爲6 5伏。提供8 T 〇 r r的氨氣背側壓力。提供 6 0°C的靜電卡盤溫度。此步驟經維持14秒鐘。 對於過蝕刻步驟(步驟4 2 4 ),其也爲s i G e蝕刻,係 提供包括Η B r,惰性稀釋劑,與在〇 2和n 2中的至少一者之 蝕刻劑氣體。於此實施例中,該蝕刻劑氣體爲133 seem HBr和2sccm 02。處理室中的壓力爲80mTorr。供給到處理 室的TCP功率爲5 00瓦。偏壓爲210伏·。提供8Torr的氦氣背 側壓力。提供3 0 °C的靜電卡盤溫度。此步驟經維持7 2秒鐘 。因爲低處理溫度之故,S i G e蝕刻步驟非常頑強且能夠 支撐整個步驟時間而沒有S i G e層的側向侵害。於触刻劑氣 體中也可以添加惰性氣體例如氦氣。於此實施例中,係加 入26 7sCcm He。於本發明裝置中的加熱器和冷卻器能夠提 供含意的溫度控制,其可將基板溫度在步驟之間從60 °C改 變到3 (TC。該加熱器和冷卻器提供快速改變溫度之能力。 此實施例經發現可提供跨晶圓之均勻蝕刻。 其他實施例 (12) (12)200539345 表1提供貫穿蝕刻所用的較佳,更佳,和最佳範圍。 表1
較佳範圍 更佳範圍 最佳範圍 n2 20-100sccm 25-75sccm 40-60sccm sf6 5-50sccm 10-30sccm 15-25sccm chf3 30-200sccm 50-150sccm 75-125sccm TCP 100- 1 000 Watts 1 5 0-600Watts 200-400 Watts 偏壓 25 -200Volts 5 0- 1 75 Volts 1 00-150Volts 壓力 1 - 4 0 m Torr 3 -2 OmTorr 5-10mTorr 流速比 C H F 3 : s F 6 50:1-2:1 20:1-3:1 10:1-3:1 流速比 chf3 :ν2 5:1-1:1 4:1-1:1 3:1-2:1 溫度 1 0 - 9 0 °C 2 5 > 8 0 °C 3 0 - 6 0 °C (13) 200539345 表2提供第一主蝕刻所用的較佳,更佳和最佳範圍。 表2
較佳範圍 更佳範圍 最佳範圍 C12 20-100sccm 25-75 seem 40-60 seem cf4 i0-100sccm 30-70 seem 40-60 seem HBr 100-500sccm 150-400 seem 200-300 seem 〇2 1-20 seem 2-15 seem 3-10 seem TCP 100- 1 000 Watts 3 00- 8 00 Watts 5 00-700 Watts 偏壓 5 0-200Volts 1 00- 1 5 0 Volts 115-135 Volts 壓力 l-40mTorr 3-20 mTorr 5-15 mTorr 流速比 HBr:CF4 10:1-2:1 8:1-3:1 6:1-4: 1 流速比Η B r : 0 2 100:1-10:1 80:1 -20: 1 60:1-40:1 流速比 Η B r : C 12 10:1-2:1 8:1-3:1 6:1-4:1 溫度 1 0 - 9 0 °C 2 5 - 7 0 °C 3 0 - 6 0 °C -17- (14) 200539345 表3提供第二主蝕刻所用的較佳,更佳和最佳範圍。 表3
較佳範圍 更佳範圍 最佳範圍 〇 2 100-400sccm 150-300 seem 160-200 seem HBr 100-600 seem 200-500 seem 300-400 seem TCP 1 00-600 Watts 200-5 00 Watts 3 00-400 Watts 偏壓 2 0-110 Volts 40- 1 00 Volts 60-90 Volts 壓力 l-20mTorr 3-15 m T o rr 5-10 mTorr 流速比Η B r : 0 2 100:1-10:1 80:1-20:1 5 0:1 -3 0:1 溫度 1 0 - 9 0 〇C 1 5 - 7 0 °C 2 0 - 6 0 °C 若用Ns取代〇2,則在上述實施例中n2具有與〇2相同 的流速和流速比。此外,除了氧氣外也可以使用相同量的 氮氣。
表4提供蝕刻SiGe層和矽晶種層的多晶矽過蝕刻( S i G e蝕刻)所用的較佳’更佳,與最佳範圍。 200539345 (15) 表4
較佳範圍 更佳範圍 最佳範圍 〇2 0.5-2 Oseem 1-10 seem 1-5 seem HBr 8 0-3 00 seem 100-200 seem 120-150 seem TCP 100-1000 200-750Watts 400-600 Watts Watts 偏壓 1 00-400 Volts 1 50-3 00 Volts 1 80-25 0 Volts 壓力 20-100 mTorr 40-90 mTorr 60-80 mTorr 流速比ΗΒΓ:〇2 200:1-10:1 100:1-20:1 80:1-30:1 溫度 0-4 0°C 1 0 - 3 0 〇C 2 0 - 3 0 °C
若用仏取代02,則N2具有與上述實施例中的〇2相同 之流速和流速比。此外,除了氧氣外也可以用相同的量使 用氮氣。 於上述諸實施例中,蝕刻氣體基本上係由所載成分氣 體所構成。於其他具體實例中,可以使用別的或加添的成 分氣體。 於另一實施例中,使用5mTorr壓力,300瓦的TCP功 率’ 53伏的偏壓’和6〇r的卡盤溫度之貫穿法可以使用含 ChF2 ’ SF6 ’和N2之貫穿氣體混合物。於一實施例中,該 貝贫氣體混合物包括3〇sccm的CH2F2,20sccm的SF6,和 5〇Sccm的N2 ’其係經維持37秒鐘。於另—實施例中,該貫 穿氣體混合物包括40sccm CH2F2,20 seem SF6 ,和 5QSeem N2 ’其係維持52秒鐘。雖然此等方法提供良好結 -19- (16) (16)200539345 果,不過經發現者,使用CH2F2時的程序窗顯得比使用 CH3F的程序窗較爲小。業經發現者,將TCP功率增加到至 少6 0 0瓦有助於減低頸縮現象(n e c k i n g )。 透過在60 °C的實驗,業經發現者,於Si Ge鈾刻中降低 HBr/He比例可減少SiGe層弓變化(bowing ),不過仍可能 造成矽晶種層中的小底腳。也發現者,延長SiGe蝕刻步 驟會增加SiGe輪廓弓化。 業經發現者,於Si Ge蝕刻步驟中,將基板溫度降低 到低於4 0 °C,較佳者到約3 0 °C,可導致晶種矽,多晶矽, 和SiGe層各具有約相同蝕刻特性之蝕刻。基板溫度的降低 可提供非常頑強的程序,其中參數中的輕微變化不會明顯 地增加倒切或弓變化,或底腳的形成。所以在SiGe蝕刻 中減低溫度可促成程序參數的某些變異而不會影響經蝕刻 特件的垂直輪廓。將基板維持在3 (TC可經由用冷卻器5 5 2 將冷卻體冷卻到2(TC而完成。冷卻液體係通過下電極508 以冷卻該下電極到20°C,而此可冷卻基板3 08到20°C。然 後使用加熱器5 60將基板加熱到30t:。 本發明的其他具體實例係用貫穿蝕刻替代第一主蝕刻 ,因而延長貫穿触刻步驟且消除掉第一主触刻。 其他具體實例可在低於40 °C的溫度下實施第二主蝕刻 以獲得更頑強的結果。本發明蝕刻也提供足夠的鈍化以防 上倒切,而不造成蝕刻停止。於另一實施例中,係在第二 主蝕刻中提供少量的Cl2以消除或減少在第二主蝕刻中形 成的任何底腳。 -20- (17) (17)200539345 也發現者,本發明蝕刻可提供減低的線邊緣粗糙度。 此外也相信本發明可在修整步驟中促成更大的鈍化作用因 而減低側壁粗糙度。 本發明其他具體實例可提分開提供本發明SiGe蝕刻 以取代多晶矽過蝕刻。 爲了幫助了解,圖7 A — 7D爲使用多種方法鈾刻過的 多種輪廓之示意圖解,其中7A — C爲使用先前技藝方法蝕 刻出的輪廓之示意圖示而圖7 D爲使用本發明蝕刻出的輪 廊之不意圖解。隱7 A爲在一基板7 0 8上的鬧氧化物層上面 的堆疊之示意圖解,此.處該堆疊包括一矽晶種層7 1 2,一 SiGe層716,和一多晶矽層722,具有經摻雜區和未摻雜區 。於此實施例中先前技藝蝕刻方法造成一彎曲SiGe部份 722與一晶種矽腳724。於此實施例中,彎曲部和底腳的組 合沒有造成任何CD增益。圖7B爲用先前技藝蝕刻的堆疊 之示意圖解,其中造成一較不彎曲的SiGe部份732和一較 大的晶種矽腳734,此處該彎曲部和底腳的組合造成CD增 益。圖7C爲使用先前技藝蝕刻的堆疊之示意圖解,其中造 成一垂直的S i G e部份和一晶種矽腳7 4 4,此處該底腳造成 CD增益。圖7D爲使用本發明蝕刻一堆疊之示意圖解.,造 成垂直的S i G e層和晶種矽蝕刻。 雖然本發明已就數個較佳具體實例予以說明過,不過 仍有落於本發明範圍內的變更,排列,修飾和各種取代等 效物。也必須提及者有許多替恣方式可用來實施本發明方 法和裝置。所以下面所附申請專利範圍理應解釋爲包括落 (18)200539345 於本發明真旨意和範圍內的所有此等變更,排 各種替代等效物。 【圖式簡單說明】 本發明要於所附圖式的圖中範例地,而 明,且於圖式中相同的指示數字係指示相似的 中 圖1爲形成可供閘電極所用的經蝕刻堆疊 程圖。 圖2爲形成諸層的堆叠之更詳細流程圖。 圖3 A - 3 B爲具有在基板上形成的閘氧化今 薄膜堆疊的示意橫斷面圖。 圖4爲鈾刻諸層的堆疊之更詳細流程圖。 圖5爲可用於本發明較佳具體實例中的處 圖。 圖6A和6B示範出一適合用來執行一控 系統。 圖7A-D爲經蝕刻的薄膜堆疊之示意圖。 列,修飾和 非限制地闡 元件且於其 之高水平流 &層 3 0 4之 理室之示意 制器之電腦 【主要元件符號說明】 304 閘氧化物層 308, 580, 708 基板 3 1 2,7 1 2 矽晶種層 316, 716 S i Ge 層 -22- 200539345
(19) 320 , 722 多晶ί夕層 322 未慘雑區 324 未摻雜層 328 摻雜區 332 防反射層 336 光阻劑罩 500 處理室 5 0 4 感應線圈 508 下電極 5 10 氣體源 520 排放泵 528 反應器頂部 535 控制器 543 氣體入口 544 第一 RF源 548 第二RF源 552 室壁 552 冷卻器 556 流體輸送裝置 560 加熱器 724 , 744 晶種矽腳 732 較不變的SiGe部份 734 較大晶種矽腳 800 電腦系統 -23- 200539345 (20) 802 804 806 808 8 10 8 12 8 14 φ 820 824 826 830 840 監視器 顯示器 外殼 磁碟機 鍵盤 滑鼠 磁碟 系統母線 記憶體 固定磁碟 揚聲器 網路介面
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Claims (1)
- (1) 200539345 十、申請專利範圍 1 · 一種在一處理室內蝕刻在一基板上面具有至少一 矽化鍺層的堆疊之方法,包括提供對矽化鍺之蝕刻,其包 括: 將一蝕刻劑氣體提供到該處理室內,其中該蝕刻劑氣 體包括Η Β Γ,一惰性稀釋劑,和在〇 2與N 2中的至少一 者; # 將該基板冷卻到低於4(TC之溫度;及 將該蝕刻劑氣體轉換成電漿以蝕刻該矽化鍺層。 2 ·如申請專利範圍第1項之方法,其中該堆疊進一 步包括在該矽化鍺層上面的多晶矽層,其中該多晶矽層有 至少一區係經摻雜,該方法進一步包括提供對該多晶矽層 的貫穿蝕刻,包括: 提供一蝕刻劑氣體於該處理室內,其中該蝕刻劑氣體 包括N2,SF6,及在CHF3和CH2F2中的至少一者;及 # 將該蝕刻劑氣體轉換爲電漿以蝕刻該多晶矽層。 3.如申請專利範圍第2項之方法,其進一步提供對 多晶矽之主蝕刻,包括 提供含有在Cl2,HBr,CF4,和02之中至少一者的 倉虫刻劑氣體;及 將該蝕刻劑氣體轉換爲電漿以蝕刻該多晶矽層。 4 ·如申請專利範圍第3項之方法,其中蝕刻該矽化 鍺層和該多晶矽層提供一垂直剖面。 5 .如申請專利範圍第4項之方法,其中該堆疊進一步 -25- (2) 200539345 …藏,宜中該s iG e蝕刻 包括一在該矽化鍺層下面的晶種矽層 … 係鈾刻穿過該晶種矽層。 :土,:§:中該晶種砂層與 6 .如申請專利範圍第5項之方法 〃 Ψ 該矽化鍺層的合倂厚度係在1 〇與5 0奈# 2 ^ ° >七·冰,宜進一步包括在 7.如申請專利範圍第6項之力/去 〆、 該堆疊上提供一光阻劑罩。 8 ·如申請專利範圍第7項之方法’其中該光阻劑罩 φ 爲193或更高代的光阻劑。 9 .如申請專利範圍第4項之方法’其中該多晶5夕層 具有至少一摻雜區。 1 0 ·如申請專利範圍第5項之方法’其中强晶種砂層 與矽化鍺層的合倂厚度係小於該多晶@層胃^ @ ~半1 ° Π .如申請專利範圍第1項之方法’其中該堆疊進一 步包括在該矽化鍺層下面的晶種矽層’ #巾_ Sl(3e Μ % 係蝕刻穿過該晶種矽層。 φ 1 2 ·如申請專利範圍第丨]項之方法’其中該晶種砂 層與矽化鍺層的合倂厚度係介於1 0與5 0奈米之間b 1 3 ·如申請專利範圍第1項之方法’其進一步包括於 該堆疊上提供一光阻劑罩。 1 4 ·如申請專利範圍第1 3項之方法,其中該光阻劑 罩爲1 9 3或更高代之光阻劑。 1 5 · —種申請專利範圍第1項之方法形成之半導體裝 置。 1 6. —種蝕刻在一基板上的多晶矽層之方法,其中該 - 26- (3) (3)200539345 多晶砂層具有至少一摻雜區,該方法包括: 將該基板放置在一處理室內; 提供一蝕刻劑氣體到該處理室內,其中該蝕刻劑氣體 包括N2’ SF6’及在CHF3和CH2F2中的至少一者;及 將該蝕刻劑氣體轉換爲電漿以蝕刻該多晶矽層。 17.如申請專利範圍第1 6項之方法,其進一步包括 提供對多晶矽之主蝕刻,包括: . 提供含Cl2,HBr,CF4,和02中至少一者的蝕刻劑 氣體;及 將該含蝕刻劑氣體轉換成電漿以蝕刻該多晶矽層。 1 8 .如申請專利範圍第.1 7項之方法,其進一步包括 在該堆疊上提供一光阻劑罩。 1 9 ·如申請專利範圍第1 8項之方法,其中該光阻劑 罩爲1 93或更高代的光阻劑。 2 0 ·如申請專利範圍第1 6項之方法’其中該多晶矽 層具有至少一未摻雜區。 2 1 · —種用申請專利範圍第1 6項之方法形成的半導體 裝置。 2 2 . —種用以蝕刻在基板上有至少一矽化鍺層的堆疊 之裝置,包括: 一處理室; 一氣體源; 一供應源; 一溫度控制裝置,用以控制該基板的溫度; -27- (4) 200539345 電腦可讀密碼,用以將鈾刻劑氣體從該氣體源提供到 該處理室內,其中該鈾刻劑氣體包括HBr,惰性稀釋劑, 及在〇2和N2之中的至少一者; 電腦可讀密碼,用以將該基板冷卻到低於40 °C的溫 度;及 電腦可讀密碼,用以使用該供能源將該蝕刻劑氣體轉 換成電漿以蝕刻該矽化鍺層。 -28-
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TWI569310B (zh) * | 2010-09-21 | 2017-02-01 | 應用材料股份有限公司 | 用以於基材上形成層之方法 |
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WO2005091338A3 (en) | 2005-12-08 |
CN1954416A (zh) | 2007-04-25 |
WO2005091338A2 (en) | 2005-09-29 |
JP2007529904A (ja) | 2007-10-25 |
TWI456650B (zh) | 2014-10-11 |
JP4777337B2 (ja) | 2011-09-21 |
KR20060131997A (ko) | 2006-12-20 |
US20050205862A1 (en) | 2005-09-22 |
KR101191699B1 (ko) | 2012-10-16 |
US7682985B2 (en) | 2010-03-23 |
CN100530566C (zh) | 2009-08-19 |
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