CN1954416A - 双掺杂多晶硅及锗化硅的蚀刻 - Google Patents

双掺杂多晶硅及锗化硅的蚀刻 Download PDF

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CN1954416A
CN1954416A CNA2005800156057A CN200580015605A CN1954416A CN 1954416 A CN1954416 A CN 1954416A CN A2005800156057 A CNA2005800156057 A CN A2005800156057A CN 200580015605 A CN200580015605 A CN 200580015605A CN 1954416 A CN1954416 A CN 1954416A
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C·R·科伊茨佐波洛斯
Y·Y·亚达姆斯
Y·米亚莫托
Y·K·塔洛
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Abstract

提供了一种用于在处理室中蚀刻衬底上的具有至少一个锗化硅层的叠层的方法。提供了锗化硅的蚀刻。将蚀刻剂气体提供到处理室中，其中蚀刻剂气体包括HBr、惰性稀释剂、以及O2与N2中的至少一种。将衬底冷却到40℃以下的温度。将蚀刻剂气体转换成等离子体，以蚀刻锗化硅层。

Description

双掺杂多晶硅及锗化硅的蚀刻
技术领域
本发明涉及半导体器件。更具体的，本发明身兼具有掺杂多晶硅和锗化硅叠层的半导体器件。
背景技术
形成多晶硅的掺杂和未掺杂区域以及锗化硅(SiGe)的膜叠层用于形成半导体器件的栅电极。
发明内容
为了实现前述及根据本发明的目的，提供一种用于在处理室中蚀刻衬底上的具有至少一个锗化硅层的叠层的方法。提供了锗化硅蚀刻。将蚀刻剂气体提供到处理室中，其中蚀刻剂气体包括HBr、惰性稀释剂，以及O2和N2中的至少一种。衬底被冷却到40℃以下的温度。将蚀刻剂气体转换成等离子体以蚀刻锗化硅层。
在本发明的另一形式中，提供一种用于蚀刻衬底上的多晶硅层的方法，其中多晶硅层具有至少一个掺杂区域。将衬底放置在处理室中。将蚀刻剂气体提供到处理室中，其中蚀刻剂气体包括N2、SF6，以及CHF3和CH2F2中的至少一种。将蚀刻剂气体转换成等离子体以蚀刻多晶硅层。
在本发明的另一形式中，提供一种用于蚀刻衬底上的具有至少一个锗化硅层的叠层的装置。该装置包括处理室、气体源、激励源、用于控制衬底温度的温度控制装置、和控制器。控制器包括具有计算机可读代码的计算机可读媒介，用于从气体源将蚀刻剂气体提供到处理室中，其中蚀刻剂气体包括HBr、惰性稀释剂，以及O2和N2中的至少一种，计算机可读代码用于将衬底冷却到40℃以下的温度，且计算机可读代码利用激励源将蚀刻剂气体转换成蚀刻锗化硅层的等离子体。
下面将在本发明的详细说明中并结合附图更详细地描述本发明的这些和其他特征。
附图说明
借助于示例而非限制性方式说明本发明，在附图的各图中相同的参考数字表示相同元件，且其中：
图1是用于形成可用于栅电极的蚀刻叠层的高级流程图。
图2是形成叠层的更详细流程图。
图3A-3B是具有形成在衬底上的栅氧化层304的膜叠层的示意性截面图。
图4是蚀刻叠层的更详细流程图。
图5是可用于本发明优选实施例中的处理室的截面图。
图6A和6B示出了适合实现控制器的计算机系统。
图7A-D是已蚀刻的膜叠层的截面图。
具体实施方式
现在将参考附图所示的几个优选实施例详细描述本发明。在以下描述中，为了彻底理解本发明而阐明许多具体细节。然而，对于本领域技术人员来说很明显的是，可以在没有这些具体细节的一些或全部的情况下实践本发明。在其他实例中，为了避免混淆本发明，不再详细描述已知的工艺步骤和/或结构。
为了便于理解，图1是用于形成可用于栅电极的蚀刻膜叠层的高级流程图。形成叠层(步骤104)。蚀刻叠层(步骤108)。图2是形成叠层(步骤104)的更详细流程图。形成栅氧化层(步骤204)。图3A是具有形成于衬底308上的栅氧化层304的膜叠层的截面图。在栅氧化层304上形成硅籽晶层312(步骤208)。在栅氧化层304上形成锗化硅(SiGe)层316(步骤212)。在SiGe层316上形成多晶硅层320(步骤216)。多晶硅层320包括双掺杂层和未掺杂层324。双掺杂层包括包括掺杂区域328和未掺杂区域322。可以使用各种结构的掺杂区域和未掺杂区域。通常，多晶硅层320的最重掺杂区域可以靠近掺杂区域328的顶部，形成从具有最重掺杂区域的顶部到具有最轻掺杂或未掺杂区域的多晶硅层底部的梯度。重掺杂区域位于多晶硅层的顶部。掺杂水平在更高的深度处降低且多晶硅最终在更高深度处成为未掺杂的。在双掺杂多晶硅层320上设置抗反射涂层(ARC)332，例如底部抗反射涂层(BARC)(步骤220)。在ARC层332上形成光致抗蚀剂掩模336(步骤224)。
在叠层的一个示例中，栅氧化层304可以约厚1.5nm。硅籽晶层312可以约厚10nm。SiGe层316可以约厚20nm。双掺杂多晶硅层320可以约厚100nm。双掺杂多晶硅层320的最重掺杂区域328可以具有50-70nm的深度。ARC层332可以约厚100nm。193nm光致抗蚀剂掩模可以约厚190nm。
蚀刻这种叠层所具有的额外困难在于，掺杂多晶硅区域的蚀刻特性不同于未掺杂多晶硅区域的蚀刻特性。结果，用于对未掺杂多晶硅区域提供垂直蚀刻轮廓的蚀刻工艺会在掺杂多晶硅区域中提供底切。在另一示例中，可对掺杂多晶硅区域提供垂直蚀刻轮廓的蚀刻会对未掺杂多晶硅区域提供锥形轮廓或足形。
双掺杂多晶硅层320下面的SiGe层316具有不同于双掺杂多晶硅层320的蚀刻性能。SiGe层316不同的蚀刻性能以及SiGe层316和硅籽晶层312的薄度增加了额外的蚀刻困难。在这些困难中，提供双掺杂多晶硅层320的垂直蚀刻的蚀刻工艺会在SiGe层316中引起底切或者在硅籽晶层312中形成足形。由SiGe层和籽晶层的薄度引起困难的部分原因在于，更加难以对这种薄层进行单独的蚀刻步骤。使用单个蚀刻步骤来蚀刻SiGe和籽晶硅层。由于叠层底部附近的尺寸有助于限定栅极长度，因此垂直蚀刻是很重要的，甚至在靠近叠层底部更加重要。因此底切或足形的形成将改变栅极长度。
此外，光致抗蚀剂优选为193nm或下一代抗蚀剂，其比老一代抗蚀剂更柔软。因此本发明的蚀刻必须更有选择性且还提供一些钝化以便在不提供太多钝化的情况下保护光致抗蚀剂蚀刻掩模，这将引起蚀刻停止。
图4是叠层蚀刻步骤(步骤108)更详细的流程图。修整光致抗蚀剂掩模(步骤404)。这里可以使用如下所述的新型修整工艺来减小光致抗蚀剂掩模的临界尺寸。蚀刻ARC层，在本实施例中为BARC(步骤408)。这里可以使用常规BARC蚀刻工艺来蚀刻穿通BARC层。
接着，使用穿透性蚀刻(break through etch)以便蚀刻穿通由多晶硅层320的未掺杂区域322和掺杂区域328形成的双掺杂区域的至少一部分(步骤412)。同时蚀刻多晶硅层顶部处的未掺杂区域322和掺杂区域328。在本实施例中，穿透性蚀刻提供蚀刻剂气体，该蚀刻剂气体包括N2、SF6，以及CHF3和CH2F2中的至少一种。蚀刻剂气体转换成等离子体，将其用于蚀刻穿通多晶硅层320的掺杂区域328和未掺杂区域322。虽然穿透性蚀刻意在蚀刻穿通形成于多晶硅上的自然氧化物，但本步骤中使用的穿透性蚀刻用于同时蚀刻穿通形成于双掺杂多晶硅上的自然氧化物和双掺杂多晶硅层的最重掺杂区域。本发明的穿透性蚀刻提供了最小的掺杂/未掺杂轮廓附加产物(loading result)，以便蚀刻具有相同蚀刻特性的掺杂和未掺杂区域，从而使掺杂和未掺杂的轮廓看起来相似。
穿透性蚀刻之后进行用于蚀刻穿通未掺杂多晶硅层324的第一主蚀刻(步骤416)。在本实施例中，通过未掺杂多晶硅层的第一主蚀刻使用包括Cl2、HBr、O2和CF4中的至少之一的蚀刻剂气体。该蚀刻步骤可以用于将部件蚀刻到SiGe层316。已经发现，该蚀刻工艺对栅氧化物具有低选择性，因此期望的是在蚀刻部件到达栅氧化物之前停止穿透性蚀刻。可以利用干涉仪终点(interferometer endpoint)将部件蚀刻到距栅氧化层304约40nm的距离。并且，可以利用发光终点在多晶硅/SiGe界面处停止蚀刻。
然后在第一主蚀刻之后进行对蚀刻停止层具有更高选择性的第二主蚀刻(步骤420)，该蚀刻停止层是栅氧化层。在本实施例中，第二主蚀刻使用由HBr和O2构成的蚀刻剂气体。第二主蚀刻用于高选择性地蚀刻多晶硅层、SiGe层和硅籽晶层。
在第二主蚀刻到达蚀刻停止层之后进行过蚀刻步骤(步骤424)以完成SiGe层和硅籽晶层的蚀刻。因此，在本实施例中SiGe蚀刻用作多晶硅过蚀刻步骤，以完成多晶硅层320、SiGe层和硅籽晶层的蚀刻。在本实施例中，SiGe层和硅籽晶层的蚀刻使用由HBr、He和O2构成的蚀刻剂气体。该过蚀刻用于完成蚀刻并清洗残渣。已经发现，通过在低于40℃的温度下进行该蚀刻提供了意想不到的效果，即其提供了垂直蚀刻轮廓而没有对SiGe和硅籽晶层形成底切、弓形或形成足形。
在超过几个月的时间里进行了实验以尝试找到在蚀刻双掺杂多晶硅层、SiGe层和籽晶层时提供垂直蚀刻轮廓的工艺。一直没有找到提供期望效果的蚀刻工艺，直到在SiGe蚀刻期间使用低于40℃的较低工艺温度的实验，出乎意料地提供了期望的轮廓而没有底切、弓形或形成足形。
通常，每个蚀刻步骤都可以提供有过蚀刻步骤。如果使用蚀刻监控器来确定终点的到来，则可以使用过蚀刻步骤提供一段时间的额外蚀刻，以便在经过终点后蚀刻一个确定数量。
例1
在本发明的示例中，形成叠层。可以使用图2所述的步骤形成叠层，以形成图3A所示的叠层。在本例中，栅氧化层304厚1.5nm。硅籽晶层312厚10nm。SiGe层316厚20nm。双掺杂多晶硅层厚100nm。ARC层332厚100nm。193光致抗蚀剂掩模336厚190nm。然后将衬底308放置在处理室中。
图5是本发明优选实施例中使用的处理室500的截面图。在本例中，处理室包括由加利福尼亚州弗里蒙特的Lam Research Corporation提供的2300 Versys硅。等离子体处理室500可以包括电感线圈504、下电极508、气体源510和排气泵520。在等离子体处理室500中，衬底308放置在下电极508上。下电极508并入合适的衬底夹持机构(例如，静电、机械夹具，等等)，用于支撑衬底308。反应器顶部528并入电介质窗口。室顶528、室壁552和下电极508限定了封闭的等离子体容积540。气体由气体源510通过气体入口543提供到封闭的等离子体容积并由排气泵520从封闭的等离子体容积排出。排气泵520形成等离子体处理室的气体出口。第一RF源544电连接到线圈504。第二RF源548电连接到下电极508。在本实施例中，第一和第二RF源544、548包括13.56MHz的电源。将RF电源连接到电极的不同组合也是可以的。将控制器535可控制地连接到第一RF源544、第二RF源548、排气泵520和气体源510。衬底冷却系统包括冷却冷却剂的冷却器552和将冷却剂从冷却器552输送到并经过下电极508然后回到冷却器552的流体输送装置556。已冷却的下电极508使衬底冷却。此外，将加热器560提供并设置在下电极内部以加热衬底580。加热器560和衬底冷却系统以及控制器535能够充分控制温度，以便在不同步骤提供不同的衬底温度，如下面提供的示例。
图6A和6B示出了计算机系统800，其适于实现用于本发明实施例中的控制器535。图6A示出了计算机系统的一种可能的物理形式。当然，计算机系统可以具有许多物理形式，从集成电路、印刷电路板和小型手持装置到大型超级计算机。计算机系统800包括监控器802、显示器804、外壳806、磁盘驱动器808、键盘810和鼠标812。磁盘814是用于将数据传输到计算机系统800或从计算机系统800传输数据的计算机可读媒介。
图6B是计算机系统800的框图示例。连接到系统总线820的是各种子系统。处理器822(也称作中央处理单元或CPU)耦合到存储装置，包括存储器824。存储器824包括随机存取存储器(RAM)和只读存储器(ROM)。如本领域已知的，ROM用于单向传输数据和指令给CPU和RAM通常用于以双向方式传输数据和指令。所有这些类型的存储器可以包括下述任何合适的计算机可读媒介。固定盘826也双向耦合到CPU 822；其提供附加数据存储容量并且也可以包括下述任何计算机可读媒介。固定盘826可以用于存储程序、数据等且通常是比主存储器慢的辅助存储媒介(例如硬盘)。将意识到，在适当的情况下，保存在固定盘826内的信息可以以标准形式被合并作为存储器824中的虚拟存储器。可移动盘814可以是任何下述计算机可读媒介的一种形式。
CPU 822还耦合到各种输入/输出装置，例如显示器804、键盘810、鼠标812和扬声器830。通常，输入/输出装置可以是：视频显示器、轨迹球、鼠标、键盘、麦克风、触控式显示器、传感器读卡器、磁带或纸带读取器、输入板、触针、语音或手写识别器、生物学阅读器或其他计算机。CPU 822使用网络接口840可任意耦合到另一计算机或远程通信网络。通过这种网络接口，可以预期，CPU在进行上述方法步骤期间可以从网络接收信息，或者可以将信息输出到网络。此外，本发明的方法实施例可以单独在CPU 822上执行或者可以在诸如互联网的网络上结合共享部分工艺的远程CPU执行。
此外，本发明的实施例还涉及具有计算机可读媒介的计算机存储产品，该计算机可读媒介上具有用于进行各种计算机执行操作的计算机代码。媒介和计算机代码可以是为本发明目的专门设计并构造的那些媒介和计算机代码，或者可以是计算机软件领域的技术人员已知并可用的类型。计算机可读媒介的例子包括但不限于：磁性媒介，例如硬盘、软盘和磁带；光学媒介，例如CD-ROM和全息装置；磁光媒介，例如光磁软盘；和为存储和执行程序代码专门配置的硬件装置，例如特专用集成电路(ASIC)、可编程逻辑器件(PLD)以及ROM和RAM装置。计算机代码的例子包括例如由编译器产生的机器代码和文件，该文件包括由利用翻译器的计算机执行的高级代码。计算机可读媒介还可以是通过包含于载波中的计算机数据信号传输并表示将由处理器执行的指令序列的计算机代码。
光致抗蚀剂修整可以在处理室500内完成或者在将衬底放入处理室500之前完成。在修整工艺(步骤404)的优选实施例中，提供HBr、O2和CHF3用于在处理室内修整光致抗蚀剂。在该例子中，修整气体是30sccm的HBr，30sccm的O2，和40sccm的CHF3。处理室中的压力为5mTorr。施加到处理室的TCP功率是250瓦。偏置电压为70伏。在静电夹具处提供8Torr的氯后部压力。提供60℃的静电夹具温度。该步骤保持44秒。本优选实施例提供了改进的光致抗蚀剂修整。
然后将BARC层开口。可以使用常规BARC开口步骤。BARC蚀刻可以在处理室500内完成或者在将衬底放入处理室500之前完成。这种BARC开口工艺(步骤408)可以使用Cl2、O2和He用于BARC蚀刻。
对于穿透性步骤(步骤412)，提供包括N2、SF6、和CHF3与CH2F2中至少一种的蚀刻剂气体。在本例中，蚀刻剂气体为100sccm的CHF3、50sccm的N2和20sccm的SF6。处理室中的压力为5mTorr。提供到处理室的TCP功率为275瓦。偏置电压为135伏。在静电夹具处提供8Torr的氦后部压力。提供60℃的静电夹具温度。该步骤保持23秒。
对于第一主蚀刻步骤(步骤416)，提供包括Cl2、HBr、O2和CF4中至少一种的蚀刻剂气体。在本例中，蚀刻剂气体为50sccm的Cl2、250sccm的HBr、50sccm的CF4和5sccm的O2。处理室中的压力为10mTorr。提供到处理室的TCP功率为600瓦。偏置电压为125伏。提供8Torr的氦后部压力。提供60℃的静电夹具温度。该步骤保持17秒。
对于第二主蚀刻步骤(步骤420)，提供包括HBr、惰性稀释剂、和O2与N2中至少一种的蚀刻剂气体。在本例中，蚀刻剂气体为180sccm的HBr和5sccm的O2。处理室中的压力为6mTorr。提供到处理室的TCP功率为350瓦。偏置电压为65伏。提供8Torr的氯后部压力。提供60℃的静电夹具温度。该步骤保持14秒。
对于过蚀刻步骤(步骤424)，该过蚀刻步骤也是SiGe蚀刻，提供包括HBr、惰性稀释剂、和O2与N2中至少一种的蚀刻剂气体。在本例中，蚀刻剂气体为133sccm的HBr和2sccm的O2。处理室中的压力为80mTorr。提供到处理室的TCP功率为500瓦。偏置电压为210伏。提供8Torr的氦后部压力。提供30℃的静电夹具温度。该步骤保持72秒。由于低处理温度，SiGe蚀刻步骤非常稳固并且能够延长该步骤时间而不横向侵蚀SiGe层。也可以将诸如氦气的惰性气体添加到蚀刻剂气体中。在本例中，添加267sccm的He。本发明装置的加热器和冷却器能够提供需要的温度控制，其能够在各步骤之间将衬底温度从60℃改变到30℃。加热器和冷却器提供快速改变温度的能力。
已经发现该示例对晶片提供均匀的蚀刻。
其他示例
表1提供了用于穿透性蚀刻的优选、更优选和最优选范围。
表1
优选范围 更优选范围 最优选范围
N2 20-100sccm 25-75sccm 40-60sccm
SF6 5-50sccm 10-30sccm 15-25sccm
CHF3 30-200sccm 50-150sccm 75-125sccm
TCP 100-1000瓦 150-600瓦 200-400瓦
偏置电压 25-200伏 50-175伏 100-150伏
压力 1-40mTorr 3-20mTorr 5-10mTorr
CHF3∶SF6流量比 50∶1-2∶1 20∶1-3∶1 10∶1-3∶1
CHF3∶N2流量比 5∶1-1∶1 4∶1-1∶1 3∶1-2∶1
温度 10-90℃ 25-80℃ 30-60℃
表2提供了用于第一主蚀刻的优选、更优选和最优选范围。
表2
优选范围 更优选范围 最优选范围
Cl2 20-100sccm 25-75sccm 40-60sccm
CF4 10-100sccm 30-70sccm 40-60sccm
HBr 100-500sccm 150-400sccm 200-300sccm
O2 1-20sccm 2-15sccm 3-10sccm
TCP 100-1000瓦 300-800瓦 500-700瓦
偏置电压 50-200伏 100-150伏 115-135伏
压力 1-40Torr 3-20mTorr 5-15mTorr
HBr∶CF4流量比 10∶1-2∶1 8∶1-3∶1 6∶1-4∶1
HBr∶O2流量比 100∶1-10∶1 80∶1-20∶1 60∶1-40∶1
HBr∶Cl2流量比 10∶1-2∶1 8∶1-3∶1 6∶1-4∶1
温度 10-90℃ 25-70℃ 30-60℃
表3提供了用于第二主蚀刻的优选、更优选和最优选范围。
表3
优选范围 更优选范围 最优选范围
O2 1-20sccm 2-15sccm 3-10sccm
HBr 100-400sccm 150-300sccm 160-200sccm
TCP 100-600瓦 200-500瓦 300-400瓦
偏置电压 20-110伏 40-100伏 60-90伏
压力 1-20mTorr 3-15mTorr 5-10mTorr
HBr∶O2流量比 100∶1-10∶1 80∶1-20∶1 50∶1-30∶1
温度 10-90℃ 15-70℃ 20-60℃
如果使用N2代替O2，则N2将具有与上述示例中O2相同的流量和流量比。并且，除氧气外可以使用相同量的氮气。
表4提供了用于过蚀刻多晶硅的优选、更优选和最优选范围，其蚀刻SiGe和硅籽晶层(SiGe蚀刻)。
表4
优选范围 更优选范围 最优选范围
O2 0.5-20sccm 1-10sccm 1-5sccm
HBr 80-300sccm 100-200sccm 120-150sccm
TCP 100-1000瓦 200-750瓦 400-600瓦
偏置电压 100-400伏 150-300伏 180-250伏
压力 20-100mTorr 40-90mTorr 60-80mTorr
HBr∶O2流量比 200∶1-10∶1 100∶1-20∶1 80∶1-30∶1
温度 0-40℃ 10-35℃ 20-30℃
如果使用N2代替O2，则N2将具有与上述示例中O2相同的流量和流量比。并且，除氧气外可以使用相同量的氮气。
在以上示例中，蚀刻剂气体基本上由特定气体成分构成。在其他实施例中，可以使用其他或额外的气体成分。
在其他示例中，具有5mTorr压力、300瓦TCP功率、53伏偏压、60℃夹具温度的穿透性方法可以使用CH2F2、SF6和N2的穿透性混合气体。在一个示例中，穿透性混合气体包括30sccm的CH2F2、20sccm的SF6和50sccm的N2，将其保持37秒。在另一个示例中，穿透性混合气体包括40sccm的CH2F2、20sccm的SF6和50sccm的N2，将其保持52秒。虽然这些方法提供了良好的效果，但已经发现，当使用CH2F2时出现的工艺窗小于使用CH3F时的工艺窗。已经发现，将TCP功率增大到至少600瓦有助于减小颈缩现象。
通过60℃的实验，已经发现在SiGe蚀刻期间降低HBr/He之比可以降低了SiGe层的弓形，但会在硅籽晶层中引起小的足形。还发现延长SiGe蚀刻步骤增大了SiGe轮廓的弓形。
已经发现，在SiGe蚀刻步骤期间，将衬底温度降到40℃以下，优选至约30℃，在籽晶硅、多晶硅和SiGe层的蚀刻中得到了具有大致相同蚀刻特性的各个蚀刻。降低衬底温度提供了非常稳定的工艺，其中参数的轻微改变不会显著增大底切、弓形或足形的形成。因此在SiGe蚀刻期间减小温度允许工艺参数的一些改变而不影响被蚀刻部件的垂直轮廓。可以通过使冷却器552将冷却液体冷却到20℃来实现将衬底保持在30℃。冷却液体经过下电极508以便将下电极冷却到20℃，其将衬底308冷却到20℃。然后使用加热器560将衬底加热到30℃。
本发明的其他实施例将穿透性蚀刻代替第一主蚀刻，由此扩展穿透性蚀刻步骤并删除第一主蚀刻。
其他实施例可以在小于40℃的温度下进行第二主蚀刻，以获得更稳定的结果。本发明的蚀刻还提供足够的钝化以便在不使蚀刻停止的情况下防止底切。在另一示例中，在第二主蚀刻期间提供少量的Cl2，以消除或减少在第二主蚀刻期间形成的任何足形。
还发现本发明的蚀刻提供了减小的线边缘粗糙度。认为本发明在修整步骤期间允许更多的钝化，其减小了侧壁的粗糙度。
本发明的其他实施例可以单独提供本发明的SiGe蚀刻，来取代多晶硅的过蚀刻。
为了便于理解，图7A-7D示意性地示出了使用各工艺蚀刻的各个轮廓，其中图7A-C是使用现有技术的工艺进行蚀刻的轮廓示意图且图7D是使用本发明的工艺进行蚀刻的轮廓示意图。图7A是衬底708上的栅氧化层上的叠层示意图，其中叠层包括硅籽晶层712、SiGe层716和具有掺杂和未掺杂区域的多晶硅层722。本例中现有技术的蚀刻工业产生了弓形SiGe部分722和籽晶硅足形724。在本例中弓形和足形的组合不会产生任何CD增益。图7B是通过现有技术蚀刻的叠层示意图，其产生了较小的弓形SiGe部分732和较大的籽晶硅足形734，其中弓形和足形的组合引起了CD增益。图7C是通过现有技术蚀刻的叠层示意图，其产生了垂直SiGe部分和籽晶硅足形744，其中足形引起了CD增益。图7D是使用本发明蚀刻的叠层示意图，其产生了垂直的SiGe层和籽晶硅蚀刻。
虽然已经依照几个优选实施例描述了本发明，但存在的改变、置换、修改和各种替代性等价物都落入本发明的范围内。还应当注意，存在完成本发明方法和装置的许多可选方式。因此意在将以下所附权利要求解释为包括所有这些落入本发明真实精神和范围内的改变、置换、修改和各种替代性等价物。

Claims (18)

1、一种用于在处理室中蚀刻衬底上的具有至少一个锗化硅层的叠层的方法，包括提供锗化硅蚀刻，其包括：
将蚀刻剂气体提供到处理室中，其中蚀刻剂气体包括HBr、惰性稀释剂、以及O2与N2中的至少一种；
将衬底冷却到40℃以下的温度；并且
将蚀刻剂气体转换成等离子体，以蚀刻锗化硅层。
2、如权利要求1所述的方法，其中该叠层还包括锗化硅层上的多晶硅层，其中多晶硅层的至少一个区域是掺杂的，还包括提供多晶硅层的穿透性蚀刻，其包括：
将蚀刻剂气体提供到该处理室中，其中蚀刻剂气体包括N2、SF6、以及CHF3与CH2F2中的至少一种；并且
将蚀刻剂气体转换成等离子体，以蚀刻多晶硅层。
3、如权利要求1-2任一项所述的方法，还包括提供多晶硅主蚀刻，其包括：
提供具有Cl2、HBr、CF4和O2中至少一种的蚀刻剂气体；并且
将蚀刻剂气体转换成等离子体，以蚀刻多晶硅层。
4、如权利要求2-3任一项所述的方法，其中蚀刻锗化硅层和多晶硅层提供垂直轮廓。
5、如权利要求1-4任一项所述的方法，其中该叠层还包括锗化硅层下面的籽晶硅层，其中该SiGe蚀刻蚀刻穿通该籽晶硅层。
6、如权利要求1-5任一项所述的方法，其中籽晶硅层和锗化硅层的组合厚度在10至50纳米之间。
7、如权利要求1-6任一项所述的方法，还包括在叠层上提供光致抗蚀剂掩模。
8、如权利要求7所述的方法，其中该光致抗蚀剂掩模是193或更高一代的光致抗蚀剂。
9、如权利要求2-4任一项所述的方法，其中该多晶硅层具有至少一个未掺杂区域。
10、如权利要求2-4和9任一项所述的方法，其中籽晶硅层和锗化硅层的组合厚度小于多晶硅层厚度的一半。
11、一种通过权利要求1-10任一项的方法形成的半导体器件。
12、一种蚀刻在衬底上的多晶硅层的方法，其中该多晶硅层具有至少一个掺杂区域，包括：
将衬底放置在处理室中；
将蚀刻剂气体提供到该处理室中，其中该蚀刻剂气体包括N2、SF6、以及CHF3与CH2F2中至少一种；并且
将蚀刻剂气体转换成等离子体，以蚀刻该多晶硅层。
13、如权利要求12所述的方法，还包括提供多晶硅主蚀刻，其包括：
提供具有Cl2、HBr、CF4和O2中至少一种的蚀刻剂气体；并且
将蚀刻剂气体转换成等离子体，以蚀刻多晶硅层。
14、如权利要求12-13任一项所述的方法，还包括在该叠层上提供光致抗蚀剂掩模。
15、如权利要求14所述的方法，该光致抗蚀剂掩模是193或更高一代的光致抗蚀剂。
16、如权利要求12-15任一项所述的方法，其中该多晶硅层具有至少一个未掺杂区域。
17、一种通过权利要求12-16任一项的方法形成的半导体器件。
18、一种用于蚀刻衬底上的具有至少一个锗化硅层的叠层的装置，其包括：
处理室；
气体源；
激励源；
温度控制装置，用于控制衬底的温度；
控制器，其中该控制器包括计算机可读媒介，该计算机可读媒介包括：
用于将蚀刻剂气体从该气体源提供到该处理室中的计算机可读代码，其中该蚀刻剂气体包括HBr、惰性稀释剂、以及O2与N2中的至少一种；
用于将该衬底冷却到40℃以下温度的计算机可读代码；以及
用于利用该激励源将该蚀刻剂气体转换成等离子体以蚀刻该锗化硅层的计算机可读代码。
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CN104658896A (zh) * 2013-11-19 2015-05-27 中芯国际集成电路制造(上海)有限公司 蚀刻方法、半导体器件
CN104658896B (zh) * 2013-11-19 2017-12-29 中芯国际集成电路制造(上海)有限公司 蚀刻方法、半导体器件
CN112470258A (zh) * 2018-07-20 2021-03-09 朗姆研究公司 用于纳米线的选择性蚀刻

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CN100530566C (zh) 2009-08-19
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US20050205862A1 (en) 2005-09-22
TWI456650B (zh) 2014-10-11
US7682985B2 (en) 2010-03-23
JP2007529904A (ja) 2007-10-25
KR101191699B1 (ko) 2012-10-16
KR20060131997A (ko) 2006-12-20
WO2005091338A2 (en) 2005-09-29
TW200539345A (en) 2005-12-01

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