TW200511498A - Method of manufacturing a substrate, having a porous dielectric layer and air gaps, and a substrate - Google Patents

Method of manufacturing a substrate, having a porous dielectric layer and air gaps, and a substrate

Info

Publication number
TW200511498A
TW200511498A TW093114544A TW93114544A TW200511498A TW 200511498 A TW200511498 A TW 200511498A TW 093114544 A TW093114544 A TW 093114544A TW 93114544 A TW93114544 A TW 93114544A TW 200511498 A TW200511498 A TW 200511498A
Authority
TW
Taiwan
Prior art keywords
substrate
metal lines
layer
air gaps
diffusion barrier
Prior art date
Application number
TW093114544A
Other languages
English (en)
Inventor
Roel Daamen
Greja Johanna Adriana Maria Verheijden
Original Assignee
Koninkl Philips Electronics Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv filed Critical Koninkl Philips Electronics Nv
Publication of TW200511498A publication Critical patent/TW200511498A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
TW093114544A 2003-05-26 2004-05-21 Method of manufacturing a substrate, having a porous dielectric layer and air gaps, and a substrate TW200511498A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP03101507 2003-05-26

Publications (1)

Publication Number Publication Date
TW200511498A true TW200511498A (en) 2005-03-16

Family

ID=33462211

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093114544A TW200511498A (en) 2003-05-26 2004-05-21 Method of manufacturing a substrate, having a porous dielectric layer and air gaps, and a substrate

Country Status (7)

Country Link
US (1) US20070035816A1 (zh)
EP (1) EP1631985A1 (zh)
JP (1) JP2007523465A (zh)
KR (1) KR20060014425A (zh)
CN (1) CN1795553A (zh)
TW (1) TW200511498A (zh)
WO (1) WO2004105122A1 (zh)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8263316B2 (en) 2004-10-01 2012-09-11 Rohm And Haas Electronic Materials Llc Electronic device manufacture
JP4679193B2 (ja) * 2005-03-22 2011-04-27 株式会社東芝 半導体装置の製造方法及び半導体装置
KR100652317B1 (ko) * 2005-08-11 2006-11-29 동부일렉트로닉스 주식회사 반도체 소자의 금속 패드 제조 방법
WO2007119188A2 (en) * 2006-04-13 2007-10-25 Koninklijke Philips Electronics N. V. Micro device with microtubes
US7691712B2 (en) * 2006-06-21 2010-04-06 International Business Machines Corporation Semiconductor device structures incorporating voids and methods of fabricating such structures
KR100772835B1 (ko) * 2006-07-12 2007-11-01 동부일렉트로닉스 주식회사 에어갭을 포함하는 반도체 소자 및 그 제조방법
US7790606B2 (en) * 2006-10-09 2010-09-07 Nxp B.V. Method of forming an interconnect structure
KR100853789B1 (ko) * 2006-11-27 2008-08-25 동부일렉트로닉스 주식회사 반도체 소자 및 그 제조 방법
KR100861839B1 (ko) * 2006-12-28 2008-10-07 동부일렉트로닉스 주식회사 반도체 소자의 금속 배선 형성 방법
KR100843233B1 (ko) 2007-01-25 2008-07-03 삼성전자주식회사 배선층의 양측벽에 인접하여 에어갭을 갖는 반도체 소자 및그 제조방법
CN101373733B (zh) * 2007-08-21 2011-11-30 中芯国际集成电路制造(上海)有限公司 集成电路器件结构形成方法及相应结构
JP2009123775A (ja) * 2007-11-12 2009-06-04 Rohm Co Ltd 半導体装置および半導体装置の製造方法
US8310053B2 (en) 2008-04-23 2012-11-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing a device with a cavity
KR101382564B1 (ko) 2008-05-28 2014-04-10 삼성전자주식회사 에어갭을 갖는 층간 절연막의 형성 방법
CN101604683B (zh) * 2008-06-11 2011-04-06 和舰科技(苏州)有限公司 一种用于互连的气隙结构及其制造方法
TWI470736B (zh) * 2008-08-26 2015-01-21 He Jian Technology Suzhou Co Ltd 一種用於互連的氣隙結構及其製造方法
JP5491077B2 (ja) 2009-06-08 2014-05-14 キヤノン株式会社 半導体装置、及び半導体装置の製造方法
US8456009B2 (en) * 2010-02-18 2013-06-04 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure having an air-gap region and a method of manufacturing the same
CN101982879A (zh) * 2010-10-15 2011-03-02 复旦大学 一种低介电常数介质与铜互连的结构及其集成方法
CN102768986A (zh) * 2012-07-04 2012-11-07 上海华力微电子有限公司 一种大马士革工艺空气间隔的制作方法
KR102002815B1 (ko) 2012-09-05 2019-07-23 삼성전자주식회사 반도체 장치 및 이의 제조 방법
KR101998788B1 (ko) 2013-04-22 2019-07-11 삼성전자주식회사 반도체 장치 및 그 제조 방법
KR102037830B1 (ko) 2013-05-20 2019-10-29 삼성전자주식회사 반도체 장치 및 그 제조 방법
KR102154112B1 (ko) 2013-08-01 2020-09-09 삼성전자주식회사 금속 배선들을 포함하는 반도체 장치 및 그 제조 방법
WO2016105344A1 (en) * 2014-12-22 2016-06-30 Intel Corporation Via self alignment and shorting improvement with airgap integration capacitance benefit
KR102334736B1 (ko) * 2015-12-03 2021-12-03 삼성전자주식회사 반도체 장치 및 그 제조 방법
US9812353B2 (en) 2015-12-03 2017-11-07 Samsung Electronics Co., Ltd. Semiconductor device and method of manufacturing the same
DE112017004206T5 (de) * 2016-08-25 2019-05-29 Sony Semiconductor Solutions Corporation Halbleitervorrichtung, bildaufnahmevorrichtung und verfahren zum herstellen einer halbleitervorrichtung
US10861739B2 (en) * 2018-06-15 2020-12-08 Tokyo Electron Limited Method of patterning low-k materials using thermal decomposition materials
KR102634459B1 (ko) * 2018-12-24 2024-02-05 삼성전자주식회사 반도체 장치 및 그 제조 방법

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5461003A (en) * 1994-05-27 1995-10-24 Texas Instruments Incorporated Multilevel interconnect structure with air gaps formed between metal leads
US5567982A (en) * 1994-09-30 1996-10-22 Bartelink; Dirk J. Air-dielectric transmission lines for integrated circuits
US6265321B1 (en) * 2000-04-17 2001-07-24 Chartered Semiconductor Manufacturing Ltd. Air bridge process for forming air gaps
TWI227043B (en) * 2000-09-01 2005-01-21 Koninkl Philips Electronics Nv Method of manufacturing a semiconductor device
JP2002110785A (ja) * 2000-09-27 2002-04-12 Sony Corp 半導体装置の製造方法

Also Published As

Publication number Publication date
US20070035816A1 (en) 2007-02-15
JP2007523465A (ja) 2007-08-16
EP1631985A1 (en) 2006-03-08
WO2004105122A1 (en) 2004-12-02
CN1795553A (zh) 2006-06-28
KR20060014425A (ko) 2006-02-15

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