TW200506597A - Semiconductor integrated circuit and inspection method thereof - Google Patents

Semiconductor integrated circuit and inspection method thereof

Info

Publication number
TW200506597A
TW200506597A TW093109723A TW93109723A TW200506597A TW 200506597 A TW200506597 A TW 200506597A TW 093109723 A TW093109723 A TW 093109723A TW 93109723 A TW93109723 A TW 93109723A TW 200506597 A TW200506597 A TW 200506597A
Authority
TW
Taiwan
Prior art keywords
memory
relief
semiconductor integrated
integrated circuit
data
Prior art date
Application number
TW093109723A
Other languages
English (en)
Inventor
Osamu Ichikawa
Original Assignee
Matsushita Electric Ind Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Ind Co Ltd filed Critical Matsushita Electric Ind Co Ltd
Publication of TW200506597A publication Critical patent/TW200506597A/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair
    • G11C29/4401—Indication or identification of errors, e.g. for repair for self repair
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0405—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals comprising complete test loop
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/1208—Error catch memory

Landscapes

  • Tests Of Electronic Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
TW093109723A 2003-04-10 2004-04-08 Semiconductor integrated circuit and inspection method thereof TW200506597A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003105990A JP3866216B2 (ja) 2003-04-10 2003-04-10 半導体集積回路およびその検査方法

Publications (1)

Publication Number Publication Date
TW200506597A true TW200506597A (en) 2005-02-16

Family

ID=33127905

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093109723A TW200506597A (en) 2003-04-10 2004-04-08 Semiconductor integrated circuit and inspection method thereof

Country Status (4)

Country Link
US (1) US7155643B2 (zh)
JP (1) JP3866216B2 (zh)
CN (1) CN100483559C (zh)
TW (1) TW200506597A (zh)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7257733B2 (en) * 2003-06-18 2007-08-14 Logicvision, Inc. Memory repair circuit and method
JP4514028B2 (ja) * 2004-05-20 2010-07-28 ルネサスエレクトロニクス株式会社 故障診断回路及び故障診断方法
US7254763B2 (en) * 2004-09-01 2007-08-07 Agere Systems Inc. Built-in self test for memory arrays using error correction coding
JP2006128635A (ja) * 2004-09-30 2006-05-18 Matsushita Electric Ind Co Ltd 半導体集積回路
DE102005001520A1 (de) * 2005-01-13 2006-07-27 Infineon Technologies Ag Integrierte Speicherschaltung und Verfahren zum Reparieren eines Einzel-Bit-Fehlers
JP2006236551A (ja) * 2005-01-28 2006-09-07 Renesas Technology Corp テスト機能を有する半導体集積回路および製造方法
JP2006252702A (ja) 2005-03-11 2006-09-21 Nec Electronics Corp 半導体集積回路装置及びその検査方法
JP2009099186A (ja) * 2007-10-16 2009-05-07 Panasonic Corp 半導体装置
US20090132876A1 (en) * 2007-11-19 2009-05-21 Ronald Ernest Freking Maintaining Error Statistics Concurrently Across Multiple Memory Ranks
US20100134690A1 (en) * 2008-12-03 2010-06-03 Sanyo Electric Co., Ltd. Television receiver
JP2010256130A (ja) * 2009-04-23 2010-11-11 Renesas Electronics Corp 半導体集積回路、および半導体集積回路のテスト方法
JP2012124774A (ja) * 2010-12-09 2012-06-28 Advantest Corp Ａｄ変換装置およびｄａ変換装置
CN102435935B (zh) * 2011-10-28 2016-06-01 上海华虹宏力半导体制造有限公司 扫描测试方法
CN102750989A (zh) * 2012-07-26 2012-10-24 上海宏力半导体制造有限公司 存储器内建自测方法以及存储器错误检查方法
KR102038036B1 (ko) * 2013-05-28 2019-10-30 에스케이하이닉스 주식회사 반도체 장치 및 반도체 장치를 포함하는 반도체 시스템
US9548137B2 (en) * 2013-12-26 2017-01-17 Intel Corporation Integrated circuit defect detection and repair
US9564245B2 (en) 2013-12-26 2017-02-07 Intel Corporation Integrated circuit defect detection and repair
KR102238706B1 (ko) * 2014-11-28 2021-04-09 삼성전자주식회사 반도체 메모리 장치 및 이를 포함하는 메모리 시스템
US10234507B2 (en) * 2016-07-20 2019-03-19 International Business Machines Corporation Implementing register array (RA) repair using LBIST
JP6570608B2 (ja) * 2017-12-21 2019-09-04 キヤノン株式会社 検査装置、撮像装置、電子機器および輸送装置
US11228380B2 (en) * 2019-10-29 2022-01-18 Keysight Technologies, Inc. Bit error ratio (BER) measurement including forward error correction (FEC) on back channel
US11320482B2 (en) * 2020-02-26 2022-05-03 Silicon Laboratories Inc. Secure scan entry

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5808947A (en) * 1995-08-21 1998-09-15 Sgs-Thomson Microelectronics, Inc. Integrated circuit that supports and method for wafer-level testing
JP2001043698A (ja) 1999-08-03 2001-02-16 Hitachi Ltd 内蔵メモリアレイの自己検査回路および自己検査方法
JP3893238B2 (ja) * 2000-07-14 2007-03-14 富士通株式会社 半導体記憶装置の不良解析装置
JP2002319298A (ja) * 2001-02-14 2002-10-31 Mitsubishi Electric Corp 半導体集積回路装置

Also Published As

Publication number Publication date
CN100483559C (zh) 2009-04-29
US20040205427A1 (en) 2004-10-14
JP3866216B2 (ja) 2007-01-10
JP2004310951A (ja) 2004-11-04
US7155643B2 (en) 2006-12-26
CN1536581A (zh) 2004-10-13

Similar Documents

Publication Publication Date Title
TW200506597A (en) Semiconductor integrated circuit and inspection method thereof
US7449909B2 (en) System and method for testing one or more dies on a semiconductor wafer
JP2570203B2 (ja) 半導体記憶装置
US5936900A (en) Integrated circuit memory device having built-in self test circuit with monitor and tester modes
DE60220511D1 (de) Verfahren und system zur optimierung der testkosten und deaktivierungsdefekte für scan- und bist-speicher
US6009026A (en) Compressed input/output test mode
US6408414B1 (en) Semiconductor device provided with a boundary-scan test circuit
US7808850B2 (en) Semiconductor device and system
WO2000028547A1 (fr) Dispositif de stockage a semi-conducteur et systeme de test
US7518936B2 (en) Semiconductor integrated circuit device and inspection method of the same
US8717838B1 (en) Method and apparatus for memory redundancy
US7482830B2 (en) Semiconductor device and method for testing semiconductor device
US7640467B2 (en) Semiconductor memory with a circuit for testing the same
US7706199B2 (en) Circuit and method for parallel test of memory device
US7394272B2 (en) Built-in self test for system in package
US20060059394A1 (en) Loop-back method for measuring the interface timing of semiconductor memory devices using the normal mode memory
KR100489999B1 (ko) 반도체 장치, 시스템, 및 메모리 액세스 제어 방법
KR100537115B1 (ko) 반도체 기억 장치
JP4375668B2 (ja) 半導体集積回路装置
JP2006277821A (ja) 半導体集積回路
US20050144525A1 (en) Method to test memories that operate at twice their nominal bandwidth
JP3709057B2 (ja) 半導体装置
JP2006092692A (ja) 半導体記憶装置および検査方法
KR100454251B1 (ko) 메모리 테스트 시간을 줄인 반도체 메모리 장치
JP2006114785A (ja) Ｄｒａｍ混載ａｓｉｃ，及びｄｒａｍ混載ａｓｉｃ設計方法