TW200425261A - Semiconductor substrate and manufacturing method therefor - Google Patents
Semiconductor substrate and manufacturing method therefor Download PDFInfo
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- TW200425261A TW200425261A TW093111750A TW93111750A TW200425261A TW 200425261 A TW200425261 A TW 200425261A TW 093111750 A TW093111750 A TW 093111750A TW 93111750 A TW93111750 A TW 93111750A TW 200425261 A TW200425261 A TW 200425261A
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- 239000000758 substrate Substances 0.000 title claims abstract description 62
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims abstract description 25
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 25
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910052732 germanium Inorganic materials 0.000 claims abstract description 15
- 150000002500 ions Chemical class 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims description 16
- 238000005468 ion implantation Methods 0.000 claims description 12
- 238000000926 separation method Methods 0.000 claims description 8
- 239000012530 fluid Substances 0.000 claims description 5
- 238000000137 annealing Methods 0.000 claims description 4
- 150000001875 compounds Chemical class 0.000 claims description 3
- 239000007789 gas Substances 0.000 claims description 3
- 239000007943 implant Substances 0.000 claims description 3
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 claims description 2
- 230000003068 static effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 8
- 239000001257 hydrogen Substances 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- -1 hydrogen ions Chemical class 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 229910052743 krypton Inorganic materials 0.000 description 1
- DNNSSWSSYDEUBZ-UHFFFAOYSA-N krypton atom Chemical compound [Kr] DNNSSWSSYDEUBZ-UHFFFAOYSA-N 0.000 description 1
- 229910052754 neon Inorganic materials 0.000 description 1
- GKAOGPIIYCISHV-UHFFFAOYSA-N neon atom Chemical compound [Ne] GKAOGPIIYCISHV-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 229910052724 xenon Inorganic materials 0.000 description 1
- FHNFHKCVQCLJFQ-UHFFFAOYSA-N xenon atom Chemical compound [Xe] FHNFHKCVQCLJFQ-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Toxicology (AREA)
- Health & Medical Sciences (AREA)
- Recrystallisation Techniques (AREA)
- Element Separation (AREA)
Description
(3) (3)200425261 火該黏合基底堆疊使該黏合基底堆疊於離子佈植層分離之 步驟爲佳。 根據本發明之一實施方式,該第三步驟以包含利用穩 定壓力或流體噴出物使該黏合基底堆疊於離子佈植層處分 離之步驟爲佳。 根據本發明之一實施方式,該第三步驟以包含利用於 離子佈植層中插入一構件使該黏合基底堆疊於離子佈植層 處分離之步驟爲佳。 根據本發明之一實施方式,該製造方法最好更包含一 步驟,該步驟移除第三步驟之後已被轉移至第二基底的殘 留於一部份砷化鎵層上之一部份離子佈植層。 根據本發明之一實施方式,該製造方法最好更包含一 步驟,該步驟平面化分離步驟中分離所得到之鍺構件表面 而於第一步驟中重複使用該鍺構件。 本發明之其他特色與優勢將由以下的描述加上所附圖 式而顯現,其中類似參考特性標示相同或相似的部分都在 其圖形中。 【實施方式】 參照所附圖式將描述本發明之實施方式。 圖1至圖7係用以解釋根據本發明之實施方式的半導 體基底製造方法之圖覽。在圖1所示的步驟中製備一鍺構 件1 1。然後,在圖2所示的步驟中,利用磊晶成長使一 砷化鎵層1 2形成於鍺構件1 1之表面上。由於鍺與砷化鎵 -6- (4) (4)200425261 之晶格常數間的不匹配很輕微,在該鍺構件1 1上可形成 一具有良好結晶性的砷化鎵層。磊晶成長則允許該砷化鎵 層具有均勻的厚度。 圖3所示的步驟中,氫離子係佈植於圖2中所示之砷 化鎵層1 2的表面。一離子佈植層1 3形成於砷化鎵層1 2 中,從而形成一第一基底10。除氫離子外,在佈植時稀 有氣體之離子例如氦、氖、氬、氪、氙、或類似者可單獨 或合倂使用之。雖然並未顯示,在離子佈植之前一隔絕層 形成於砷化鎵層1 2的表面。離子佈植層1 3可形成於鍺構 件1 1與砷化鎵層1 2至少其一之中。 圖4所示之步驟中,一第二基底20黏合於第一基底 10之表面以形成一黏合基底堆疊30。一矽基底或於其上 形成例如Si02層之絕緣層所得到之基底典型地適於作爲 該第二基底2 0。任何其他基底例如一絕緣基底(例如一 玻璃基底)也可能用於作爲該第二基底20。 圖5所示之步驟中,黏合基底堆疊30於離子佈植層 13處被分離爲二基底。該離子佈植層13具有高濃度的微 腔、微泡、扭曲、或缺陷,而比黏合基底堆疊3 0之其餘 部分更爲易脆。此分離可利用例如退火該黏合基底堆疊 3 〇而完成。或者,此分離之進行可由例如使用一液體的 方法。關於該方法,以利用形成一流體(液體或氣體)噴 出物並將該噴出物注入該分離層1 2的方法,利用流體之 穩定壓力的方法,或類似者爲佳。除噴出物注入方法外, 一種使用水作爲流體的方法被稱爲水噴出物方法。或者, (5) (5)200425261 該分離可利用插入一固體構件例如楔體至分離層1 2中。 圖6所示之步驟中,利用一蝕刻劑或類似者移除第二 基底20之砷化鎵層12b上殘留的離子佈植層13b。此時 ,砷化鎵層1 2 b最好是用來作爲蝕刻停止層。然後,氫退 火步驟、拋光步驟、或類似者可因平面化第二基底之需求 而進行。 經由上述的操作,即得到圖7中所示之半導體基底 40。圖7中所顯示之半導體基底40在其表面上具有薄砷 化鎵層1 2b。以「薄砷化鎵層」表示是想意謂這層比一般 半導體基底更薄。要展現作爲半導體裝置的優勢,該砷化 鎵層12b之厚度最好在5奈米至5微米的範圍內。在該砷 化鎵層12b上可形成AlGaAs、GaP、InP、InAs或其他類 似之化合物半導體層,取決於該半導體裝置的規格。 在圖5所示步驟中的分離之後,殘留在鍺構件1 1上 之離子佈植層1 3 a或類似者係使用一蝕刻劑或類似物加以 移除。然後,可進行氫退火步驟、拋光步驟、或類似步驟 以平面化該鍺構件之表面。該平面化後的基底可再使用作 爲圖1中所示步驟使用的鍺構件1 1。重複該鍺構件Π的 再使用可大大地降低半導體基底的製造成本。 如同以上所描述的,根據本發明之製造方法使得到具 有均勻厚度及良好結晶性之砷化鎵層的半導體基底成爲可 能。又,根據本發明之製造方法能大大地降低具有砷化鎵 層之半導體基底的製造成本。 因此,根據本發明可提供一製造半導體基底的方法, -8 - (6) (6)200425261 此半導體基底充分地展現其作爲化合物半導體裝置的優越 性並能確保良好的經濟性。 由於許多明顯範圍廣泛地不同之本發明實施例可在不 背離其精神與觀點下實現,可了解的是除了定義於申請專 利範圍中以外,此發明並不受限這些特定的實施例。 【圖式簡單說明】 附圖係本說明書之一部份,圖解本發明之實施例, 並連同描述以供解釋發明原理之用。 圖1係用以解釋根據本發明之較佳實施例的半導體基 底製造方法之圖覽; 圖2係用以解釋根據本發明之較佳實施例的半導體基 底製造方法之圖覽; 圖3係用以解釋根據本發明之較佳實施例的半導體基 底製造方法之圖覽; 圖4係用以解釋根據本發明之較佳實施例的半導體基 底製造方法之圖覽; 圖5係用以解釋根據本發明之較佳實施例的半導體基 底製造方法之圖覽; 圖6係用以解釋根據本發明之較佳實施例的半導體基 底製造方法之圖覽;及 圖7係用以解釋根據本發明之較佳實施例的半導體基 底製造方法之圖覽。 (7) (7)200425261 主要元件對照表 10 :第一基底 1 1 :鍺構件 1 2 :砷化鎵層 1 2 a :砷化鎵層 1 2 b :砷化鎵層 1 3 :離子佈植層 1 3 a :離子佈植層 1 3 b :離子佈植層 20 :第二基底 30 :黏合基底堆疊 40 :半導體基底 -10-
Claims (1)
- 200425261 Π) 拾、申請專利範圍 1· 一種半導體基底製造方法,包含 桌一步驟’在具有砷化鎵層於鍺構件上之第一基底中 佈植離子並形成一離子佈植層於該第一基底中; 第二步驟,黏合該第一基底與一第二基底以形成一黏 合基底堆疊;及 第三步驟’於該離子佈植層處分離該黏合基底堆疊。 2 ·如申|靑專利範圍第1項之製造方法,其中該砷化 鎵層係利用磊晶成長而形成。 3 ·如申請專利範圍第1項之製造方法,其中該第一 步驟包含形成一化合物半導體層於該砷化鎵層上之步驟。 4 ·如申請專利範圍第1項之製造方法,其中該離子 包括氫離子與稀有氣體離子之一。 5 ·如申請專利範圍第1項之製造方法,其中該第三 步驟包含利用退火該黏合基底堆疊而於該離子佈植層分離 該黏合基底堆疊之步驟。 6·如申請專利範圍第1項之製造方法,其中該第三 步驟包含利用一流體之噴出物或一靜態壓力以於該離子佈 植層分離該黏合基底堆疊之步驟。 7 ·如申請專利範圍第1項之製造方法,其中該第三 步驟包含利用插入一構件於該離子佈植層中以於該離子佈 植層分離該黏合基底堆疊之步驟。 8.如申請專利範圍第1項之製造方法,更包含移除 該第三步驟後移轉至該第二基底之殘留於一部份砷化鎵層 -11 - (2) (2)200425261 上的一部份離子佈植層。 9 ·如申請專利範圍第1項之製造方法,尙包含平坦 化該分離步驟分離所得到的該鍺構件之表面並於該第一步 驟中重複使用該鍺構件之步驟。 10· 一種由如同申請專利範圍第1項之製造方法所製 造的半導體基底。-12-
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003128917A JP4532846B2 (ja) | 2003-05-07 | 2003-05-07 | 半導体基板の製造方法 |
Publications (2)
Publication Number | Publication Date |
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TW200425261A true TW200425261A (en) | 2004-11-16 |
TWI259514B TWI259514B (en) | 2006-08-01 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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TW093111750A TWI259514B (en) | 2003-05-07 | 2004-04-27 | Semiconductor substrate and manufacturing method therefor |
Country Status (6)
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EP (1) | EP1620880A4 (zh) |
JP (1) | JP4532846B2 (zh) |
KR (1) | KR100725141B1 (zh) |
CN (2) | CN101145509A (zh) |
TW (1) | TWI259514B (zh) |
WO (1) | WO2004100233A1 (zh) |
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JP5128781B2 (ja) * | 2006-03-13 | 2013-01-23 | 信越化学工業株式会社 | 光電変換素子用基板の製造方法 |
CN108231695A (zh) * | 2016-12-15 | 2018-06-29 | 上海新微技术研发中心有限公司 | 复合衬底及其制造方法 |
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JPH0794409A (ja) * | 1993-09-20 | 1995-04-07 | Fujitsu Ltd | Iii−v族化合物半導体薄膜の形成方法 |
JP3879173B2 (ja) * | 1996-03-25 | 2007-02-07 | 住友電気工業株式会社 | 化合物半導体気相成長方法 |
JP3697106B2 (ja) * | 1998-05-15 | 2005-09-21 | キヤノン株式会社 | 半導体基板の作製方法及び半導体薄膜の作製方法 |
FR2784795B1 (fr) * | 1998-10-16 | 2000-12-01 | Commissariat Energie Atomique | Structure comportant une couche mince de materiau composee de zones conductrices et de zones isolantes et procede de fabrication d'une telle structure |
JP2004507084A (ja) * | 2000-08-16 | 2004-03-04 | マサチューセッツ インスティテュート オブ テクノロジー | グレーデッドエピタキシャル成長を用いた半導体品の製造プロセス |
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2003
- 2003-05-07 JP JP2003128917A patent/JP4532846B2/ja not_active Expired - Fee Related
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2004
- 2004-04-27 TW TW093111750A patent/TWI259514B/zh not_active IP Right Cessation
- 2004-04-28 EP EP04730068A patent/EP1620880A4/en not_active Withdrawn
- 2004-04-28 CN CNA2007101812355A patent/CN101145509A/zh active Pending
- 2004-04-28 CN CNB2004800006869A patent/CN100358104C/zh not_active Expired - Fee Related
- 2004-04-28 KR KR1020057020457A patent/KR100725141B1/ko not_active IP Right Cessation
- 2004-04-28 WO PCT/JP2004/006178 patent/WO2004100233A1/en active Application Filing
Also Published As
Publication number | Publication date |
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EP1620880A1 (en) | 2006-02-01 |
KR100725141B1 (ko) | 2007-06-07 |
TWI259514B (en) | 2006-08-01 |
JP2004335693A (ja) | 2004-11-25 |
KR20060005406A (ko) | 2006-01-17 |
JP4532846B2 (ja) | 2010-08-25 |
CN100358104C (zh) | 2007-12-26 |
CN101145509A (zh) | 2008-03-19 |
WO2004100233A1 (en) | 2004-11-18 |
EP1620880A4 (en) | 2008-08-06 |
CN1698180A (zh) | 2005-11-16 |
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