TW200405216A - Method for conditioning electronic microcircuits for a chip card and electronic microcircuit module obtained thereby - Google Patents
Method for conditioning electronic microcircuits for a chip card and electronic microcircuit module obtained thereby Download PDFInfo
- Publication number
- TW200405216A TW200405216A TW092109055A TW92109055A TW200405216A TW 200405216 A TW200405216 A TW 200405216A TW 092109055 A TW092109055 A TW 092109055A TW 92109055 A TW92109055 A TW 92109055A TW 200405216 A TW200405216 A TW 200405216A
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- Taiwan
- Prior art keywords
- mask
- substrate
- module
- patent application
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- Prior art date
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07745—Mounting details of integrated circuit chips
- G06K19/07747—Mounting details of integrated circuit chips at least one of the integrated circuit chips being mounted as a module
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07743—External electrical contacts
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07745—Mounting details of integrated circuit chips
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- H—ELECTRICITY
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
- H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
- Y10T156/10—Methods of surface bonding and/or assembly therefor
- Y10T156/1052—Methods of surface bonding and/or assembly therefor with cutting, punching, tearing or severing
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
- Y10T156/10—Methods of surface bonding and/or assembly therefor
- Y10T156/1052—Methods of surface bonding and/or assembly therefor with cutting, punching, tearing or severing
- Y10T156/1056—Perforating lamina
- Y10T156/1057—Subsequent to assembly of laminae
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Credit Cards Or The Like (AREA)
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200405216 玖、發明說明: 【發明所屬之技術領域】 一:?月的目的是調節在模組中之電子微電路 — 固U %路係设計來容納一積體電路,一般 = :而形成電予微電路模組。本發明的進一步目並 侍《電子微電路模組。確實 、疋、而獲 產量的增加,㉟片卡在曰L 模組的晶片卡 二 卡在日吊生活的使用越來越頻繁,製止 程已編來符合量的需求,有時損及品質 又口口的可非度。本發明進一步相關 組在晶片卡中或其他基板。 文h些模 【先前技術】 晶片卡獲得是配置電子微電 凹槽中。這個電子模組包含微 接觸面,在此卡的可見面這邊 片’其接著隱藏在卡的凹槽中 面積較低面的上方面的反面。 路模組在由卡的厚度形成的 電路,其有傳導性面積的上 。電子模組的另一面帶有晶 。晶片被固定並連接在傳導 有關的先前技藝,法國專利編號FR-A-2 488 446說明一 設計來貼附在識別卡中的緊密電子模組。此模組包含以底 黏著在包含接觸區之金屬板第一面的晶片。晶片藉由連接 晶片上邵到这些接觸區的導線連接到這些接觸區◊此模組 包含支撐兀件或基板,金屬板可支撐在其上。支撐元件接 著包含一或多個窗格讓晶片黏著及/或連接到金屬板。 晶片的黏著有一問題,因為長久而言不可靠。再者,放 置黏膠量的均勻分配且是以精密定義的間隔。但是黏膠平 85033 200405216 面上氣泡的出現會減弱模組的 合要求的產品條件,使用的黏 的結合。但是這些黏膠也造成 附在金屬板上不穩定的原因。 機械力量。事實上,為了符 膠要可以在相當高溫下快速 氣泡的行程並因而是晶片貼 為了讓機械力量導引至模組,並在此同時保護導線及晶片 ’塗層的產品被用來將之塗層。塗層產品可能是樹脂,例如 :這個在熱處理的效應下或以紅外線或紫外光線照射而變硬 並聚合。這些塗層樹脂本身就是問題。他們的可濕性不穩定 並部分取決於外部條件,而其無法在沒有明顯的花f下加以 控制。配置的樹脂形成較低面邊的圓頂,但其在配置時會散 開,因為還沒有聚合。樹脂滴的散開造成模組的機械力量的 減弱而提供微晶片及其導線較差的保護。 這個滴的流動產生了困難,因為其也使得模組太寬。由 於這個滴的位置,因此必須在滴的周圍提供周邊,以便保 田周邊區域來將模組貼p付與卡片。這些貼附區域接著黏著 到晶片卡凹槽的侧面槽口中的前半部。 另方面,熱聚合樹脂,其在紫外線照射效應下聚合, 提:可濕性方面的正確結果,藉之提供所塗層物品的完善 保邊。但廷個樹脂未給予模組足夠的機械力量。再者,紫 外泉…、射會妨害這些模組上晶片的記憶體區域。 要解决I^個問題,已知的解決方案利用呈現良好的機械力 口口 、对^,而且可以讓這種樹脂滴的直徑縮小。這些解 、、木貫做屏障來維持滴的外流。此屏障可以❾,例如,配 置在要放置此晶g、 Θ义金屬板區域周邊之碎酮環的絹網印花 85033 200405216 而獲得。炊κ 、 〜’這個解決方業的效率受到限制,而再者其並 非完全的限备丨、、念AA、、4 別屑的泥動,如果平面有些微的傾斜。 另夕卜的,M m杰,, 、 國專利編號US-A 5,989,941說明在塗層產品形 ^ 、、并障的用途並可改善電子模組的熱消耗及機械附 ' 、這種屏障的解決方案也熟知為技術名詞,,dam & fill"。廣 ρχε. ϊ 曰 ' 早由—黏著層固定在模組的支撐上。其固定在維持 阳片連接的接觸板之相同支撐某一邊的位置上。這個屏障 對應到包含尺寸讓接觸板形成金屬化電路模型之窗格的薄 膜以及^片都整個框在這個窗格中。根據這個文件只知道 :用的疋包含至少—個傳導薄膜的薄膜。再者,這個薄膜 只有在金屬電路產生後以及在晶片連接到這個電路之後才 貼附在此模組上。 此薄膜包含例如長的係長條,其中一面以塗抹器塗層以 黏[生材料。根據此文件,此薄膜接著切割成特定大小,以 便藉之形成窗格。配置此薄膜窗格使之與支撐的不同區域 合:,每個區域包含金屬電路而一晶片連接其電路,支撐 總疋包含哭出物使之固定在 U疋在日曰片卡。潯膜以此方式黏著在 如此每個窗格只配置在-個電路周圍。因為薄膜 有:格接著可以讓塗層材料的外流受限制當樹脂滴 放置在有其晶片的電路上。 為了接著裝配在識別卡中,根據這個指示· 組必須塗層以敎的黏膠,其使之黏著在識別卡凹槽底部 ’因為所使用薄膜型態的基礎本質。 85033 200405216 根據最先進技術的微模組的困難包含的事實,即使在給 予防止樹脂滴外流的薄膜時,仍需要長的,仔細的以及沒 有效率的準備階段,其對應貼附微模組在卡片上的階段Γ 事實上,為了貼附微模組在卡片±,使用第二薄膜::塗 層有”熱熔"膠並且在第一階段預先剪裁形成其中的窗格。接 著,7這個膠膜熱捲到微模組上,而最後在第三階段這個膜 的膠被活化做最後微模組的貼附在卡片上。 第一階段是低效率的,因為切割剪切機即使在其已經冷 卻後仍黏在膠膜上而阻止了對於薄膜的較快速操作。 第一階段因此不符合晶片卡大量生產的速度要求。再者, 為了保證膠膜正確較位在微模組上,必須要提供對其他 的滾珠移除,而造成較慢的程序。在快速的程序,當膠膜 =片發生時,有明顯的退回率。在這個階段的退回^很昂 貴的,因為沒有任何的退回元件是可以重複使用的。 要達到能快過每一個微模組是個別黏著的量產速度,使 用這種膠膜是必要的。但是使用這種膠膜是必要的Z便固 定微模組在其凹槽底部,即使其超時可靠度受到限制。 【發明内容】 本發明的任務是去除前文提到的問題,藉由重新定義電 子微電路的調節作用,以便使後續包含此微電路之模組: 卡片貼附。如此,電子模組調節階段的效率獲得改善、,並 進步这種電子才莫組貼附在卡片± #長期可靠度可以增加 。最終產品的可靠度增加是因為模組黏著在卡片上的^靠 度獲得改善’並也是因為晶片的黏著在電子微電路背面: 85033 200405216 可靠度獲得改善。實際上,本發明提供用來轉移所有黏合 裝置到電子微電路模組。 本無明的目的因而是包含基板,在這個基板第一面的至 少一接觸面,可以容納積體電路的這個基板的第二面的電 子微電路’特徵為其包含平行六面體形狀,第一黏合裝置 來維持遮罩第一面在基板的第二面相反位置,此遮罩限制 平行六面體有穿孔而在積體電路周圍形成窗格,以及分配 在遮罩第二面上的第二黏合裝置。 本發明進一步目的因而是調節電子微電路模組的方法, 其特徵為包含下面的階段,階段包含有·· -在基板帶的第一面上產生接觸面積, -配置第一黏合裝置在基板第二面與遮罩第一面之間,以 保持遮罩在第二面相反位置, 將遮罩Y牙孔,如此遮罩窗格面對接觸面積, 配置第一黏合裝置在遮罩的第二面上,以及 以平行ττ面體形式分開個別模組。 【實施方式】 —圖1顯示根據本發明之電子微電路模組i。模組!包含形成 —平面的基板2。基板2最好用電介f材料做的,例如 酯薄膜’特別是聚乙烯對苯二甲酸酯(ρΕτ),聚二酸: ,或甚至是聚亞醯胺樹脂。在特定的具體實: 板的厚度是2 5微米的等級。 在基板2的第一面3上,模組!有_接觸面4。接觸, 例如印刷電路。取得這個印刷電路是以基板上厚度㈣到 85033 -10- 200405216 35微米的鋼層薄片疊層。銅層藉由先前的配置 在第一面3的位置中。基板2與其銅層接著—般的化學= 來形成印刷電路4。 x 基板2也提供有孔5,以穿過基板所形成平面而形成的, 並允許其第-面3貼到第二面6。第二面6與第一 而且平行。 々从向 微電路模組1方裳—二 、在罘—面6廷邊包含一厚遮罩7,其以黏人 置8版黏在這個第二面6。遮罩了對應到厚度在別微米等級 :薄膜以:其中至少形成有-窗格9。遮罩的厚度大於積體 電路10的高度。窗格9夠大到讓積體電路10,或晶片10直接 固定在後來的基板的第二面6。遮罩7最好是用聚乙歸 二甲酸酿(PETG)或聚乙歸基氯化物(pvc)型態的塑㈣入 物做的。也可以是用紙做的。產生遮罩7的材料選擇取決: 後續所設計電子模組的用途。實際上為遮罩7所選擇的材料 可以‘襄匕在互補裝置’例如晶片卡中輕易的膠黏或焊接。 在一範例中,黏合裝置8的形式為熱塑膠聚合物樹脂層 (聚酯型態,例如)其可在適當溫度下被活化(例如在⑽。: 130 QC之間)。 遮罩7是由坪接帶產生的。在一變化中這個焊接帶在目占 附在第二面6上前是有穿孔的。遮罩7最好的形式是包各好 幾個窗格例如9的焊接帶。焊接帶因此包含連績的窗格9形 成重複的圖形且以位在窗格間的焊接區段彼此分開及藉 由圍繞窗格邊緣的連續焊接元件,在帶的方向中。這些^ 繞著窗格9的焊接區段是要框住基板2的不同區域。基板2 85033 11 200405216 的每個不同區域對應一組 茂n L 卿面和’例如4本身。i含蛘诚 罩7的窗格9已正確配置的_ 身坆锨遐 10的晶片。 、、接觸面積4’是要容納例如 遮罩7必須非常準確的定位在 ^ Τ ΛΛ , 昂一面6上’因為它的定位 對万;正確的貼附晶片丨〇在第二面上 ,..._ 非节重要並可以讓你 由例如5的孔連接到接觸面積 ''二 在晶片呢裝之前配置,萬_不正/而’因為遮罩最好 差代價比較低。 不正確的定位這種型態的誤 使用薄片疊層技術以便獲得 ^ ^ 于耍罩7相對於晶片10配置並 連接的區域位置的非常準確的 1 為了廷個目的,力赫 佳具體實例中載負遮罩7的帶、 w ^ ^ ή, , . ^ G。從向疋位的裝置(規律配 置在:的長度上)形成索引’互補裝置透過它使帶向前移, 可用來確保在薄片疊層期間遮罩7正確的定位。 根據第一具體實例,為維 _ . ™ L _ 百牙孔的遮罩7在基板2之第 一一迫個第二面6已經事前塗層黏合裝置8。在 此實例中,黏合裝置8甚至可以力g 以在印刷電路4產生前配置。 再者,黏合裝置8可以塗抹在整個第- 、 正丨u矛一面6上,甚至對應遮 罩7的窗格9的區域(除了孔5的位罾 7 U置)。遮罩7接著以滾筒對基 板2上的黏合裝置疊層。 根據第二具體實例黏合裝置8配置在遮罩7的其中一面, 此面是要壓在第二面6上的。窗格9接著在塗層以黏合裝置8 《後產生,其保證即使可確定黏膠的分体並防止基板第二 面的塗層。相同的方式’藉由在兩池間連續的薄片疊層方 法,遮罩7膠黏在基板2上。在這個第二實例中可能必須要 85033 -12- 200405216 提供第二黏合裝置來維持晶片1〇在這個第二面6上的位置 中〇 在較佳的具體實例中,晶片i 0用第一黏合裝置8貼附在窗 格9並膠黏在基板2的第二面6。晶片1〇最好在遮罩7配置在 基板2之後貼附。然而,在兩個方法中,也可以在之前貼附 。為了達到有效及固定的膠黏,黏膠在晶片要放置的定點 活化。在一變化中,如圖2顯示的,第二層的黏膠4,用來膠 黏晶片10在基板2上。 之後,為了連接晶片1 〇到接觸面積4,最好使用接線連接 技術,稱為,,接線接合,,,其中晶片10的上表面12以金屬,例 如鍍金線11連接到接觸面積4的下面13。使用的接線u的直 徑為例如,20微米而兩個端子的連接是用超音波熱熔接產 生的。接線11在孔5的場點穿過基板2。晶片以表面貼附元件 技術CMS &知的覆晶"貼附,也是可能的。在這個實例 中晶片最好在遮罩貼附前贴附在基板上。 -一這固固定在基板2上,遮罩7的厚度大於晶片的高度 。以此方式,由遮罩7帶的框形成的邊緣出現確保晶片_ 到保護。為了提高保護性,晶片1G及接線_ 層14。 w力曰至 樹脂塗層14以液能形彳λ *丄 、、 便&、形式引入並由聚合變硬及硬化。為了 這個塗層窗格9的尸Ej 女a Α 、、、 、、的開口万向向上。配置在窗格9形成的空腔 中的树脂1 4流動可以讀命間访接 π」以戒空間被填滿。聚合可由熱 處理裝置或可能有紫外纟泉昭^ 、·’ 妗“… 卜、.泉…射而加速 '樹脂14最好被紫外 、”皮知、射來限制不希望要的遮罩效應,如果遮罩是用州 85033 -13 - 200405216 做的。 用超音波洋接技術。 以此方式形成的微電路模組1則有一接觸面,以接觸面積 例如1’、以及合併遮罩7的後面,此後面平行於接觸面。要 貼附延樣的微晶片!在互補裝置(例如晶片卡)中,首先必須 配備有晶片10形成完整的電子模組,並接著放置此完整:: 模組在互補裝置的凹槽中。本發明中的互補裝置座中的凹 槽為獨-的平行六面體。這個凹槽形成單純的空腔,沒有 槽口 ’如此這個凹槽的底部大小與個別模組的相同。凹样 的底邵的材質與遮罩7的相容。在此,相容的意思是兩個: 質可以彼此固定的膠黏在—起,利用傳統的黏$,或是利 在此實例中互補裝置為晶片型態的識別卡,最好是用盒 遮罩的那些相容的塑膠材料。因Λ,可以用氰酸的 黏膠。膠黏也可以藉由分配黏膠並利用超音波震動技 定0 、從帶開始,模組可以在晶片安裝在每個窗格空腔9之前或 曰後刀開在&佳貫例中微電路模組的個別分開是在這些 晶片貼附而且每一個的窗格空腔9被填充塗層樹脂之後執 行的。 ^較佳實例中’膠的層15配置在整個帶上(在晶片被塗層 的k邊上)在堂層後且在分開之前,這個黏膠也最好是熱溶 型態的。接著模組被分開,例如由㈣如16及17或晶粒模 切。每個模纽接著看來像是平行六面正方形,纟中一面覆 蓋一層的Η膠。這種模組接著由其邊緣抓住,或藉由從上 85033 i · 3- -14- 200405216 面從板4以吸管吸入。接著將之放置在對應的晶片卡19的平 行六面體凹槽1 8或某些其他的晶片支撐。凹槽丨8有直立邊 ,而沒有槽口。 在一嫒化中,層1 5在與層1 8的同時做。其接著與窗格9同 時晶粒模切。接著基板2對帶7做薄片疊層。接著晶片1〇貼 附。接著做塗層1 4,接著模組被個別分開且在這個實例中 ’也已經預先膠黏,其貼附在晶片卡的空腔18中。 兩個實例中模組的形式都是平行六面體。在最新科技中 其不包含任何突出物。這些突出物,其為周邊附接區域, 係用來貼附模組在卡片的槽口空腔中。然而,這些突出物 的缺點是造成撕裂。本發明巾,晶片由底部膠黏到卡片上 膠層1 5的般及杈正的放置保證其厚度,並因而單純的 付口均勻冲洗外伸至卡上之面積4所需的容忍度。沒有突出 物除去可能遇到的撕裂問題。 +因此在第—模式中遮罩帶鋪在基板帶上,晶片則放置在 空腔中,晶片以填充遮罩中的孔來塗層,層15並送上而預 先f黏的平行,、面體模組被分開。這個實例中,這些膠層 最好:熱熔型態的黏膠層,其可由加熱而活化。…曰 、、々在第二實例中’膠層8及15被放置在遮罩帶的每-邊,還 ^打孔的’窗格9經過遮罩及膠層的產生,預先膠黏的遮罩 在基板2上,藉由對齊金屬化4對應後背的窗格9,晶片 ^裝’此晶片塗層而縣膠黏的平行六面體模組也在這個 點分開。 欠化中,每一膠層可以用的兩面有膠的帶取代。在 85033 -15- 200405216 進一步的、泛化中’個別的模組可以膠黏至晶片十的單純平 行六面體空腔底部,藉由氰基丙烯酸黏膠的膠黏或藉由在 這個空腔底部中模組的基底面超音波膠黏。 【圖式簡單說明】 本叙明將可獲得較佳的理解。冑由閱讀上面的說明及觀 看隨附的圖示。這些在此只是做為範例形式並且完全不在 限制本發明。圖示顯示: 圖1根據本發明之電子模組,貼附在晶片基板上,通常是 曰曰片卡的縱像橫切面圖示; 圖2根據本發明乏雷| +知<私子模組的下側透视圖。 【圖式代表符號說明】 1 電子微電路模組 2 基板 3 弟一面 4 接觸面積 4, 第二層膠 5 孔 6 弟二面 7 遮罩 8 黏合裝置 9 窗格 10 積體電路 11 接線 12 上表面 85033 -16 - 200405216 13 下面 14 樹脂塗層 15 膠層 16, 17 模組 18 凹槽 19 晶片卡 85033 -17-
Claims (1)
- 200405216 拾、申請專利範圍·· 1· -種電子微電路模組⑴’其包含—基板⑺,在這個基 板第-面⑺上的至少一接觸面積⑷,可以容納—積體 電路(10)的這個基板的第二面(6),特徵為其包含一平行 六面體形狀,—第一黏合裝置(8)以維持遮罩⑺的第一 面在相對基板第二面的位置上,遮罩限㈠行六面體的 穿孔形成積體電路周®的窗格以及分配在料第二面 上的第二黏合裝置。 2. 如申請專利㈣第!項的模組,其特徵為遮罩是用與提 供來容納模組之卡片相同的材質做的,例如聚醋的聚合 物或聚乙婦基氯化物型態。 3. 如申請專利範圍第!或2項的模组,其特徵為遮罩的厚度 ’相對其貼附之基板第二面而定羞的 W疋我的,大於積體電路的 合 ΕΕΡ. 回度0 如申μ專利範圍第1或2項的模組,其特徵為第一黏合裝 置可以讓積體電路維持在基板上。 口 5· -種用來調節電子微電路模組⑴的方法,其特徵為並包 含以下階段,其包含: _在基板帶(2)的第-面(3)上產生接觸面積⑷, _配置第-黏合裝置(8)在基板第二面與遮罩帶⑺的 弟一面之間,以保持遮罩在相對第二面上的位置, -穿孔遮罩帶使得遮罩窗袼面對接觸面積, -配置第二黏合裝置在遮罩的第二面上,以及 -分開平行六面體形式的個別模組。 ,·如_請專利範圍第5項的方法,其特徵為包含额外的階 85033 405216 段’其包含: -選擇遮罩的材料與模組要貼附之卡片相同。 7·如申請專利範圍第5或6項的方法,其特徵為遮罩的形式 為包含好幾個窗格的帶,窗格薄片疊層在包含幾個接觸 面積的支撐上,在分開成為個別單元前。 8·如申請專利範圍第5或6項的方法,其特徵為階段包含維 持遮罩在相對基板第二面的位置,包含的動作有: 薄片疊層第一黏合裝置在基板的第二面上。 >•如申請專利範圍第5或6項的方法,其特徵為階段包含配 置黏合裝置在遮罩上,包含動作有: -配置黏合裝置在遮罩上,並接著 -在對基板第二面薄片疊層之 10·如申請專利範圍第5或6項的方法 、%階段包含膠黏積體電路到基板 裝置上。 前穿孔這個遮罩。 ’其特徵為所包含的後 的第二面,在第一黏合 11 ·如申請專利範圍第5或6項的方法 段有: 其特徵為其包含的階 -膠黏配備電子電路的遮罩 12·如申請專利範圍第11項的方法 遮罩到凹槽,包含的動作有: 到卡片凹槽的底部。 ’其特徵為階段包含膠黏 13. -配置氰基丙缔酸的黏膠在 如申請專利範圍第1 1項的方法 遮罩到凹槽,包含的動作有: 遮罩與凹槽底部之間。 ’其特徵為階段包含膠黏 -以超音波射出焊接。 85033
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FR0204899A FR2838850B1 (fr) | 2002-04-18 | 2002-04-18 | Procede de conditionnement de microcircuits electroniques pour carte a puce et microcircuit electronique ainsi obtenu |
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TW200405216A true TW200405216A (en) | 2004-04-01 |
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TW092109055A TW200405216A (en) | 2002-04-18 | 2003-04-18 | Method for conditioning electronic microcircuits for a chip card and electronic microcircuit module obtained thereby |
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US (1) | US7320738B2 (zh) |
EP (1) | EP1495442B1 (zh) |
JP (1) | JP2005535105A (zh) |
KR (1) | KR20040098667A (zh) |
CN (1) | CN1647106B (zh) |
AU (1) | AU2003227761A1 (zh) |
FR (1) | FR2838850B1 (zh) |
TW (1) | TW200405216A (zh) |
WO (1) | WO2003088139A1 (zh) |
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TWI487000B (zh) * | 2007-08-10 | 2015-06-01 | Quantum Global Tech Llc | 電子裝置製程構件之非即時調節的方法與設備 |
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CN100403335C (zh) * | 2005-08-30 | 2008-07-16 | 资重兴 | 存储卡的制造方法 |
KR100875952B1 (ko) * | 2006-09-22 | 2008-12-26 | 소프트픽셀(주) | 전자카드 및 그 제조방법 |
US7999197B1 (en) * | 2009-04-20 | 2011-08-16 | Rf Micro Devices, Inc. | Dual sided electronic module |
US8474726B2 (en) | 2010-08-12 | 2013-07-02 | Feinics Amatech Teoranta | RFID antenna modules and increasing coupling |
US8366009B2 (en) | 2010-08-12 | 2013-02-05 | Féinics Amatech Teoranta | Coupling in and to RFID smart cards |
US8789762B2 (en) | 2010-08-12 | 2014-07-29 | Feinics Amatech Teoranta | RFID antenna modules and methods of making |
US9195932B2 (en) | 2010-08-12 | 2015-11-24 | Féinics Amatech Teoranta | Booster antenna configurations and methods |
US9033250B2 (en) | 2010-08-12 | 2015-05-19 | Féinics Amatech Teoranta | Dual interface smart cards, and methods of manufacturing |
US8870080B2 (en) | 2010-08-12 | 2014-10-28 | Féinics Amatech Teoranta | RFID antenna modules and methods |
US8991712B2 (en) | 2010-08-12 | 2015-03-31 | Féinics Amatech Teoranta | Coupling in and to RFID smart cards |
US9112272B2 (en) | 2010-08-12 | 2015-08-18 | Feinics Amatech Teoranta | Antenna modules for dual interface smart cards, booster antenna configurations, and methods |
BR112014005507A2 (pt) | 2011-09-11 | 2017-06-13 | Féinics Amatech Teoranta | módulos de antena rfid e métodos de fabricação |
BR112014019291A8 (pt) | 2012-02-05 | 2017-07-11 | Feinics Amatech Teoranta | Módulos da antena de rfid e métodos |
EP2741240B8 (en) * | 2012-12-10 | 2018-03-28 | IDEMIA France | A secure chip module and a method of making the same |
CN107111767B (zh) * | 2014-12-23 | 2020-11-20 | 3M创新有限公司 | 柔性射频识别标签 |
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2002
- 2002-04-18 FR FR0204899A patent/FR2838850B1/fr not_active Expired - Lifetime
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2003
- 2003-04-16 AU AU2003227761A patent/AU2003227761A1/en not_active Abandoned
- 2003-04-16 KR KR10-2004-7016551A patent/KR20040098667A/ko not_active Application Discontinuation
- 2003-04-16 JP JP2003585002A patent/JP2005535105A/ja active Pending
- 2003-04-16 US US10/511,792 patent/US7320738B2/en not_active Expired - Lifetime
- 2003-04-16 EP EP03725201A patent/EP1495442B1/fr not_active Expired - Lifetime
- 2003-04-16 WO PCT/EP2003/050109 patent/WO2003088139A1/fr active Application Filing
- 2003-04-16 CN CN038087081A patent/CN1647106B/zh not_active Expired - Fee Related
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TWI487000B (zh) * | 2007-08-10 | 2015-06-01 | Quantum Global Tech Llc | 電子裝置製程構件之非即時調節的方法與設備 |
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EP1495442A1 (fr) | 2005-01-12 |
AU2003227761A1 (en) | 2003-10-27 |
FR2838850B1 (fr) | 2005-08-05 |
US7320738B2 (en) | 2008-01-22 |
CN1647106A (zh) | 2005-07-27 |
EP1495442B1 (fr) | 2012-08-01 |
US20050253228A1 (en) | 2005-11-17 |
FR2838850A1 (fr) | 2003-10-24 |
KR20040098667A (ko) | 2004-11-20 |
CN1647106B (zh) | 2010-05-12 |
JP2005535105A (ja) | 2005-11-17 |
WO2003088139A1 (fr) | 2003-10-23 |
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