TW200402863A - Integrated semiconductor structure - Google Patents

Integrated semiconductor structure Download PDF

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TW200402863A
TW200402863A TW092114098A TW92114098A TW200402863A TW 200402863 A TW200402863 A TW 200402863A TW 092114098 A TW092114098 A TW 092114098A TW 92114098 A TW92114098 A TW 92114098A TW 200402863 A TW200402863 A TW 200402863A
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metal
semiconductor structure
integrated semiconductor
patent application
scope
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TW092114098A
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TWI237890B (en
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Robert Bauer
Werner Ertle
Till Frohnmueller
Bernd Goller
Reinhard Greiderer
Nagler Oliver
Schmeckebier Olaf
Stadler Wolfgang
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Infineon Technologies Ag
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Description

200402863 五、發明說明（1) 本發明關於一積體半導體結構，其具有一基板，至少 一位於基板上之半導體元件，及具有一表面之墊金屬， 複數個金屬層位於墊金屬及基板之間，及複數個絕緣層 將金屬層彼此分開，該墊金屬在至少一半導體元件之至 少一部分延伸。 此型之半導體結構曾揭示於美國專利號碼6，2 0 7，5 4 7。 製造積體半導體結構之一重要方面為半導體元件電接 觸（黏接），該元件係位於半導體結構之中。此情況下，
外殼接點（P I N s )於半導體元件間電接觸係經由接點島而 產生。該接點島為金屬區（墊金屬），其可電連接至半導 體元件及金屬層。考慮到目前使用之黏接方法，墊金屬 與半導體元件之尺寸相比較，為半導體結構中相當大之 尺寸。墊金屬因此涵蓋晶片之大部分表面，因此在墊金 屬下面之區域構成晶片體積之大比例部分。
在半導體結構黏接期間，一高機械負荷加在墊金屬 上。此一負荷帶來一種危險，即，將墊金屬下面配置之 結構損壞。例如，絕緣層之頂部其直接位於墊金屬之下 面可能變成斷裂，因而導致因半導體結構之損壞鈍化之 透電流。其次，半導體元件如主動元件，如M0S電晶體， 其具有相當薄之閘極氧化物，為可靠度理由，必須在各 種情況下被保護以不受過度壓力。因此，以前之半導體 元件未配置於墊金屬下面，以便避免損壞。其意義為晶 片面積之大幅損失必須接受。 EP 1 017 098 A2曾揭示一應力吸收金屬層於機械加強
第7頁 200402863 五、發明說明（2) 電絕緣層之結合，及此二層之足夠厚度，俾半導體元件 之至少一部分可直接延伸至墊金屬下面。但此建議僅能 稍為降低晶片表面上所佔之面積。 美國專利號碼6，2 0 7，5 4 7在其引言中揭示，在墊金屬與 頂部金屬層之間引進一種結構中間層，以便穩定及保護 下面之主動電路。此舉之結果為具有閘極氧化物之結構 如Μ 0 S電晶體，可被直接配置於墊金屬之下面。但，此型 結構之中間層之產生需要特別修改及複雜之生產方法。 因此，本發明之目的為建議一半導體結構，其可使用 簡化之生產方法，對半導體元件之使用方面無任何限 制，其可配置在墊金屬之下面。 根據本發明，本發明之目的係由引言所述之積體半導 體結構達成，其中，在墊金屬表面下面，至少頂部二金 屬層有一結構，每一案例下，至少包括二相鄰之互聯。 本發明係根據一發現，利用位於墊金屬下面之頂部二 金屬位準之適當安排（布局），可構成阻尼及穩定結構， 而不需修改積體半導體結構之製造方法。此外，發明人 發現因為此型積體半導體結構增加之穩定性，任何型之 半導體元件可安排在墊金屬之表面下面。 與以往設計不同，本發明之互聯可被電方式利用，而 並非僅用來增加穩定性。例如，該等運行在墊金屬下面 之互聯係連接至半導體結構上一或不同電位。頂部金屬 層之互聯典型用來作為下面之半導體元件（電晶體）之供 應線。
200402863 五、發明說明（3) 視所用之技術而定，金屬層之數目可在3及1 1個之間， 例如，4至8個金屬層為目前之0 . 1 3 u m C Μ 0 S技術代所使 用。 本發明積體半導體結構之構型提供數個互聯於金屬層 中，在墊金屬之表面下面至少有2至6個間之互聯，視此 墊金屬之尺寸延伸之程度而定。 根據本發明，在一金屬層内之互聯可彼此電絕緣。 在另一發展中，在金屬層内之互聯為彼此電連接。此 外，如有二個以上之互聯在墊金屬表面之下面，金屬層 中之各別互聯可彼此電絕緣，其餘互聯則彼此電連接。 如所週知之假結構亦可用為結構之用，該結構具有純 穩定性功能，而並非電連接至任何電位，而被併入墊金 屬表面之下面之至少一小區域。但，此種設計導致電可 用面積之損失。 另一種提供位於墊金屬下面結構之屏蔽之優異構型， 可提供將互聯設計為足夠寬及彼此餘裕之空間。根據本 發明，互聯之寬度與空間之比值為3及2 0之間，較佳為 1 0。至少，頂部二金屬層設計為寬互聯，以便達到阻尼 效應而不需任何不必要之程序。 在本發明積體半導體結構之一特別優異進一步發展 中，至少在墊金屬表面之下面，具有複數個通孔，該等 通孔電連接至頂部金屬層之互聯至金屬層下面之互聯， 該通孔垂直穿過頂部二金屬層間之絕緣層。此舉首先可 保證半導體元件即使在此等金屬層間發生短路時仍然工
200402863 五、發明說明（4) 作，此等短路可能由機械壓力而發生。其次，該通孔進 一步穩定積體半導體結構。 最佳之穩定及阻尼可經由該通孔之適當構成而達成。 較佳為相當多數目之通孔位於頂部二金屬層之間，分布 在墊金屬表面之下面，該通孔彼此以串聯安排或與另一 通孔成補償安排。因此，任何發生之壓力可分布在最大 可能面積上。
本發明另一優異發展之積體半導體結構，提供頂部二 金屬層之互聯具有複數個孔隙，至少在墊金屬表面之下 面。此等孔隙可與形成絕緣層之相同材料填充，例如， 矽二氧化物或矽氮化物。此舉可額外穩定半導體結構。 本發明積體半導體結構之另一發展中，至少在墊金屬 下面之孔隙之總面積為互聯總面積之5 % - 3 0 %之間。該 孔隙較佳構成互聯之2 0 %。 根據本發明該積體半導體結構與發生之壓力，亦因頂 部二金屬層之互聯之彼此安排方式而增加穩定性，因為 在頂部之互聯中之孔隙係與下面互聯中之孔隙成彼此補 償。此一補償安排可保證高度之阻尼。 在本發明積體半導體結構之另一實施例中，頂部金屬 層之互聯約位於金屬層下面之互聯之上面。
頂部金屬層之互聯較佳與金屬層下面之互聯彼此成補 償。此舉可導致形成之阻尼結構非常有效。此例中之互 聯中之橫向補償可為最大，因此，此例中金屬層之二相 鄰互聯被上面之互聯部分所蓋住。
第10頁 200402863 五、發明說明（5) 積體半導體結構之另一優異構型提供之金屬層至少大 部分為足夠硬之金屬製成。因此可防止金屬層之厚度在 機械之負荷下降低，或可防止位於金屬層上面之絕緣層 在機械負荷之下被推而穿過下面之絕緣層。 該金屬典型為銅，鋁，鎢，鉬，銀，金，鉑或其合 金。 在另一改進中，墊金屬之表面涵蓋一區域，其在金屬 層内包含至少50%金屬。此等較佳包括互聯之金屬區域 (無孔隙），但亦可引入金屬假結構。 對於一積體半導體結構之特別穩定構型而言，金屬均 勻分布在墊金屬表面下面。因此，由金屬及於互聯中孔 隙組成之互聯及相鄰互聯中之電連接，較佳能均勻分布 在塾金屬表面之下面。 在金屬與頂部金屬層之間較佳有一頂部絕緣層，頂部 絕緣層之第一厚度為D1 ，頂部金屬層之第二厚度為D2， 厚度D1與D2之比值為1與5之間。此舉可減低頂部絕緣層 形成裂紋之危險。因此可提供下面之半導體元件之保 護。 本發明積體半導體結構之另一發展提供厚度D 1頂部絕 緣層，及厚度為D3之墊金屬，厚度D1與D3之比值為0.5及 3之間。 該半導體結構包括一墊金屬3，其有一表面F及厚度D3， 例如一厚鋁層，一鈍化層8，基板1，半導體元件2，例如 電晶體2位於基板上，電晶體2安排在墊金屬3之表面F下
第11頁 200402863 五、發明說明（6) 面，複數個金屬層4 . X及複數個絕緣層5 . y將金屬層4 . X彼 此隔開。為清晰理由，圖1僅圖解說明第一及頂部二金屬 層4.1 ， 4·χ_1及4.x ;視所用技術而定，目前可使用11 個金屬層4 . X安排在彼此之上。 為形成對積體半導體結構黏接或測試時產生之機械壓 力之屏蔽，墊金屬3及位於墊金屬3下面之頂部絕緣層5. y 之設計為足夠厚之絕緣層。絕緣層5 . y較佳有一厚度D 1， 其為頂部金屬層4·χ之厚度D2 —及五倍，及為墊金屬3之 厚度D3之0.5及3倍。 頂部二金屬層4 . X及4 . X - 1由絕緣層5 . y - 1將其隔開。通 孔6垂直穿過此絕緣層5 . y - 1 ，及電連接頂部金屬層4 . X至 下面之金屬層4.X-1 。特別在墊金屬3之表面F下面區域 中，有複數個通孔6於二金屬層4. X及4· x-1之間。此等構 型可提供足夠之電晶體2對機械負荷之保護。 圖2顯示本發明基體半導體結構之直接在墊金屬表面下 面之二金屬層區域之透視說明。頂部金屬層之互聯4 . X. z 及下面之金屬層之互聯4.X-1.Z具有孔隙7.x及7.x-1。互 聯4 . X . z中之孔隙7 . X與下面之互聯4 . X - 1 . z之孔隙7 . X - 1 互成補償配置。孔隙7 . X與7 . X - 1不在彼此之上面。此 外，該二互聯4 . X與4 . X - 1 . z經垂直向通孔6彼此電連接 至通孔6。為保證對機械壓力之最大穩定性，可安排多個 通孔6於墊金屬下面區域中。 當精於此技藝人士應用此特殊技術及能力時，孔隙7 X 及通孔6之其他安排亦可產生結果。
第12頁 200402863 五、發明說明（7) 圖3顯示本發明積體半導體結構之墊金屬及相鄰墊金屬 3之平面圖。四個互聯4.X.1至4. X. 4在墊金屬3之下面運 行。第五個互聯4 . X. 5在墊金屬3之區域外運行。各別互 聯4 . X . z及其寬度B間之空間A清晰可見。半導體元件如電 晶體或二極體亦位於墊金屬34之表面下面但圖3中看不 見。
本發明之全面結果為，一適當之阻尼及穩定之結構可 使任何型式之電半導體元件安排在墊金屬表面下面，在 黏接及測試期間發生之壓力下，即使無昂貴之方法變化 及不需增加任何額外方法，亦無任何損壞此等半導體元 件之危險。此外，現在可利用墊金屬表面下面之區域作 為電源供應軌道。
第13頁 200402863 圖式簡單說明 圖1為本發明積體半導體結構之範例實施例之剖面圖。 圖2為圖1之頂部二金屬層之部分互聯。 圖3為本發明積體半導體結構與墊金屬及互聯之平面圖。 元件符號說明： 1 基板 2 半導體元件及電晶體 3 墊金屬 4.1、4.χ、4·χ-1 金屬層 5.1、5.y、5.y-l 絕緣層 6 通孔 7. X 孔隙 D 1 頂部絕緣層5 . y之厚度 D3 墊金屬3之厚度 B 互聯4.x.z之寬度 8 鈍化 D2 頂部金屬層4. X之厚度 A 二互聯4 . X . z間之空間 F 墊金屬3之表面
第14頁

Claims (1)

  1. 200402863 六、申請專利範圍 1. 一種積體半導體結構，具有； 一基板（1 )， 至少一半導體元件（2 )位於該基板（1 )上， 一墊金屬（3)具有一表面（F)， 複數個金屬層（4 · X )，其位於該墊金屬（3 )與該基板（1 ) 之間， 複數個絕緣層（5 · y )，其將該金屬層（4 · X )彼此隔開， 該墊金屬（3) 延伸於該至少一半導體元件（2)上之至少 一部分之上， 其中，在該墊金屬（3)之該表面（F)下面，至少二頂部之 該金屬層（4 · X，4 · X - 1 )有一結構，該結構在每一例子中 至少包括二相鄰之互聯（4 · X · z，4 · X _ 1 . z ) 2. 如申請專利範圍第1項之積體半導體結構，其中在該墊 金屬（3)之該表面（F)下面之該金屬層（4·χ)之該互聯 (4·χ·ζ)數目z為2及6之間。 3. 如申請專利範圍第1或2項之積體半導體結構，其中在 一金屬層（4 · X )中之該互聯（4 · X · z )為彼此電絕緣。 4. 如申請專利範圍第1至3項之積體半導體結構，其中一 金屬層（4·χ)中之該互聯（4·χ·ζ )彼此為電連接。 5. 如申請專利範圍第1至4項之積體半導體結構，其中在 一金屬層（4·χ)中之該互聯（4·χ·ζ)有一寬度（B)及彼此間 有一空間（A )，該寬度（Β )與該空間（A )間之比值介於3及 2 0之間。 6 .如申請專利範圍第5項之積體半導體結構，其中該寬度
    第15頁 200402863 六、申請專利範圍 (B )與該空間（A )間之比值為1 0。 7 .如申請專利範圍第1至6項之積體半導體結構，其中至 少在該墊金屬（3)之該表面（F)下面，有複數個通孔（6)， 其將該頂部金屬層（4· X )之該互聯（4 . X · z )電連接至其下 之金屬層（4 · X - 1 )之該互聯（4 · X 1 · z )，該通孔6係穿過該 絕緣層（5 · y - 1 )。 8.如申請專利範圍第1至7項之積體半導體結構，其中在 至少該墊金屬（3)之該表面（F)下面，該頂部二金屬層 (4·χ，4·χ-1)之該互聯（4·χ·ζ，4·χ·-1·ζ )有複數個孔 隙（7·χ，7·χ-1) 〇 9 .如申請專利範圍第8項之積體半導體結構，其中，在至 少該墊金屬（3)之該表面（F)下面，該孔隙（7·χ，7·χ_1) 具有介於該互聯（4· X. ζ 4· χ-1 · ζ)總面積之5%及30%間之 總面積。 1 0 .如申請專利範圍第9項之積體半導體結構，其中該孔 隙（7 · X，7 · X - 1 )具有該互聯（4 · X · ζ，4 · X - 1 · ζ )總面積之 2 0 %之總面積。 Π .如申請專利範圍第8至1 0項之積體半導體結構，其中 該頂部二金屬層（4·χ，4·χ-1)之該互聯（4·χ·ζ，4·χ-1·ζ) 之排列方式為，在頂部之該互聯（4 · X · ζ )中之該孔隙 (7 · X )與在下面之該互聯中（4 · X - 1 · ζ )之該孔隙（7 · X - 1 )彼 此補償。 1 2 .如申請專利範圍第8至1 1項之積體半導體結構，其中 該頂部金屬層（4 · X )之該互聯（4 · X · ζ )約大致位於下部之
    第16頁 200402863 六、申請專利範圍 該金屬層（4.X-1)之該互聯（4·χ-1·ζ)之上。 1 3 .如申請專利範圍第8至1 2項之積體半導體結構，其中 該頂部金屬層（4 · X )之該互聯（4 · X · ζ )與下部之該金屬層 (4 · X - 1 )之該互聯（4 · X - 1 · ζ )為補償配置。 1 4.如申請專利範圍第1至1 3項之積體半導體結構，其中 該金屬層（4 . X)中至少大部分係由夠硬之金屬製成。 1 5 .如申請專利範圍第1 4項之積體半導體結構，其中該金 屬包含铭，銅，鶬，鉬，銀，金，翻或其合金。 1 6.如申請專利範圍第1至1 5項之積體半導體結構，其中 該墊金屬（3)之該表面（F)涵蓋一區域，其在一金屬層 (4·χ)内包含至少50% 金屬。 1 7.如申請專利範圍第1 6項之積體半導體結構，其中該金 屬均勻分布在該墊金屬（3)之該表面（F)下面。 1 8.如申請專利範圍第1至1 7項之積體半導體結構，其中 一頂部絕緣層（5 · y )係提供於該墊金屬（3 )與該頂部金屬 層（4 · X )之間，該頂部絕緣層（5 · y )有一第一厚度（D 1 )， 及該頂部金屬層（4. X)有一第二厚度（D2)，該二厚度 (D 1 ，D 2 )之比值介於1及5之間。 1 9.如申請專利範圍第1至1 8項之積體半導體結構，其中 該頂部絕緣層（5 · y )係提供於該墊金屬（3 )與該頂部金屬 層（4 · X )之間，該頂部金屬層（5 · y )有一厚度（D 1 )，該墊 金屬（3)有另一厚度（D3)，具該二厚度（D1 ，D3)間之比值 介於0. 5及3之間。 2 0 .如申請專利範圍第1 - 1 9項之積體半導體結構，其中該
    第17頁 200402863 六、申請專利範圍 金屬層（4·χ)之數目介於3與11之間。
    第18頁 111··
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