SU1401568A1 - Digital filter - Google Patents

Abstract

The invention relates to radio engineering. The purpose of the invention is to simplify the digital filter by reducing the number of multipliers. The filter contains adders (C) 1-4, multi-input C 5, lines 6-10 (LZ) delays, multipliers 11 and 12. LZ 13 and 14 were entered. El-delays (EZ) lines 6-10, -13, 14 provide a delay of signals for the following number of sampling frequency cycles: EZ 8, 9g, 50, 10 and 13, - for one cycle, EZ 8t, 8 13 - for two cycles, EZ t, 2 t Г 8, 9, and 4 on three cycles, EZ 8, 9, - five cycles, EZ 14 - six cycles, EZ 14, - seven cycles, LZ 6 and EZ 7 j - eight cycles, EZ 14 and 13 - ten and fourteen cycles, respectively. The input signal is fed to the input LZ 10, and from its output and retraction to the inputs of multipliers 11 and 12. The output signals of multipliers II and 12 are summed in C 1-4 with the same signals delayed in LZ 13 and 14. Output signals C 1 -4 arrive at the inputs of C 5 directly and through LZ 6-9. With 5 forms the output signal of the filter. 1 il. i (L

Description

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&& ЖЖЭ: ЕЕ l% z№lS ± TS r

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The invention relates to radio engineering and can be used in digital signal processing devices.

The purpose of the invention is to simplify the digital filter by decreasing the number of multipliers.

The drawing shows a structural electrical circuit of a digital filter.

The digital filter contains the first, second, third and fourth adders - 4, respectively, a multi-input adder 5, the first, BTOpjnos third, fourth and fifth lines 6-10 delay, respectively, the first Pi second 12 multipliers, the sixth 13 and the seventh 14 delay lines

The second delay line 7 contains the first 7, and the second 7 elements are

Up (Xp-, - xhp-b + Xn-t, .v + x „, + x„, + x „,, 8 Х.рН- Х„ -, -Хп. + Х.гй + 1- -29 + Х „.з, + Хп-, 2) +

+ 3 (X „+ Xn. + X„ .5 + X ,, + X „,„ + X „, + X, 5 +

 (7 П-1 5 n- 2Z n-ls X n-27 П-28 - М-30 S

where c,;, and р, are the multiplication factors of the second 12 and first P multipliers, respectively ;.

X is the input signal delayed by the i-clock of the sampling rate. In order to implement the difference equation (1), the delay elements of the lines 6-10, 13 and 14 from the first to the seventh delay provide the delay of the signals for the next number of clock cycles

sample rates. Elements 8

2 2.J

0 ,, 10 And 13 (delays - by one clock, elements 8 ,, 8 j-, 9 and 13, ,, delays - by. Two cycles. Elements 7, 8 9ts of delay. - by three cycles. Elements 8, 9 , delays - by five contacts. Golds 14.3 delays are six clocks, delay element 14 is seven clocks. Delay line 6 and delay element 7 are eight clocks. Delay elements 14 and 13 are ten and fourteen cycles respectively

The input signal of the digital filter comes to the input of the fifth delay line 10, and from its output and retraction to the inputs of the first 11 and second 12 multipliers, where it is multiplied by the coefficients p and oC, respectively.

The output signals of the first 11 and second 12 multipliers are summed in

The third delay line 8 contains the first to fifth elements 8, - 8 delays. The fourth line 9 delay contains the first to fourth elements 9 - 9 delay. The fifth delay line O contains the first 10 and second 10 delay elements. The sixth delay line 13 contains the elements 13, - 13-5 from the first to the third delay. The seventh line 14 delay contains elements 14 - 14 delays from the first to the third.

The digital filter works as follows.

The output of the digital filter is generated in accordance with the difference equation.

(one)

Q

five

0

the first, second, third, and fourth multipliers 1-4, respectively, with the same signals delayed in the sixth 13 and seventh 14 delay lines.

The output signals of the first to fourth adders 1-4 are fed to the inputs of the multi-input adder 5 directly and through the delay lines 6-9 from the first to the fourth, where they are delayed by the required number of cycles.

Multi-input adder 5 forms the output signal of the digital filter.

Claims (1)

Invention Formula A digital filter containing a multi-input cc matrix whose output is a digital filter output, a first delay line, the input and output of which are connected to the first and second inputs of a multi-input adder, respectively, a second delay line, whose input, output and output are connected to the third, fourth and fifth inputs of the multi-input adder, respectively, the third delay line, the input, the first, second, third, fourth taps and the upper end of which are connected to the sixth, seventh, eighth, ninth, tenth and eleventh inputs of multiple respectively, the even delay line, the input, the first, second, third taps and the output of which are connected to the twelfth, thirteenth, fourteenth, fifteenth and sixteenth inputs of the multiple input sum-, torus, respectively, first, second, third and fourth adders, whose outputs are connected to the inputs of the first, second, third and fourth delay lines, respectively, the first and second multipliers, whose outputs are connected to the first inputs of the third and fourth adders, respectively, and the fifth delay line, the input The trickle is in the course of the digital filter, and the output and the tap of the delay line are connected to the inputs of the first and second multipliers, respectively, characterized in that, in order to simplify the digital filter by reducing the number of multipliers, the pole and the seventh delay lines, whose inputs are connected to the outputs of the first and second multipliers, respectively, with the first tap of the sixth delay line connected to the first input of the second adder, the second tap of the sixth delay line connected to the second input of the fourth adder, sixth delay line coupled to a second input of the second adder, the first finger seventh delay line connected to the first input of the first adder, a second branch seventh delay line coupled to a second input of the third adder, and a seventh delay line output is connected to the second input of the first adder.