JPS5680916A - Interpolating filter for sampled value - Google Patents

Interpolating filter for sampled value

Info

Publication number
JPS5680916A
JPS5680916A JP15833279A JP15833279A JPS5680916A JP S5680916 A JPS5680916 A JP S5680916A JP 15833279 A JP15833279 A JP 15833279A JP 15833279 A JP15833279 A JP 15833279A JP S5680916 A JPS5680916 A JP S5680916A
Authority
JP
Japan
Prior art keywords
inputted
adder
multipliers
outputs
supplied
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15833279A
Other languages
Japanese (ja)
Other versions
JPS6320047B2 (en
Inventor
Akira Kanemasa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP15833279A priority Critical patent/JPS5680916A/en
Publication of JPS5680916A publication Critical patent/JPS5680916A/en
Publication of JPS6320047B2 publication Critical patent/JPS6320047B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00Networks using digital techniques
    • H03H17/02Frequency selective networks
    • H03H17/04Recursive filters
    • H03H17/0416Recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing
    • H03H17/0427Recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing characterized by the ratio between the input-sampling and output-delivery frequencies
    • H03H17/0438Recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing characterized by the ratio between the input-sampling and output-delivery frequencies the ratio being integer
    • H03H17/0444Recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing characterized by the ratio between the input-sampling and output-delivery frequencies the ratio being integer where the output-delivery frequency is higher than the input sampling frequency, i.e. interpolation
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H2218/00Indexing scheme relating to details of digital filters
    • H03H2218/06Multiple-input, multiple-output [MIMO]; Multiple-input, single-output [MISO]

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)
  • Filters That Use Time-Delay Elements (AREA)

Abstract

PURPOSE:To reduce the structure of hardware while decreasing the frequency of multiplication by using a recursive digital filter having the transfer relation satisfying specific conditions. CONSTITUTION:Multichannel, e.g. four-channel multiplexed data of sampling rate fSL is inputted to input terminal 1. The input data is supplied to adder 30, whose output is inputted to delay element 50 and multiplier 70. Outputs of delay elements 50-56 are inputted to multipliers 71-77 and those of elements 51, 53, 55, and 57 are inputted to multipliers 60-63, whose outputs are inputted to adder 33 and then supplied to adder 30. Output data of multipliers 70, 72, 74, and 76 are inputted to adder 31, and those of multipliers 71, 73, 75, and 77 to adder 32. Outputs of adders 31 and 32 are both inputted to selecting circuits 80 and 81 and with a timing signal from timing signal generating circuit 9, input signals are selected in time-division mode. Then, two-channel multiplexed signals of sampling frequency fSH=2fSL appear at output terminals 21 and 22.
JP15833279A 1979-12-06 1979-12-06 Interpolating filter for sampled value Granted JPS5680916A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15833279A JPS5680916A (en) 1979-12-06 1979-12-06 Interpolating filter for sampled value

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15833279A JPS5680916A (en) 1979-12-06 1979-12-06 Interpolating filter for sampled value

Publications (2)

Publication Number Publication Date
JPS5680916A true JPS5680916A (en) 1981-07-02
JPS6320047B2 JPS6320047B2 (en) 1988-04-26

Family

ID=15669321

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15833279A Granted JPS5680916A (en) 1979-12-06 1979-12-06 Interpolating filter for sampled value

Country Status (1)

Country Link
JP (1) JPS5680916A (en)

Also Published As

Publication number Publication date
JPS6320047B2 (en) 1988-04-26

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