SU1478300A1 - Digital filter - Google Patents

Abstract

The invention relates to radio engineering and can be used to filter processes represented by a digital code. The purpose of the invention is to improve the filtering accuracy while simplifying the center frequency tuning while maintaining the passband of the digital filter. The FC contains three adders 1,2,6, two delay elements 10.9, three multipliers 13, 14, 17. To achieve the goal, five adders 4, 3, 8, 7, 5, two delay elements 12, 11 and two are entered multiplier 15, 16. 2 Il.

Description

,,. ,, ,, A + F-WAZ; 1 +2 (2 A + AF) Z-2

pf T-25 (2A + B) (2 rA:: 2A + B-TTz-2-2 (2A-B) Z-3 + (1-2B) Z- t

H

where F, A, B are the multiplication factors of the first, fifth, and fourth multipliers, 13, 16, and 15, respectively. In this case, the center frequency of the digital filter is determined only by the value of /, since

s „-arccoso /.

where T is the quantization period of the input signal.

Claims (1)

Invention Formula A digital filter comprising a serially connected first multiplier, the input of which is an input of a digital filter, a first adder and a second adder, serially connected a first delay element and a second multiplier, the output of which is connected to the second input of the first adder, a second delay element whose input is connected with the output of the first delay element, the third adder and the third multiplier, connected in series, characterized in that, in order to increase the filtration accuracy while simplifying the transfer triple center frequency and maintaining the bandwidth of the digital filter, a sequence introduced 15 0 25 0 0 35 but the fourth multiplier is connected, the input of which is connected to the output of the second adder, the fourth adder and the fifth adder, the output of which is connected to the input of the first delay element, the fifth multiplier, the input of which is connected to the output of the second adder the adder, with the second and third inputs of the fourth adder, and is the output of a digital filter, the serially connected sixth adder, the first subtracting input of which is connected to the output of the fourth multiplier, the second subtracting the input and the first and second subtractive inputs of the second adder and connected to the output of the second delay element, and the first and second summing inputs of the sixth adder connected to the output of the fifth adder, the third delay element, the seventh adder, the second input of which is connected to the output of the third multiplier delays and the eighth adder, the first and second subtractive inputs are connected to the second summing input of the second adder, to the summing input of the third adder and to the input of the first multiplier, and the output is connected to the second input home fifth adder. Compiled by E. Borisov Editor A. Motyl Tehred A. Kravchuk Proofreader O. Kravtsova Order 2371/53 Circulation 885 VNIIPI State Committee for Inventions and Discoveries at the State Committee on Science and Technology of the USSR 113035, Moscow, Zh-35, Raushsk nab., D. A / 5 Production and Publishing Combine Patent, Uzhgorod, st. Gagarin, 101 Subscription