SU1499430A1 - Rejection digital filter - Google Patents

Abstract

The invention relates to radio engineering. The purpose of the invention is to simplify the restructuring of the notch digital filter. The filter contains adders 1 and 2, algebraic adders 3-6, el-delay delay 7-10 and multipliers 11-14. The goal is achieved by providing for all links of the multilink digital notch filter the same value of the coefficient α, which determines the frequency of notch. 2 Il.

Description

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The invention relates to radio engineering and can be used in communication technicians, automation, etc.

The purpose of the invention is to simplify the adjustment of the notch digital filter.

FIG. 1 shows a structural electrical notch digital filter; in fig. 2 - his graph.

The notch digital filter contains first and second adders 1 and 2, first to fourth algebraic adders 3-6, first to fourth delay elements 7-10, and first to fourth multipliers 11-14

Notch digital filter works in the following way. .

The signals from the outputs of the first and third delay elements 7 and 9 are multiplied by the factors ot and c in the second and third multipliers 12 and 13, respectively. The output of the first and third delay elements is recorded in the second and fourth delay elements 8 and 10, respectively, in the third algebraic adder 5 the input signal and the signals from the outputs of the second delay element 8 and the second multiplier 12 are summed. In the first algebraic adder 3 the signals from the third outputs are summed an algebraic adder 5, a fourth delay element 10, and a third multiplier 13. The signal from the output of the first

0 5 where

five

0

the algebraic adder 3 is multiplied by the factor b in the first multiplier 11, the output signals of the first algebraic adder 3 and the first multiplier 11 are added in the first adder 1, the output signal of the first adder 1 is multiplied by the factor b in the fourth multiplier 14, the output signals of the first adder 1 and the fourth The multiplier 14 is added to the second adder 2, the output of the second adder 2 is fed to the output of the filter. In the second algebraic adder 4, the input signal is summed with the code signals of the first and second multipliers 11 and 12. The output signal of the second algebraic adder 4 is recorded into the first delay element 7, the fourth algebraic adder 6 summarizes the output signals of the third algebraic matrix 5 and the first, third and the fourth multipliers 1 1, 13 and 14. Next, the operation of the notch digital filter is repeated for new values of the input signal.

Starting from the graph (Fig. 2), the transfer function of the notch digital filter is found.

H (Z) S) tf

N (Z)

M (zT

N (Z) (1 + b4) (H-bi) (1-2oi, Z + Z) (1-2rfiZ l + Z); M (Z) 1 - (oi, + ftii + b 2 (oi, - Oi) + b, “i2 (1 + bj)) Z- +

,-one

+ (1 + bj) (b, h-сг, Ы (1 + b)) Z.

- (2bjei2 + b, (1 + b),).

The main application of the device is associated with the condition odj 0, - On,

H (Z)

., Ll. ± ilLlt ilLl-2 z l ± z ll

1 - GG (2 + 7 () (1 + b2) (b, (T + bTT), (2b2 + b7 (T + b) z + bJz--

CD

The transfer function (1) can: os b V O te - be obtained using the transform. 2

neither

from the analogue low-pass filter of the second prototype In this case, the coefficient o opr - yT. a V determines the frequency of the rejection, and the coefficient 1 - 2clZ + Zcents b and b - the notch band.

,-one

Then the transfer function takes the form

The value of the coefficient ci is the same for all links of the multilink relay digital filter, which allows to simplify its restructuring, while reducing the volume of the ROM of the coefficients.

For Butterworth filters is the same and the value of the coefficients b in the multi-tier digital filter,

Claims (1)

Invention Formula A digital filter containing a first algebraic adder, a multiplier and an adder, a second algebraic adder, whose inverting inputs are input of a recursive digital filter, a first and second elements of the rear and a third algebraic adder, and a second multiplier, input which is connected to the output of the first delay element, and the output of the second multiplier is connected to the first non-inverting inputs of the second and third algebraic adders about lichayuschiys in that, in order to simplify adjustment rezhek- iterated digital filter, a third multiplier administered sequentially a connected quarter multiplier and a second adder, the output of which is the output of the digital notch filter, and a fourth algebraic adder connected in series, the third and quarter delay elements, the output of which is connected to the first non-inverting input of the first algebraic adder, and the output of the third delay element is connected via a third multiplier to the first non-inverting input of the fourth and the inverting input of the first algebraic adders, the output of which is connected to the second input of the first total pa whose output is connected to the second input of the second adder and the input of the fourth multiplier, the output of which is connected to the inverting input of the fourth algebraic adder, the second non-inverting input of which is connected to the output of the first multiplier and the second non-inverting input of the second algebraic adder, the inverting input of which is connected to the second non-inverting invertor. the third algebraic adder, the output of which is connected to the second and third non-inverting inputs of the first and fourth algebraic adders accordingly.