CA1288483C - Low frequency digital notch filter - Google Patents
Low frequency digital notch filterInfo
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- CA1288483C CA1288483C CA000514260A CA514260A CA1288483C CA 1288483 C CA1288483 C CA 1288483C CA 000514260 A CA000514260 A CA 000514260A CA 514260 A CA514260 A CA 514260A CA 1288483 C CA1288483 C CA 1288483C
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Abstract
ABSTRACT
A low frequency digital notch filter comprising two sub-filters - an all-pass-network filter and a T-section filter with a feedback connection from the T-filter to an input node, and feed forward connection from this input node to a terminal output node. The all-pass-network filter has a transform function:-A(Z) = [Z-1+K]/[1+K1Z-1]; and the T-section filter has throughput and tap transform functions:-B(Z)=[(K3+R2.K4)Z-1-1]/[1-K3Z-1]
and, C(Z)=K2Z-1/[1 - K3Z-1], where Z-1 is the unit delay operator and K1 to K4 are multiplier coefficients. The T-section filter may be implemented using a combination of three multipliers and a delay element.
A low frequency digital notch filter comprising two sub-filters - an all-pass-network filter and a T-section filter with a feedback connection from the T-filter to an input node, and feed forward connection from this input node to a terminal output node. The all-pass-network filter has a transform function:-A(Z) = [Z-1+K]/[1+K1Z-1]; and the T-section filter has throughput and tap transform functions:-B(Z)=[(K3+R2.K4)Z-1-1]/[1-K3Z-1]
and, C(Z)=K2Z-1/[1 - K3Z-1], where Z-1 is the unit delay operator and K1 to K4 are multiplier coefficients. The T-section filter may be implemented using a combination of three multipliers and a delay element.
Description
g~ 34~3~
~l--Low Frequency Digital Notch Filter Technical Field The present invention concerns improvements in or relating to the design of low frequency digital notch filters and, composite filters incorporating the same.
There are many Digital Signal Processing (DSP) applications where one of the functions required is a filter to reject any low frequency signals, and possibly in addition, to reject any DC component of the signal. A
typical application of such a filter arises where the digital signal being processed is a digital representation of an analogue signal where the analogue signal contains unwanted signals at 50Hz or 60Hz. These signals can arise as signals coupled into the system from nearby line powered equipment. It is often necessary to remove these unwanted signals together with any DC component that is present.
Background Art A number of different filter structures have hitherto been considered for implementing such a filter, particularly for applications where the frequencies of signals that are to be rejected are but a small fraction of the system sampling rate (approx. 1%). When considering the suitability of such structures, a number of aspects of their performance must be considered. To ensure easy and ~ ~8~4~33 efficient implementation, it is desirable that the filter should have a reasonably regular structure~ Also, considering cost factors, it should have a minimum of complexity. It is also a requisite that the number of multiplications be kept to a minimum and it is preferable that the wordlength of multiplier coefficients also be kept to a minimum. There are other performance considerations that lead to a need for increased signal wordlength. Recursive filter structures tend to amplify any quantisation noise which must inveriably occur during the truncation operation that follows any multiplier stage. It is usual to compensate for this amplification by adopting additional bits in the signal wordlength in order to keep filter noise at an acceptable level. The lS signal amplitudes at internal nodes of the filter must also be considered. A filter with a high effective Q-factor may have signals at internal nodes as much as 40dB higher in amplitude than the input signal, at certain frequencies, even if the overall gain is unity. Clipping is prevented again by increasing signal wordlength.
By way of example, consider an application requiring the~rejection of signals at 50Hz and 60Hz by at least 25dB, rejection of all components at DC, with less than 0.7dB
attenuation of signals or 200Hz at a system sampling rate Z5 of 8Hz.
B
4~3~3 A filter comprised of biquadratic sections would b~
very regular and easy to implement. However, such a filter optimised for best noise and signal growth performance, would include as many as fourteen 9-bit multipliers and six delay elements. This would have a noise amplification of approx. 13dB with noise gain at internal nodes of OdB. The signal wordlength would n~ed to be increased by an additional three bits fQr filter compensation as aforesaid. It should howev~r be noted that many alternative structures exist. Thus for example, a filter with considerably worse signal growth performance could be implemented using eleven multipliers and five delay elements.
Disclosure of the Invention It is intended to provide a digital filter of reasonably regular structure, but one with less complexity for equivalent or better performance than that provided hitherto.
In accordance with the invention there is provided a low frequency digital notch filter comprising:-an input node;
an all-pass network first filter stage having an input and an output, said input being connected to said input node, the first filter stage including at least one first delay element and at least one first coefficient multiplier for multiplication by a coefficient K1, the ~3 ~ ~84~3~
first delay element and first coefficient multiplier being interconnected in such a way as to provide a transfer function A(Z) for the first stage as follows:
A(Z)=(Z~n+Kl)/(l~K1Z n), where n~1;
a second filter stage having an input and an output, the input of the second filter stage being coupled to the output of the first filter stage, the second filter stage including a second delay element and three second coefficient multipliers for multiplication by coefficients K2, K3 and K4 respectively, the second delay element and second multipliers being so interconnected that the transfer function B~Z) for the second stage is as follows~
B(Z)=t(K3+K2-K4)Z n 1]/(1-K3Z n), wherein n~l;
a filter output node coupled to the output of the second filter stage; and a feedforward line coupled between said input node and said output node for summing the filter input with the output of the second stage~ whereby to provide a notch characteristic at a desired frequency.
The notch filter aforesaid may be combined in series with a DC-rejection filter, according to the application.
According to a further aspect of the invention, there is provided a T-section filter for use in a distal notch filter as recited above, and including a delay element and three coefficient multipliers for ~884~
- 4a -multiplication by coefficients K2, K3 and K4 respectively, the delay element and multipliers being so interconnected that the transfer function B(Z) for said T-section filter is as follows:
B(Z~=t(K3~K2-K4)Z n-l]/(l-K3z n~, where n~1;
and said T-section filter having a tapping node located at the output of the delay element, such that the transfer function C(Z) between the input to sai~ T-s~ction filter and the tapping point is given as follows:
C(Z~ = K~Z n/(l-X3Z n), where n~1:
and a feedback line coupled between said tapping point and said input.
Brief Introduction to the Drawinqs In the drawings accompanying this application:-Figure 1 is a circuit diagram of a low frequencydigital notch filter implemented in accordance with the invention:
.; .,, 2 ~8~.3 5_ Figure 2 is a circuit diagram of a DC-rejection filter for use in combination with the notch filter shown in the preceding figure; and, Figure 3 is a graph showing a typical gain frequency response specification, and a frequency response attainable using a combination of the filters shown in the preceding figures.
Description of a Preferred Embodiment An embodiment of the inven~ion will now be described, by way of example only, with particular reference to the drawings aforesaid.
The low frequency notch filter section of a composite rejection filter is shown in figure l. Essentially, this section is comprised of two sub-filters, an all-pass-network filter l and a T-section filter 3.
The all-pass-network filter l incorporates a delay element 5 and a coPfficient multiplier 7. The transform function of this filter l has the form A(Z) given by the expression:
AIZj = (Z-l + Kl) / (l + K1Z-l), where K is the value of coefficient applied to the multiplier 7. It may be implemented by a standard recursive structure - See, for example, structures described in the article "Digital Signal Processin~ Schemes for Efficient Interpolation and Decimation" by RIA.Valerzuela and R.G.Constantinides, 3.,~
IEE Proc. Vo. 130 Pt.G No. 6 (Dec 1983) P. 232. The all-pass-network filter ~, shown, includes branch nodes 9 and 11 between a common input, the delay element 5 and the multiplier 7. It also includes an output node 13 which is connected to the output of the delay element 5, and the output of the multiplier 7. Cross-connections 15 and 17 respectively, are provid~d between the output o~ the delay element 5 and the input of the multiplier 7 via branch node 11, and between the output of the multiplier 7 and the input of the delay element 5, via the branch node 9.
The T-section filter 3 is connected to the output node 13 of the all-pass-network filter 1. It is comprised of three multipliers 19, 21 and 23 which provide multipli-cation by coefficients K2, K3 and K4 respectively. The transform functions B(Z) and C(Z) of this filter 3 have the form given in the following expressions:-B(Z)=[(Kl K4~K3)z 1-1]/[1-K3z 1]; and, (input-to-output.) C(Z)=K2Z /[l-K3Z ].
(input-to-tap.) In the implementation of this filter 3, as shown in figure l, the~multiplier 19, a branch node 27, the delay unit 25 and the multiplier 21 are connected in series and the delay unit 25 is shunted by the multiplier 23, via ~ ~B~3 the branch node 27. The output of the multiplier 21 is connected to an output node 29. This latter node 29 is also connected to the T-filter input for subtracting input signal.
The low frequency notch filter section is completed by an input node 31 and a terminal output node 33. A feedback signal is extracted from the T-section filter 3 from a point in the signal path between the delay unit 25 and the multiplier 21, and subtracted from the input signal at the input node 31. The output signal from the node 31 is fed in parallel to the input of the all-pass-network filter 3 and to the output node 33, where it summed with the output signal of the T section filter 3.
The low frequency notch filter section shown in figure 1 also includes a fifth multiplier 35 which is connected to the output of the output node 33. This latter introduces further multiplication by a coefficient K5, of value 1.
The DC-rejection filter section of the composite filter is shown in figure 2~. This latter section is connected in series with the low frequency notch filter sectlon described above. Essentially this section is comprised of an all-pass-network filter 1 and an output node 37. The input signal to this section is fed in parallel to the network filter 1 and to the output node 37. At this node 37 the input signal is subtracted from 1~84~33 signal from the output of the network filter 1. The all-pass-network filter 1 may be of identical configuration to that previously described with reference to figure 1.
The multiplier 7 in this case provides multiplication by a coefficient K6. In the DC-rejection filter shown in figure 2, the output node 37 is connected to a seventh multiplier 3g. This multiplier 39 introduces further multiplication by a coefficient K7 of value 1/2. This choice of DC-rejection filter offers improvement performance compared with its biquadratic section counterpart, and is very similar in form to the notch filter, thus improving the potential for efficient implementation.
~ A typical performance specification is illustrated in figure 3. Rejection at 50Hz is required and a level response for frequencies above 200Hz. Suitable values for the coefficients Kl to K7 are given in Table 1 appearing below:-20 Coefficient Value Kl ~ [1-3/16]
K4 ~ 1/4 K6 ~ [1-1/32]
~-~8~34~33 As can be seen from figure 3, the required performance is readily achieved when the coefficients given above are adopted. The figure shows DC-rejection, lo~ frequencY
rejection at 50Hz, and, a near level response at frequencies above 200Hz.
The following table gives the performance of the two sections, figs 1 and 2, taken together.
Structure: Reasonably regular, uses simple all-pass-network as the basic building block for the filter.
Complexity: 7 multipliers, 3 delay elements.
Multipliers: 7 bit, although 4 of the 7 multipliers, being simply a division by a power of two can be very simply implemented.
Noise amplification: approx. lOdB.
Maximum noise gain at internal nodes: 3dB.
Signal wordlength: 3 additional bits required to compensate for filter.
It can be seen that this stucture offers a number of improvements over more conventional structures, at the expense of a slightly less regular structure. It manages to achieve similar performance to the biquadratic section filter examined earlier for a giYen signal wordlength using half the number of storage elements and half the number of multipliers, and with the multiplications in many cases being trivial, eg 1/2 etc.
3 ~884~33 The coefficients K1 to K7 may be varied to meet the requirements of other applications, in particular to vary the frequency of t'ne notch filter relative to the samplin~ frequency~ One of the advantages of the stru~ture aforesaid is that many of the multiplications may be performed trivially ie. using divide-by-two cascades, even when the coefficients are altered to conform to a different requirement. Thus referring to figures 1 and 2, the coefficients K5 and K7 would always be chosen equal to 1/2. It can usually ~e arranged for one if not both of the coefficients K2 and K4 to be a power of 1/2 and the coefficient K3 to be related to the coefficients K2 and K4 as follows~ K3 = 1 - (2 * K2 * K4).
~l--Low Frequency Digital Notch Filter Technical Field The present invention concerns improvements in or relating to the design of low frequency digital notch filters and, composite filters incorporating the same.
There are many Digital Signal Processing (DSP) applications where one of the functions required is a filter to reject any low frequency signals, and possibly in addition, to reject any DC component of the signal. A
typical application of such a filter arises where the digital signal being processed is a digital representation of an analogue signal where the analogue signal contains unwanted signals at 50Hz or 60Hz. These signals can arise as signals coupled into the system from nearby line powered equipment. It is often necessary to remove these unwanted signals together with any DC component that is present.
Background Art A number of different filter structures have hitherto been considered for implementing such a filter, particularly for applications where the frequencies of signals that are to be rejected are but a small fraction of the system sampling rate (approx. 1%). When considering the suitability of such structures, a number of aspects of their performance must be considered. To ensure easy and ~ ~8~4~33 efficient implementation, it is desirable that the filter should have a reasonably regular structure~ Also, considering cost factors, it should have a minimum of complexity. It is also a requisite that the number of multiplications be kept to a minimum and it is preferable that the wordlength of multiplier coefficients also be kept to a minimum. There are other performance considerations that lead to a need for increased signal wordlength. Recursive filter structures tend to amplify any quantisation noise which must inveriably occur during the truncation operation that follows any multiplier stage. It is usual to compensate for this amplification by adopting additional bits in the signal wordlength in order to keep filter noise at an acceptable level. The lS signal amplitudes at internal nodes of the filter must also be considered. A filter with a high effective Q-factor may have signals at internal nodes as much as 40dB higher in amplitude than the input signal, at certain frequencies, even if the overall gain is unity. Clipping is prevented again by increasing signal wordlength.
By way of example, consider an application requiring the~rejection of signals at 50Hz and 60Hz by at least 25dB, rejection of all components at DC, with less than 0.7dB
attenuation of signals or 200Hz at a system sampling rate Z5 of 8Hz.
B
4~3~3 A filter comprised of biquadratic sections would b~
very regular and easy to implement. However, such a filter optimised for best noise and signal growth performance, would include as many as fourteen 9-bit multipliers and six delay elements. This would have a noise amplification of approx. 13dB with noise gain at internal nodes of OdB. The signal wordlength would n~ed to be increased by an additional three bits fQr filter compensation as aforesaid. It should howev~r be noted that many alternative structures exist. Thus for example, a filter with considerably worse signal growth performance could be implemented using eleven multipliers and five delay elements.
Disclosure of the Invention It is intended to provide a digital filter of reasonably regular structure, but one with less complexity for equivalent or better performance than that provided hitherto.
In accordance with the invention there is provided a low frequency digital notch filter comprising:-an input node;
an all-pass network first filter stage having an input and an output, said input being connected to said input node, the first filter stage including at least one first delay element and at least one first coefficient multiplier for multiplication by a coefficient K1, the ~3 ~ ~84~3~
first delay element and first coefficient multiplier being interconnected in such a way as to provide a transfer function A(Z) for the first stage as follows:
A(Z)=(Z~n+Kl)/(l~K1Z n), where n~1;
a second filter stage having an input and an output, the input of the second filter stage being coupled to the output of the first filter stage, the second filter stage including a second delay element and three second coefficient multipliers for multiplication by coefficients K2, K3 and K4 respectively, the second delay element and second multipliers being so interconnected that the transfer function B~Z) for the second stage is as follows~
B(Z)=t(K3+K2-K4)Z n 1]/(1-K3Z n), wherein n~l;
a filter output node coupled to the output of the second filter stage; and a feedforward line coupled between said input node and said output node for summing the filter input with the output of the second stage~ whereby to provide a notch characteristic at a desired frequency.
The notch filter aforesaid may be combined in series with a DC-rejection filter, according to the application.
According to a further aspect of the invention, there is provided a T-section filter for use in a distal notch filter as recited above, and including a delay element and three coefficient multipliers for ~884~
- 4a -multiplication by coefficients K2, K3 and K4 respectively, the delay element and multipliers being so interconnected that the transfer function B(Z) for said T-section filter is as follows:
B(Z~=t(K3~K2-K4)Z n-l]/(l-K3z n~, where n~1;
and said T-section filter having a tapping node located at the output of the delay element, such that the transfer function C(Z) between the input to sai~ T-s~ction filter and the tapping point is given as follows:
C(Z~ = K~Z n/(l-X3Z n), where n~1:
and a feedback line coupled between said tapping point and said input.
Brief Introduction to the Drawinqs In the drawings accompanying this application:-Figure 1 is a circuit diagram of a low frequencydigital notch filter implemented in accordance with the invention:
.; .,, 2 ~8~.3 5_ Figure 2 is a circuit diagram of a DC-rejection filter for use in combination with the notch filter shown in the preceding figure; and, Figure 3 is a graph showing a typical gain frequency response specification, and a frequency response attainable using a combination of the filters shown in the preceding figures.
Description of a Preferred Embodiment An embodiment of the inven~ion will now be described, by way of example only, with particular reference to the drawings aforesaid.
The low frequency notch filter section of a composite rejection filter is shown in figure l. Essentially, this section is comprised of two sub-filters, an all-pass-network filter l and a T-section filter 3.
The all-pass-network filter l incorporates a delay element 5 and a coPfficient multiplier 7. The transform function of this filter l has the form A(Z) given by the expression:
AIZj = (Z-l + Kl) / (l + K1Z-l), where K is the value of coefficient applied to the multiplier 7. It may be implemented by a standard recursive structure - See, for example, structures described in the article "Digital Signal Processin~ Schemes for Efficient Interpolation and Decimation" by RIA.Valerzuela and R.G.Constantinides, 3.,~
IEE Proc. Vo. 130 Pt.G No. 6 (Dec 1983) P. 232. The all-pass-network filter ~, shown, includes branch nodes 9 and 11 between a common input, the delay element 5 and the multiplier 7. It also includes an output node 13 which is connected to the output of the delay element 5, and the output of the multiplier 7. Cross-connections 15 and 17 respectively, are provid~d between the output o~ the delay element 5 and the input of the multiplier 7 via branch node 11, and between the output of the multiplier 7 and the input of the delay element 5, via the branch node 9.
The T-section filter 3 is connected to the output node 13 of the all-pass-network filter 1. It is comprised of three multipliers 19, 21 and 23 which provide multipli-cation by coefficients K2, K3 and K4 respectively. The transform functions B(Z) and C(Z) of this filter 3 have the form given in the following expressions:-B(Z)=[(Kl K4~K3)z 1-1]/[1-K3z 1]; and, (input-to-output.) C(Z)=K2Z /[l-K3Z ].
(input-to-tap.) In the implementation of this filter 3, as shown in figure l, the~multiplier 19, a branch node 27, the delay unit 25 and the multiplier 21 are connected in series and the delay unit 25 is shunted by the multiplier 23, via ~ ~B~3 the branch node 27. The output of the multiplier 21 is connected to an output node 29. This latter node 29 is also connected to the T-filter input for subtracting input signal.
The low frequency notch filter section is completed by an input node 31 and a terminal output node 33. A feedback signal is extracted from the T-section filter 3 from a point in the signal path between the delay unit 25 and the multiplier 21, and subtracted from the input signal at the input node 31. The output signal from the node 31 is fed in parallel to the input of the all-pass-network filter 3 and to the output node 33, where it summed with the output signal of the T section filter 3.
The low frequency notch filter section shown in figure 1 also includes a fifth multiplier 35 which is connected to the output of the output node 33. This latter introduces further multiplication by a coefficient K5, of value 1.
The DC-rejection filter section of the composite filter is shown in figure 2~. This latter section is connected in series with the low frequency notch filter sectlon described above. Essentially this section is comprised of an all-pass-network filter 1 and an output node 37. The input signal to this section is fed in parallel to the network filter 1 and to the output node 37. At this node 37 the input signal is subtracted from 1~84~33 signal from the output of the network filter 1. The all-pass-network filter 1 may be of identical configuration to that previously described with reference to figure 1.
The multiplier 7 in this case provides multiplication by a coefficient K6. In the DC-rejection filter shown in figure 2, the output node 37 is connected to a seventh multiplier 3g. This multiplier 39 introduces further multiplication by a coefficient K7 of value 1/2. This choice of DC-rejection filter offers improvement performance compared with its biquadratic section counterpart, and is very similar in form to the notch filter, thus improving the potential for efficient implementation.
~ A typical performance specification is illustrated in figure 3. Rejection at 50Hz is required and a level response for frequencies above 200Hz. Suitable values for the coefficients Kl to K7 are given in Table 1 appearing below:-20 Coefficient Value Kl ~ [1-3/16]
K4 ~ 1/4 K6 ~ [1-1/32]
~-~8~34~33 As can be seen from figure 3, the required performance is readily achieved when the coefficients given above are adopted. The figure shows DC-rejection, lo~ frequencY
rejection at 50Hz, and, a near level response at frequencies above 200Hz.
The following table gives the performance of the two sections, figs 1 and 2, taken together.
Structure: Reasonably regular, uses simple all-pass-network as the basic building block for the filter.
Complexity: 7 multipliers, 3 delay elements.
Multipliers: 7 bit, although 4 of the 7 multipliers, being simply a division by a power of two can be very simply implemented.
Noise amplification: approx. lOdB.
Maximum noise gain at internal nodes: 3dB.
Signal wordlength: 3 additional bits required to compensate for filter.
It can be seen that this stucture offers a number of improvements over more conventional structures, at the expense of a slightly less regular structure. It manages to achieve similar performance to the biquadratic section filter examined earlier for a giYen signal wordlength using half the number of storage elements and half the number of multipliers, and with the multiplications in many cases being trivial, eg 1/2 etc.
3 ~884~33 The coefficients K1 to K7 may be varied to meet the requirements of other applications, in particular to vary the frequency of t'ne notch filter relative to the samplin~ frequency~ One of the advantages of the stru~ture aforesaid is that many of the multiplications may be performed trivially ie. using divide-by-two cascades, even when the coefficients are altered to conform to a different requirement. Thus referring to figures 1 and 2, the coefficients K5 and K7 would always be chosen equal to 1/2. It can usually ~e arranged for one if not both of the coefficients K2 and K4 to be a power of 1/2 and the coefficient K3 to be related to the coefficients K2 and K4 as follows~ K3 = 1 - (2 * K2 * K4).
Claims (10)
1. A low frequency digital notch filter comprising:-an input node;
an all-pass network first filter stage having an input and an output, said input being connected to said input node, the first filter stage including at least one first delay element and at least one first coefficient multiplier for multiplication by a coefficient K1, the first delay element and first coefficient multiplier being interconnected in such a way as to provide a transfer function A(Z) for the first stage as follows:
A(Z)=(Z-n+K1)/(1+K1Z-n), where n?1;
a second filter stage having an input and an output, the input of the second filter stage being coupled to the output of the first filter stage, the second filter stage including a second delay element and three second coefficient multipliers for multiplication by coefficients K2, K3 and K4 respectively r the second delay element and second multipliers being so interconnected that the transfer function B(Z) for the second stage is as follows:
B(Z)=[(K3+K2.K4)Z-n-1]/(1-K3Z-n), wherein n?l;
a filter output node coupled to the output of the second filter stage; and a feedforward line coupled between said input node and said output node for summing the filter input with the output of the second stage, whereby to provide a notch characteristic at a desired frequency.
an all-pass network first filter stage having an input and an output, said input being connected to said input node, the first filter stage including at least one first delay element and at least one first coefficient multiplier for multiplication by a coefficient K1, the first delay element and first coefficient multiplier being interconnected in such a way as to provide a transfer function A(Z) for the first stage as follows:
A(Z)=(Z-n+K1)/(1+K1Z-n), where n?1;
a second filter stage having an input and an output, the input of the second filter stage being coupled to the output of the first filter stage, the second filter stage including a second delay element and three second coefficient multipliers for multiplication by coefficients K2, K3 and K4 respectively r the second delay element and second multipliers being so interconnected that the transfer function B(Z) for the second stage is as follows:
B(Z)=[(K3+K2.K4)Z-n-1]/(1-K3Z-n), wherein n?l;
a filter output node coupled to the output of the second filter stage; and a feedforward line coupled between said input node and said output node for summing the filter input with the output of the second stage, whereby to provide a notch characteristic at a desired frequency.
2. A filter according to claim 1, wherein the second filter stage has a tapping node located at the output of the second delay element, such that the transfer function C(Z) between the input to the second stage and the tapping point is given as follows:
C(Z) = K2Z-n/(1-K3Z-n), where n?1;
and a feedback line coupled between said tapping point and said input node.
C(Z) = K2Z-n/(1-K3Z-n), where n?1;
and a feedback line coupled between said tapping point and said input node.
3. A notch filter as claimed in claim 1 or 2, wherein two of said three second coefficient multipliers are connected one each side of the second delay element, and the remaining second coefficient multiplier is shunted across said second delay element via a branch node, an output node being included to subtract signal introduced at a common input from signal output from said second coefficient multipliers.
4. A notch filter as claimed in either claim 1 or 2, wherein the value of coefficient K3 is related to the coefficients K2 and K4 by the expression:-K3 = 1-(2*K2*K4) and the coefficients K2 and K4 are powers of 1/2.
5. A notch filter as claimed in either claim 1 or 2, and including a fifth multiplier for multiplication by a coefficient K5 of value 1/2, connected to said notch filter output node.
6. A composite filter comprising a notch filter as claimed in claim 1 and a DC-rejection filter connected in series therewith.
7. A composite filter as claimed in claim 6, wherein said DC-rejection filter comprises a common input;
an all-pass-network filter of identical construction to said first filter stage; and a node connected to the common input and the output of the all-pass-network filter to subtract input signal from filter output signal.
an all-pass-network filter of identical construction to said first filter stage; and a node connected to the common input and the output of the all-pass-network filter to subtract input signal from filter output signal.
8. A composite filter, as claimed in claim 6 or 7, wherein a seventh multiplier for multiplication by a coefficient K7 of value 1/2, is included at the output of the DC-rejection filter.
9. A T-section filter for use in a low frequency notch filter as defined in claim 1, said T-section filter having an input and an output, and including a delay element and three coefficient multipliers for multiplication by coefficients K2, K3 and K4 respectively, the delay element and multipliers being so interconnected that the transfer function B(Z) for said T-section filter is as follows:
B(Z)=[(K3+K2.K4)Z-n-1]/(1-K3Z-n), where n?1;
and said T-section filter having a tapping node located at the output of the delay element, such that the transfer function C(Z) between the input to said T-section filter and the tapping point is given as follows:
C(Z) = K2Z-n/(1-K3Z-n), where n?1;
and a feedback line coupled between said tapping point and said input.
B(Z)=[(K3+K2.K4)Z-n-1]/(1-K3Z-n), where n?1;
and said T-section filter having a tapping node located at the output of the delay element, such that the transfer function C(Z) between the input to said T-section filter and the tapping point is given as follows:
C(Z) = K2Z-n/(1-K3Z-n), where n?1;
and a feedback line coupled between said tapping point and said input.
10. A T-section filter as claimed in claim 9, wherein two of said multipliers are connected one each side of the delay element, and the remaining multiplier is shunted across the delay element via a branch node, and output node being included to subtract signal introduced at a common input from signal output from said multipliers.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB8521378 | 1985-08-28 | ||
| GB858521378A GB8521378D0 (en) | 1985-08-28 | 1985-08-28 | Digital notch filter |
| GB8522643A GB2182513B (en) | 1985-08-28 | 1985-09-12 | Low frequency digital notch filter |
| GB8522643 | 1985-09-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1288483C true CA1288483C (en) | 1991-09-03 |
Family
ID=26289707
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000514260A Expired - Fee Related CA1288483C (en) | 1985-08-28 | 1986-07-21 | Low frequency digital notch filter |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPH0693599B2 (en) |
| CN (1) | CN1009519B (en) |
| BG (1) | BG46609A3 (en) |
| CA (1) | CA1288483C (en) |
| FI (1) | FI91468C (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105659496A (en) | 2014-03-13 | 2016-06-08 | 联发科技股份有限公司 | Feedforward filter using translational filter |
| EP3725017A1 (en) * | 2017-12-13 | 2020-10-21 | Telefonaktiebolaget LM Ericsson (publ) | Method of estimating a propagation delay difference of an optical link and apparatus for same |
-
1986
- 1986-07-21 CA CA000514260A patent/CA1288483C/en not_active Expired - Fee Related
- 1986-08-22 BG BG7625286A patent/BG46609A3/en unknown
- 1986-08-26 FI FI863448A patent/FI91468C/en not_active IP Right Cessation
- 1986-08-26 CN CN 86105367 patent/CN1009519B/en not_active Expired
- 1986-08-27 JP JP20118586A patent/JPH0693599B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| FI91468C (en) | 1994-06-27 |
| FI91468B (en) | 1994-03-15 |
| FI863448A0 (en) | 1986-08-26 |
| JPS6251819A (en) | 1987-03-06 |
| JPH0693599B2 (en) | 1994-11-16 |
| CN1009519B (en) | 1990-09-05 |
| BG46609A3 (en) | 1990-01-15 |
| CN86105367A (en) | 1987-02-25 |
| FI863448A (en) | 1987-03-01 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKLA | Lapsed |