CA1269723A - Notch filter for an interpolator/decimator filter structure - Google Patents

Abstract

ABSTRACT
A NOTCH FILTER FOR AN INTERPOLATOR/DECIMATOR
FILTER STRUCTURE
A filter structure including a notch filter (C) designed to have a transmission zero at a frequency slightly displaced from one half of the lower sampling rate of the interpolator/decimator, and thus providing increase in attenuation at the half-rate frequency.
The notch filter (C) is comprised of two like all-pass-network filters (31 and 33) and has feed forward and feedback connections (39 and 41), the latter connection (41) including a coefficient multiplier (43).
The feedback connection (41) is made between a tapped output (T) of the second of the network filters, filter (33) and an input node (35).
The tapped filter,(33) is characterised by throughput and a tapped output transform functions X(Z) and Y(Z) given by the following expressions:-X(Z) = [Z-1 - K]/ [1 - KZ-1]; and, Y(Z) = .alpha. Z-1/ [1 - KZ-1];
where Z-1 is the unit delay operator, K the multiplier coefficient and, .alpha. , a structure dependant constant.

Description

~6~723 A NOTCH FILTER FOR AN INTERPOLATOR/DECIMATOR
.
F I LTER STRUCTURE
Technical Field The present invention concerns improvements in or relatin~ to interpolator and decimator filter structures of the type incorporating recursive digital filters. The invention also concerns the design o~ notch filters ~or use in such structures.
Background Art Novel forms of interpolator/decimator filter structure have been described recently in the literature.
In particular, reference is made to the two articles:-"Digital Signal Processing Schemes for efficient Interpolation and Decimation" by R.A.Valanzuala and A.G.
Constantinidss, reported in IEE. Proc. Vol.130 No.6 pp.225-234 (Dec~1983); and, "Efficient Sampling Rate alteration using Recurs~ve tIIR) Digital Filters" by R~Ansari and B.Lui, reported in IEEE
Trans Acoust., Speech Sig Proc. Vol.ASSP-31 No.6 pp.l366 1373 (Dec.1983).
The structures described are capable of interpolating or decimating between two sampling rates related by a factor N where N is an integer. It proves most advantageous when M is 2, and it is this case that is considered urther. It should be noted that Interpolation : . : : - , ~:
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and Decimation between sampling rates differing by a factor of a power of two is easily implemented by a cascade o similar filters, each changing the frequency hy a factor of two.
Important properties of these interpolator and decimator filter structures are as follows:
i) The repeated use of simple All-Pass-Networks (APNsj to build up the ~ilter structure, facilitating implemention, ii) Most of the signal processing is performed at the lower of the two sampling frequencies, reducing the number of multiplications and additions required per unit time to achieve a given performance requirement compared to alternative filter structures, lS iii) Good noise performance~
iv) Low sensitivity of filter performance to coefficient value, resulting in short wordlength co-efficients, v) Reduced number of co-efficients required to implement a filter with given performance compared to alternative conventional filter structures.
However, there are some limitations to the performance of the filter structures as currentl~
described in the literature. In particular such filter structures are incapable of providing more than 3dB of attenuation at half of the lower sampling frequencies.

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~26~t~3 There are many applications where there is a requiremen~
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Disclosure of the Invention The present invention is intended as a solution to the problem of providing in excess of 3dB attenuation at one half of the lower sampling frequency. Interpolator and Decimator filter structures are provided wherein this problem is overcome by introducing a notch filter. This filter, which operates at the lower of the two sampling frequenc;es, introduces a transmission zero at some frequency slightly less than half of the lower sampling erequency and considerably more than 3dB attenuation at half the lower sampling frequency.
In accordance with the invention there is provided an interpolator-or-decimator filter structure, operable between a lower and a higher sampling rate, comprising:
an lnterpolating or decimating switched branched network, including one or more all-pass-network filters; and, connected in series therewith, a notch filter, this filter having a transmission xero at a frequency displaced from a frequency o one half of the lower sampling rate, and being comprised of a plurality of all-pass-network filters;
each all pass network filter including a delay element and at least one coefficient multiplier and having as . . - . ~

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: . . . . : -$'~3 characteristic a transform function X(Z) of the form:
X(Z) = [z-l _ K ]/ [1 - KZ-l]
where z 1 is the unit delay operator and K the multiplier coefficient.
In accord with the invention there is also provided a notch filter for use in the interpolator/decimator filter structure as set forth above, the notch filter comprising:-A pair of all-pass-network filters connected in-line between an input node and an output node, the input to the first one of the pair of filters being connected to the output node, and a tapped output of the second one of these filters being connected to the input node, and wherein each all-pass-network filter is defined by a throughput transform function X(Z):-X(Z) = [Z-l _ KJ/ [1 - KZ-l], and wherein the second of these filters has an intermediate transform function Y(Z):-Y(Z) = ~ Z-l/[1 - KZ-l]; where ~ is a structure constant~
8rief Introduction of the Drawlnys In the drawings accompanying this specification:-Figures 1 and 2 are circuit diagrams of alternative all-pass-natwork filters, each of known configuration, each suitable for application to the construction of , ,, . : .

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. interpolator/decimator ~ilter structures;
Figure 3 is a block circuit diagram of a notch filter, constructed in accordance with this invention, and using a combination of filters of the type shown in either S one of the precedlng figures;
Figures 4 and 5 are block circuit diagrams of a decimator filter structure and an interpolator filter structure, respectively, each incorporating the notch filter shown in figure 3 above; and, Figures 6 and 7 are graphs of gain-frequency response for an interpolator/decimator structure and a notch filter, respectively.
_scription of Preferred Embodiments Embodiments of this invention will now be described, by way of example only, and with particular reference to the drawings aforesaid.
An all-pass-network filter A of known configuration is shown in figure 1. This filter has two branches 1 and

3 each providin~ a conncction between a common input terminal 5 and an output node 7. One branch, branch 1, inclsldes a branch node 9 and a delay element 11. The other branch, branch 3, includes a branch node 13 and a coefficient multiplier lS. Output O/P is taken ~rom the output node 7 and an intermediate output-T is taken from the signal path between this output node 7 and the delay .. . .. .

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'7 element 11. Cross-connections.17 and 19 are provided between the output of the delay element 11 and the branch node 13 preceding the multiplier 15, and between the output of the multiplier 15 and the branch node 9 preceding the delay element 11, respectively.
An alternative to the above all-pass-network is shown in figure 2. This nietwork filter B comprises an input node 21, a delay element 23 and an output node 25, connected in-line. A first coefficient multiplier 27 is connected across the delay element 23 and this provides a feed forward path between the input to this element 23 and the output node 25. A second coefficient multiplier 29 is also connected across the delay element 23 and thiis provides a feedback path between the output of the delay element 23 and the input node 21. Output O/P is taken from the output node 25 and an intermediate output-T is taken from the signal path between the delay element 23 and the outpuk node 25.
Either one of the ~ilters, filter A or filter B, may be used in the construction of the notch filter and the interpolator/decimator ~ilter structures shown in the following figures. For a particular application, the choice of all~pass-network filter will depend on the overall filter noise performance re~uired, the signal growth tolerances at internal nodes and upon other , ~ , .: .

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The throughput and intermediate transform functions X~Z) and Y(Z) of both the filters, filter A and filter B, may be expressed as follows:-X(Z) = [z-l _ K ]/ [1 - KZ~l]; and, Y(Z) = OL Z~ [1 - KZ-l ]
where the term ~ is a structure constant, dependant thus on the particular configuration, and the term K is the multiplier coefficient.
The notch filter C shown in figure 3 includes two like all-pass-network filters 31, 33 each constructed as described above. These two filters 31 and 33 are connected in-line between an input node 35 and an output node 37. A by-pass feed forward connection 39 is made between the input to the first one 31 of these two filters 31 and 33 and the output node 37. A negative feedback path 41 is made from the intermediate output T of the second one 33 of these two filters 31 and 33 to the input node 35. This path 41 includes a coeficient multiplier 43. In the fi~ure, tne labels Kl, K2~ K3 denote multiplier coefficients for the two filters 31 and 33 and the multiplier 43. Thes0 coe~ficients Kl, K2, K3 determine the frequency response, and these can be optimised to meet a ~iven requirement.
This notch fil~er C is incorporated in the decimator : ... ~ .
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~i26~3 structure shown in figure 4. The first stage of this structure comprises a sampling switch 45 which alternates between two branches 47 and 49 of the structure, each of which terminates at an output node 51. One branch 47 of this structure comprises a pair of like all-pass-network filters 53 and 55. Each has one of the forms described previously. The other branch 49 of the structure includes another like all-pass-network filter s7. This branch of the structure may also include a delay element 59. This stage of the structure performs the decimator function as described in the references quoted previously. A filter designed for a specific requirement is shown. However, further all-pass-networks may be introduced in each of the two branches 47 and 49 and the lS values of multiplier coeficients preset to meet alternative requirements. This first stage j~ followed by a divide-by-two multiplier 61, the notch ~ilter C and one further divide-by-two multiplier 63. The latter pair of divide-by-two multiplier 61 and 63 are employed to reduce the signal amplitude to an acceptable level. In the figure, labels K4 to K8 denote the multiplier coefficients of the first divide-by-two multiplier 61, the three all-pass-network ilters 53, SS and 57, and the second divide-by-two multiplier 63, respectively.
Figure 6 shows a typical attenuation requirement or ~ .: :

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decimator or interpolator, one that operates between a 16Hz sampling rate and an 8Hz sampling rate.
This may be compared with the response of the decimator also shown. The values of the coefficients to K8, used in structure on which this response is based, are tabulated in the table below:-TABL~ 1 -10 Coefficient Decimal Equiv. Fractional Binary Value _alue Value Kl O.S 1/2 0.100000 K2 0.984375 63/64 0.111111 K3 (A) 10.75 10~ 1010.11 K3 (B) 0.16796875 43/256 0.00101011 K4 0.5 1/2 0.100000 K5 0.21875 7/32 0.001110 K6 0.875 7/8 0.111000 K7 0.59375 19/32 0.100110 K8 0-5 1/2 0.100000 It can be seen from the table that only the coefficient K3, the coeficient of the feedback - multiplier 43 of the notch filter C, need di~fer for the alternative filter APN implementations ~ and B. The gain-frequency response of the notch flltsr C is shown in figure 7. This has a notch at a frequency of 3.8kHz.

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The notch filter C can also be used as part of an interpolator filter structure. This is shown in figure 5 where the notch filter C is used as the input stage to an interpolating sub-filter E. This latter comprises three all-pass-network filters 65, 67 and 69. These are arranged in two branches 71 and 73 extending between a common input junction 75 and a sampling switch 77. This last stage of the structure is similar to that described in the articles quoted. A delay element 79 may be included in the lower branch 73. The notch filter C and the interpolating sub-filter E are linked by a divide-by-two coe~ficient multiplier 81. In this figure the labels K4 to K7 denote the multiplier coefficients of the linking multiplier 81 and the three ilters 65, 67 and 69. iO
Typical values of the coefficients Kl to K7 are as tabulated above.

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Claims (3)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A notch filter, for use in an interpolator or decimator filter structure, this notch filter comprising:-a pair of all-pass-network filters connected in-line between an input node and an output node, the input to the first one of the pair of filters being connected to the output node, and a tapped output of the second one of these filters being connected to the input node, and wherein each all-pass-network filter is defined by a throughput transform function X(Z):-X(Z) = [Z-1 - K]/ [1 - KZ-1], and wherein the second of these filters has an intermediate transform function Y(Z):-Y(Z) = .alpha. Z-1/ [1 - KZ-1]; where .alpha. is a structure constant.

2. A notch filter, as claimed in claim 1, wherein each all-pass-network filter comprises a delay element and a coefficient multiplier, each in respective branches of the network filter and, disposed between a common input terminal and an output node; branch nodes also being located between the input terminal and the delay element and multiplier, these being cross-coupled to the outputs of the multiplier and delay element, respectively.

3. A notch filter, as claimed in claim 1, wherein each all-pass-network filter comprises a delay element in-line between an input node and an output node, there being a feedback connection between the output of the delay element and the input node, and, a feed forward connection between the input to the delay element and the output node, each connection including a lîke coefficient multiplier.