JPH02113712A - Digital filter - Google Patents

Abstract

PURPOSE:To obtain a digital filter with simple calculation and simple constitution by obtaining a transfer function from an analog transfer function directly through the use of an approximated complete integration device. CONSTITUTION:An input digital signal and a negative feedback digital signal from a complete integration device 1c are added by an adder 1e to output a deviation signal between the input digital signal and the negative feedback digital signal. Then A coefficient (k) is multiplied with a deviation output digital signal from the adder 1e by a multiplier 1d, the output digital signal of the multiplier 1d is inputted to the complete integration device 1c, and the output of the complete integration device 1c is extracted as the output of the digital filter. Thus, a proper approximation is applied so as to simplify the transfer function of the filter in this way. Then the digital filter realized with simple calculation and constitution is obtained.

Description

[Detailed description of the invention] Industrial field of application Conventional technology (Fig. 14) Means for solving the problem to be solved by the invention (Fig. 1) Effect (Fig. 1) Example 1 Explanation of the embodiment (Figures 2 and 3) Explanation of the second embodiment (Figures 4 and 5) Explanation of the third embodiment (Figures 6 and 7) Explanation of the fourth embodiment (Figures 8 and 9) Description of the fifth embodiment (Figure 10.11) Description of the sixth embodiment (Figure 12.13) Effects of the invention [Summary Digital filter (including delay equalizer) for performing codigital signal processing With regard to this, appropriate approximations are made to simplify the transfer function of the filter, and digital filters (including delay equalizers) can be created with simple calculations and a simple configuration.
The purpose is to realize a perfect integrator that has an adder that adds digital signals and a unit delay element that delays the digital signal by a unit, and a digital signal that has been multiplied by a required coefficient to the perfect integrator. It is configured to include a multiplier that outputs an output, and an adder that adds the input digital signal and the negative feedback digital signal from the perfect integrator and outputs a deviation signal between the input digital signal and the negative feedback digital signal to the multiplier. do.

[Industrial Application Field] The present invention relates to a digital filter (including a delay equalizer) for performing digital signal processing.

In recent years, with the demand for digital signal processing, digital filters have been required to be faster and smaller, and for this purpose, it has been proposed to use, for example, a cyclic digital filter (also referred to as an IIR digital filter).

[Prior Art] FIG. 14 is a block diagram of a conventional IIR digital filter, and in this FIG. 14, 14a is a multiplier;
14b is an adder, 14-c is a unit delay element, and this I
In the IR digital filter, an input digital signal is sequentially delayed by a unit delay element], 4c, multiplied by a required coefficient by a multiplier 14a, and all the signals are added together by an adder 14, and the output of the adder is sent by a unit delay element 14c. The product is sequentially delayed and multiplied by a required coefficient by the multiplier 14a, and then the resultant is sent to the adder 1.
4 is used to add all the numbers.

Conventionally, a bilinear Z-transform method, an impulse invariance method, or the like is used to obtain filter coefficients (multiplier coefficients) from a filter transfer function to realize an IIR digital filter.

(1) [Problem to be solved by the invention] However, in the conventional digital filter design method,
Filter coefficients (multiplier coefficients) from the filter transfer function
In order to find , quite complex calculations are required, which is a bottleneck in digital filter design.

The present invention was devised under these circumstances, and is a digital filter (delay equalizer) that can be realized with simple calculations and a simple configuration by applying appropriate approximations to simplify the transfer function of five filters. ).

[Means to solve the problem] FIG. 1 is a block diagram of the principle of the present invention.

In FIG. 1, 1a is an adder that adds digital signals, 1b is a unit delay element that delays the digital signal by a unit, and these adder 1a and unit delay element 1b
A complete integrator 1c is constructed.

1d is a multiplier that outputs a digital signal multiplied by a required coefficient k to perfect integrator 1c, and 1e is a multiplier that adds the input digital signal and the negative feedback digital signal from perfect integrator 3-c and calculates the sum of these signals. This is an adder that outputs a deviation signal between the input digital signal and the negative feedback digital signal to the multiplier 1d.

[Function] With this configuration, the input digital signal and the negative feedback digital signal from the perfect integrator 1c are added by the adder 1e, and a deviation signal between these input digital signals and the negative feedback digital signal is output. Further, the deviation output digital signal of this adder 1e is multiplied by a certain coefficient k by a multiplier 1cl, and the output digital signal of this multiplier 1d is further inputted to a perfect integrator IC.

Then, for example, the output of the perfect integrator 1G is taken out as the output of the digital filter. Note that the output of the digital filter (including the delay equalizer) can also be taken out from other parts depending on the type of filter (including the delay equalizer) desired.

[Example] Hereinafter, the present invention will be described in detail with reference to the drawings.

(,) Description of the first embodiment Fig. 2 is a block diagram showing the first embodiment of the present invention.The embodiment shown in Fig. 2 is an application of the present digital filter to a first-order low-pass filter. In FIG. 2, 2a is an adder that adds digital signals, and 2b is a D flip-flop as a unit delay element that delays the digital signal by a unit.These adder 2a and D flip-flop 2b form a perfect integrator 2c. is configured.

2d is a multiplier that outputs a digital signal multiplied by a required coefficient k to the perfect integrator 2c, and 2e is a multiplier that adds the input digital signal and the negative feedback digital signal from the perfect integrator 2c to calculate these input digital signals. This is an adder that outputs a deviation signal between the signal and the negative feedback digital signal to the multiplier 2d.

Hereinafter, a circuit portion consisting of a combination of perfect integrators, nine multipliers, and an adder as described above will be referred to as a basic circuit unit.

Next, the reason why the first-order low-pass filter is configured with such a circuit configuration will be explained.

First, the transfer function Hi(s
T), Hi (sT)=1/ (1-exp(-sT)) month/
(sT)...(1), which can be approximated to a complete integral.

Note that T is a delay time, which corresponds to the clock cycle of the input to the D flip-flop.

Therefore, a block diagram of the circuit shown in FIG. 2 is shown in FIG. 3. Then, when the transfer function I((sT) of the one shown in FIG. 3 is determined, the following (
This is because, as shown in equation 2), it is the same as the transfer function of the first-order low-pass filter.

H(sT)=/(k+(sT)) (2) In this case, the cutoff frequency is the delay amount of the unit delay element (
(sampling period) and multiplier coefficient (gain).

With the above configuration, the input digital signal and perfect integrator 2
The adder 2e adds the feedback digital signals from the adder 1e and outputs a deviation signal between these input digital signals and the negative feedback digital signal. Multiply by multiplier 2d,
Further, by inputting the output digital signal of this multiplier 2d to a perfect integrator 2c and taking out the output of the perfect integrator 2C as an output of a digital filter, it can be taken out as an output of a first-order low-pass filter.

In this way, appropriate approximations are made to simplify the transfer function of the filter, and a first-order low-pass filter can be realized with simple calculations and a simple configuration.

(b) Description of Second Embodiment FIG. 4 is a block diagram showing a second embodiment of the present invention.The embodiment shown in FIG. 4 is an application of the present digital filter to a bypass filter. In Figure 4, 4
a is an adder, 4b is a unit delay element (this unit delay element 4
For example, a D flip-flop is used as b),
4c is a perfect integrator, 4d is a multiplier, and 4e is an adder. The circuit configuration in this case is also the same as the basic circuit unit described above, but the difference in this circuit from that shown in FIG. 2 is as follows.
In this case, the output of the adder 4e is taken out as the output of the digital filter.

Next, the reason why the bypass filter is configured with such a circuit configuration will be explained.

The block diagram of the circuit shown in FIG.
The transfer function H(
sT) is the same as the transfer function of the bypass filter, as shown in equation (3) below.

H(sT)=sT/(k+(sT)) (3) With the above-described configuration, the input digital signal and the negative feedback digital signal from the perfect integrator 4c are added by the adder 4e,
A deviation signal between these input digital signals and a negative feedback digital signal is output, and the deviation output digital signal of this adder 4e is multiplied by a coefficient k in a multiplier 2d, and the output digital signal of this multiplier 4d is perfect integrator 4c
If the output of the adder 4e is taken out as the output of the digital filter, it can be taken out as the output of the bypass filter.

In this case as well, by applying appropriate approximation to simplify the transfer function of the filter, a bypass filter can be realized with simple calculations and a simple configuration.

(C) Description of the third embodiment Fig. 6 is a block diagram showing the third embodiment of the present invention.The embodiment shown in Fig. 6 is an application of the present digital filter to a band pass filter. In Figure 6,
6a is an adder, 6b is a unit delay element (for example, a D flip-flop is used as this unit delay element 6b)
, 6C is a perfect integrator, 6d is a multiplier, 6e is an adder,
The configuration of these elements is a basic circuit unit configuration, which is the same configuration as the above-mentioned primary bypass filter.

Further, 6f is an adder, 6g is a unit delay before -F (for example, a D flip-flop is used as this unit delay element 6g), 6h is a perfect integrator, 61 is a multiplier, and 6j is an adder. The structure of the element is basically the same as that of the above-mentioned low-pass filter.

That is, this filter has a structure in which a bypass filter section and a low-pass filter section form a double loop.

In this circuit, the output of the perfect integrator 6c is taken out as the output of the digital filter.

Next, the reason why a bandpass filter is configured with this circuit configuration will be explained.

The block diagram of the circuit shown in FIG.
The transfer function H(
sT) is the same as the transfer function of the bandpass filter, as shown in equation (4) below.

H(sT) = to □sT/((sT)2+, (sT)+
, 2) and (4) where kl is the gain of the multiplier 6d,
k2 is the gain of the multiplier 61.

With the above configuration, if the input digital signal is passed through the bypass filter section and the low-pass filter section and the output of the perfect integrator 6C is taken out as the output of the digital filter, it can be taken out as the output of the band-pass filter.

In this case as well, by applying appropriate approximation to simplify the transfer function of the filter, a bandpass filter can be realized with simple calculations and a simple configuration.

(d) Explanation of the fourth embodiment Fig. 8 is a block diagram showing the fourth embodiment of the present invention. The embodiment shown in Fig. 8 is an example in which five digital filters are applied to a second-order pi-cut low-pass filter. So, this 8th
In the figure, 8a is an adder, 8b is a D flip-flop as a unit delay element, 8c is a perfect integrator, 8d is a multiplier, and 8e is an adder, and the configuration of these elements is a basic circuit unit configuration. , and 8f is an adder, 8g
is a D flip-flop as a unit delay element, 8h is a perfect integrator, 81 is a multiplier, and 8j is an adder.

In this circuit, the output of the adder 8a of the first-stage perfect integrator 8C is input to the second-stage multiplier 8j, and the output of the second-stage perfect integrator 4h is negatively fed back to the adder 4j. At the same time, the output of the second stage perfect integrator 4h is taken out as the output of the digital filter.

Therefore, the element configuration between the adder 8f, D flip-flop 8g + perfect integrator 8h, multiplier 8i, and adder 85 is such that the first stage basic circuit unit is inserted between the adder 8j and the multiplier 81. If you think about it, it basically has a basic circuit unit configuration.

Next, the reason why a second-order pi-cut low-pass filter is configured with this circuit configuration will be explained.

In other words, the block diagram of the circuit shown in FIG. 8 is as shown in Part 9, and when the transfer function H(sT) of the circuit shown in FIG. 9 is determined, as shown in the following equation (5), This is because the transfer function is the same as that of the second-order low-pass filter.

H(sT)2, 2/((sT)2+, (sT)
+ to 1 to 2) = (5) Note that k is the gain of the multiplier 8d, and k2 is the gain of the multiplier 8j.

1] With the above configuration, the output of the adder 8a of the first stage perfect integrator 8C is input to the second stage multiplier 81, and the output of the second stage perfect integrator 4h is negatively fed back to the adder 4j. At the same time, if the output of the second-stage perfect integrator 4h is taken out as the output of the digital filter, it can be taken out as the output of the second-order pi-cut low-pass filter.

In this case as well, appropriate approximations are made to simplify the transfer function of the filter, and 2
It is possible to realize the following pi-cut low-pass filter.

(e) Description of the fifth embodiment FIG. 10 is a block diagram showing the fifth embodiment of the present invention. The embodiment shown in FIG.
This is applied to a second-order delay equalizer, and in this Figure 1-0, 10a is an adder, and 10b is D as a unit delay element.
A flip-flop, ]Oc is a perfect integrator, 10d is a multiplier, and 10e is an adder, and this configuration is also a basic circuit unit configuration.

Also, 1. Of is an adder, and this adder 1. Of is an adder], receives the output of Oe as a plus, and is a perfect integrator 1. The output of Oc is received as a negative signal, and the differential output between both signals is taken out as the output of this first-order delay equalizer.

Next, the reason why the first-order delay equalizer is configured with this circuit configuration will be explained.

That is, the block diagram of the circuit shown in FIG. 10 becomes as shown in FIG. 11, and when the transfer function H (sT) of the circuit shown in FIG. 11 is determined, as shown in the following equation (6), This is because it is the same as the transfer function of the first-order delay equalizer.6H(sT) = [1/key + (k/5T))
Co[(k/sT)/(1+(k/5T))]...(6
) With the above-described configuration, the adder 10f receives the output of the adder]Oe as a plus, and receives the output of the perfect integral = 15 unit 10c as a minus, and extracts the difference output between the two signals from the adder 10f. This can be taken out as the output of the first-order delay equalizer.

In this case, appropriate approximations are made to simplify the transfer function of the filter, and with simple calculations and a simple configuration, 1
It is possible to realize a second-order delay equalizer.

(f) Description of Sixth Embodiment FIG. 12 is a block diagram showing a sixth embodiment of the present invention.
This is applied to a second-order delay equalizer, and in FIG. 12, 12a is an adder, 12b is a D flip-flop as a unit delay element, 12c is a perfect integrator, 12d is a multiplier, ], 2e is an adder. This configuration is still a basic circuit unit configuration.

In addition, 1.2f is an adder, 12g is a D flip-flop as a unit delay element, 12h is a perfect integrator, and 12i
is a multiplier, and 12j is an adder.

The output of the adder 12a of the first-stage perfect integrator 12c is input to the second-stage multiplier 12j, and the output of the second-stage perfect integrator ]-2h is negatively fed back to the adder 12j.

Therefore, the adder 11f and the D flip-flop 12g
, perfect integrator 12h2 multiplier 121. The element configuration between the adder 12j is also such that the element configuration between the adder 12j and the multiplier 12i is
If you consider that the basic circuit unit of the first stage is inserted,
After all, it basically has a basic circuit unit configuration.

Furthermore, 12 is a multiplier, and 12Ω is an adder, and this adder 12Q receives the output of the multiplier 12 as a plus, and receives the output of the adder 12a of the perfect integrator 12c as a minus, and calculates the difference between the two signals. The output is taken out as the output of this second-order delay equalizer.

Next, the reason why the second-order delay equalizer is configured with this circuit configuration will be explained.

That is, the block diagram of the circuit shown in FIG. 12 becomes as shown in FIG. 13, and when the transfer function H (sT) of the circuit shown in FIG. 13 is determined, as shown in the following equation (7), This is because the transfer function is the same as that of the second-order delay equalizer.

) - ((sT) = 3 [(sT)" ÷ (k3 - (k1/to, ))
To sT+, k2] ÷ ((sT)2+ to 1sT+,
)...(7) Note that kl is the gain of the multiplier 12d, and k2 is the gain of the multiplier 12.
The gain of i and k2 are the gains of the multiplier 12.

With the above configuration, the output of the adder 1.2a of the first stage perfect integrator 12c is input to the second stage multiplier 12i, and
While the output of the complete integrator 12h in the stage is fed back negatively to the adder 12j, the adder 12Q receives the output to the multiplier 12 as a positive value, and also receives the output from the adder 12 of the perfect integrator 12c.
The output from the second-order delay equalizer can be obtained by receiving the negative output from a and taking out the difference output between the two signals from the adder 12Q.

In this case as well, appropriate approximations are made to simplify the transfer function of the filter, and 2
It is possible to realize a second-order delay equalizer.

[Effects of the Invention] As detailed above, according to the digital filter of the present invention, a digital filter (including a delay equalizer) can be constructed directly from an analog transfer function by using an approximate perfect integrator. This has the advantage that a digital filter (including a delay equalizer) can be realized with simple calculations and a simple configuration.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram showing a first embodiment of the invention, Fig. 3 is a block diagram of what is shown in Fig. 2, and Fig. 4 is a second embodiment of the invention. A block diagram showing an example; FIG. 5 is a block diagram of the one shown in FIG. 4; FIG. 6 is a block diagram showing a third embodiment of the present invention; FIG. 7 is a block diagram of the one shown in FIG. 6; 9 is a block diagram of the fourth embodiment of the present invention, FIG. 9 is a block diagram of what is shown in FIG. 8, FIG. 10 is a block diagram of the fifth embodiment of the present invention, and FIG. 11 is a block diagram of the one shown in FIG. FIG. 12 is a block diagram of the sixth embodiment of the present invention; FIG. 13 is a block diagram of the device shown in FIG. 12; FIG. 14 is a block diagram of a conventional example. In the figure, 1a is an adder, 1b is a unit delay element, 1c is a perfect integrator, 1d is a multiplier, 1e is an adder, 2a is an adder, 2b is a D flip-flop (unit delay element), and 2c is a perfect integrator. 2d is a multiplier, 2e is an adder. 4a is an adder, 4b is a unit delay element, 4c is a perfect integrator, 4d is a multiplier, 4e is an adder, 6a is an adder, 6b is a unit delay element, 6cj is a perfect integrator, 6d is a multiplier, 6e , 6f is an adder, 6g is a unit delay element, and 6h is a perfect integrator. 6j is a multiplier, 6J is an adder, 8a is an adder, 8b is a D flip-flop (unit delay element), 8c is a perfect integrator, 8d is a multiplier, 8e and 8f are adders, 8g is a D flip-flop ( 8h is a perfect integrator, 8j is a multiplier, 8j is an adder, 1, Oa is an adder, 10b is a D flip-flop (unit delay element) 1, O
c is a perfect integrator, 1, Od is a multiplier, ], Oe, 10f is an adder, 1, 2 a is an adder, 1, 2 b is a D flip-flop (unit delay element) 1,
2c is a perfect integrator, 12d is a multiplier, 12e and 12f are adders, 12g is a D flip-flop, 12h is a perfect integrator, 12i is a multiplier, 12j is an adder, 12 is a multiplier, 12Ω is an adder It is. (Unit delay element) 11371.2 (11) 6L coming? Figure 14

Claims (1)

[Claims] A perfect integrator (1c) having an adder (1a) that adds digital signals and a unit delay element (1b) that delays the digital signal by a unit; A multiplier (1d) that outputs a digital signal multiplied by a coefficient, and a multiplier (1d) that adds the input digital signal and the negative feedback digital signal from the perfect integrator (1c) to obtain the input digital signal and the negative feedback digital signal. an adder (1) that outputs the deviation signal of
e) A digital filter comprising: