SU1334366A1 - Low-frequency digital filter - Google Patents

Abstract

The invention relates to radio, technology. The purpose of the invention is to simplify the technical implementation by using multipliers with multipliers less than one and simplifying adjusting the cutoff frequency, the filter contains multipliers 1 and 2, adders 3-7 and delay elements 8 and 9. The goal is achieved by introducing adder 5 and multiplier 1, with which The addition of the inverted new samples of the input signal with the samples stored in the element — Delay 8 — is carried out, and the result of this addition is weighed. 1 il. (L with Log SoMOff 00 SlaE about ;: Co od 0

Description

The invention relates to radio engineering and can be used to process signals defined by a digital code.

 The purpose of the invention is to simplify the technical implementation by using multipliers with multipliers less than one and simplifying adjustment of the cutoff frequency.

The drawing shows an electrical block diagram of a digital low-pass filter.

Digital lowpass filter contains the second and first multipliers 1 and 2, the third, fourth, fifth, second and first adders 3-7, the first and second elements 8 and 9 of the delay

Digital lowpass filter works as follows.

The input signal samples arrive at the first input of the first adder 5, from the output of which they are fed to the input of the second multiplier 1. Then the input signal samples and the samples weighted in the second multiplier 1 are fed to the inputs of the first adder 7. The counts summed up in the first adder 7 are received to the input of the second adder 6. The counts summed up and reweighted in the first mixer 2 are fed to the inputs of the third adder 3. The value of the counts of the signal at the output of the third adder 3 is recorded in the first delay element 8. These samples are weighted in the second multiplier 1 and from the output of the first adder 7 are fed to the input of the second adder 6, from the output of which they go to the first multiplier 2. The newly weighted samples in the first multiplier 2 and the counts weighted in the second multiplier 1 are skewed in the third adder 3

In the fourth adder 4, the counts are added, received 1-1x from the output of the third adder 3, with doubled the value of the signal counts stored in the first delay element 8. The result of the addition is recorded in the second delay element 9. From the output of the second adder. 6, the inverted signal samples stored in the second delay element 9 are fed to the input of the first multiplier 2, where they are multiplied by the corresponding multiplication factor. Then, the samples from the output of the third adder 3 are fed to the input of the fourth adder 4, where they are added to the signal samples stored in the second element 9.

delays. The result of the addition is recorded in the first delay element 8, and the signal samples stored therein are overwritten in the second

delay element 9.

To calculate the next sample of the output signal, it is necessary to store the signal samples recorded in the first and second delay elements 8 and 9.

The following operations are performed with the newly input samples of the input signal. In the fifth adder 5, the inverted new samples of the input signal are added with the samples stored in the first delay element 8. The result of the addition, weighted in the second multiplier 1, is added to the new samples of the input signal in the first adder 7.

Signals from the output of the first

adder 7 is fed to the second adder 6, where it is added to the inverted counts recorded in the BtopoM delay element 9.

The result of the addition is weighted by the TC in the first multiplier 2 and enters: the third adder 3, which produces its addition with the samples of the signal coming from the output of the first

adder 7. The samples coming from the output of the third adder 3 are added in the fourth adder 4 with the samples stored in the first delay element 8 and with the samples

signal stored in the second element: 9 delay. Then, the samples of the signal stored in delay elements 8 and 9 are overwritten, and the result of the last addition is fed to the output of the digital low-pass filter.

The transfer function of a digital low-pass filter, which is a second-order low frequency link, is

H (Z)

(1-B) (H-A) (1 + 2Z

+ Z-M

1-B (1 + A) Z- + AZ, where A and B are the multiplication factors of the first and second multipliers 2 and 1, respectively. From the conditions of stability / A / / B / 1 it can be seen that the values of A and B do not exceed unity

in absolute value, which leads to a simplification of the technical implementation of multipliers.

Beli express the coefficient B through the parameters of the natural frequency of the analog low-pass filter Uo and the tuning parameter

AT

l-foV-r iTwJr

it can be seen that this coefficient does not depend on the quality factor of the filter, which allows you to simplify the adjustment of the cutoff frequency, using only the coefficient B for this

Formula Ula Invention

A digital lowpass filter containing a series-connected first adder, the first input of which is the input of the low-pass filter, the second adder, the first multiplier, the third adder, the second

Editor I. Casard

Compiled by E. Borisov Tehred I. Popovich

Order 3979/56

Circulation 901 Subscription

VNIIPI USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5

Production and printing company, Uzhgorod, st. Design, 4.

five

0

five

the input of which is connected to the output of the first adder, and the fourth adder, the output of which is an output of a low-pass filter, serially connected to the first delay element, the input of which is connected to the output of the third adder, and the second delay element, co-connected to the second inputs of the second and A fourth adder, characterized in that, in order to simplify the technical implementation by using multipliers with multiplication factors less than unity and simplifying adjustment of the cutoff frequency, additional Consequently, the fifth adder, the first input of which is combined with the first input of the first adder, and the second input is connected to the output of the first delay element, combined with the third and fourth inputs of the fourth adder, and the second multiplier, the output of which is connected to the second input of the first adder.

Proofreader A.T. sko

Claims (1)

Claim A digital low-pass filter containing a series-connected first adder, the first input of which is the input of the low-pass filter, the second adder, the first multiplier, the third adder, the second input of which is connected to the output of the first adder, and the fourth adder, the output of which is the output of the low-pass filter connected in series to the first delay element, the input of which is connected to the output of the third adder, and the second delay element, the output of which is connected to the second inputs of the second and fourth sums torus, characterized in that, in order to simplify the technical implementation by using multipliers 15 with multiplication factors less than unity and simplify the adjustment of the cutoff frequency, a fifth adder is added in series, the first input of which is shared with the first input of the first adder, and the second input is connected to the output of the first delay element combined with the third and fourth inputs of the fourth adder, and a second multiplier, the output of which is connected to the second input of the first adder.