RU1798891C - Digital recursive filter - Google Patents

Abstract

Usage: in automation and computer technology for spectral analysis with the representation of the input signal in the format of linear delta modulation. SUMMARY OF THE INVENTION: The device comprises a first multiplier and a first adder connected in series. The input of the first multiplier is combined with the input of the second delay unit, the output of which is connected to the input of the second multiplier, and the output of the first adder is connected to the first input of the algebraic adder and the input of the third delay unit. The output of the third delay block is connected to the second input of the algebraic adder, the output of which is connected to the multiplier and the fourth delay block connected in series. The outputs of the first delay unit, the second multiplier and the fourth delay unit are connected to the corresponding inputs of the second adder, the output of which is connected to the input of the first delay unit and the first input of the first adder. 1 ill.

Description

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WITH

The invention relates to the field of automation and computer engineering and can be used in spectral analysis with the representation of the input signal in linear delta modulation (LDM) format.

The purpose of the invention is to improve the performance when filtering linear delta modulated signals.

The drawing shows a structural electrical circuit of the filter.

The digital recursive filter contains the input of filter 1, the first, second and third multipliers 2, 3 and 4, the first and second adders 5 and 6, the algebraic adder 7, the first-fourth delay blocks 8-11, the first, second and third inputs 12, 13 and 14 setting filter coefficient values, filter output 15.

The input of the first multiplier 2 is combined with the input of the second delay unit 9 and is the input of the filter 1, the output of the second delay unit 9 is connected to the input of the second multiplier 3, the output of the first adder 5 is the output of the filter 15 and connected to the first input of the algebraic adder 7 and the input of the third delay unit 10, the output of which is connected to the second input of the algebraic adder 7, the output of which is connected to the input of the multiplier 4, the output of which is connected to the input of the fourth delay unit 11, the output of which and the outputs of the first delay unit 8 and second th multiplier 3 are connected to corresponding inputs of the second adder 6 whose output is connected to the input of the first delay unit 8 and the first input of the first adder 5, the second input of which Con 00 00 4 U

Yu

than to the output of the first multiplier 2, the second inputs of the first, second and third multipliers 2, 3, 4 are, respectively, the first, second and third inputs 12, 13 and 14 of the filter coefficient values.

Digital recursive filter works as follows.

The digital recursive filter operation algorithm is as follows.

The difference equation of the first order, in which the input, output signals and coefficients of the difference equation are presented in PCM format, has the form:

Yn a Yn-1 + L0Xn + bixn-l,

(1)

where {xn}, {yr},. n 0 - input and output PCM sequences; and g, bo, bi are the coefficients of the difference equation y0 0,

Replace the input and output signals with sequences characteristic of the DM format

(2)

where yn yn - yn-i; ei (x) Ј {-1,1} - input LDM - sequence. In view of (2), equation (1) takes the form

Pack 5 U1 + b0 Ј eiM + bin21fei (x) - ..

i - 1

i 1

I 1

 Whence we have yn bo e (x) n

(x).

n - 1

+ X () eiw + aivyi. eleven.

Consider the expression on the right-hand side of (3). Multiplying the single-bit values e fi by a constant coefficient b0 is equivalent to multiplying the sign of the value of bo by ± 1 and degenerates into an operation on the signed bit bo. The second term is the continuous accumulation of values (b0 + b1) eC + aivyi, the first part of which is equivalent to the considered one, and the second is the multiplication of the values of the first difference of the output signal {Vyi} by a constant coefficient ai, and the sequence {vyi} has a resolution much lower than the output sequence {yi}.

The above algorithm is implemented as follows.

-. The filter starts with zeroing all delay units (reset and synchronization circuits are not shown in the drawing). AT

As a result of this, a filter value 0 is set at the output 13 of the filter.

The input 1 of the filter receives the delta-code sequence of the input signal: 5 {B (x) n}, n 0, B (x) n € {0,1), B (x) n (1 + eMri) / 2 .. s sampling rate T. characteristic of this view. The output is clever,

.0 inhabitants .2 with ErxV A sequence of values {eHi b0} is generated. COOT-. corresponding to the multiplication of the sign of the coefficient bo at input 13 by the value of eHv. At the same time, the input sequence {Exxn} through a one-bit delay block 9 goes to the second multiplier 3, the output of which is from bo - bi at input 14 and the input is delayed by one. the clock cycle (equal to the period of the sampling frequency) of the sequence, the signal value {(bo + bi)} is generated in the fifth cycle. These operations are most easily performed using an EXCLUSIVE OR element.

5 Thus, in the nth step, the values of the signals e xVi (b0 + bi) and bo respectively arrive at the inputs of the second b and the first 5 adders, and the output signal generates the value of the output signal

0 unitary enterprise in PCM format, which, arriving at the inputs of the algebraic adder 7. directly and through the third delay unit 10 (with a delay of one clock cycle), forms the first difference of the output signal vyn UP - Up-1 at the output of unit 7. In the smart factor 4, the value of the first difference is 7 unit. multiplied by the coefficient ai supplied to the inputs 12, resulting in the output of the fourth delay block 11, taking into account

0 delay by one clock cycle, the signal value ai is generated.

This signal, together with the output signal from the multiplier 3, is fed to the inputs of the second adder 6, where it is summed with the previously accumulated value of the output signal of the adder 6 at the output of the first delay unit 8. G taking into account zero initial values, this leads to the formation of the value at the output of adder 6 signal

0

Vyn-1 ai + (bo + bi) e (x) n-i + 2 4

n -2

i 1

n - 1

55 + (b0 + b i) e (- g yyi a i + (b0 + b i) eMi.

i 1

The output signal of the adder 6 together with the output signal of the multiplier 2 generates at the output of the first adder 5

filter output yn in PCM format according to (3).

Thus, by introducing into the known device blocks 7, 10 and 11 with corresponding connections, the proposed device performs recursive digital filtering of the input signal with linear delta modulation while reducing the time spent in each clock cycle due to the low bit depth of the processed values ( of the input signal in xp and the first difference of the output signal 7Up), with high filtering accuracy provided by the high resolution of the PCM filter coefficients.

The sign multiplication operation in blocks 2 and 3 is performed as follows. We denote the sign bit of the coefficient bo by B0 6 {0,1}, then the multiplication result can be written in the form 2 (B ji, ФВ0) -1 -1о1- where ф is the modulo-two summation operation performed using the EXCLUSIVE OR element , Ibol. - modulus of the coefficient b0.

Claims (1)

SUMMARY OF THE INVENTION A digital recursive filter comprising in series a first multiplier whose input is the input of a digital recursive filter, and the first adder, the output of which is the output of a digital recursive filter, connected in series to the first block delays and a second adder, a second delay unit, a second and a third multiplier, characterized in that. in order to increase the speed when filtering signals with linear delta modulation, a third delay unit and an algebraic adder are connected in series, the second input of which is connected to the input of the third delay unit and the output of the first adder, and the output to the input the third multiplier, as well as the fourth delay unit, the input of which is connected to the output of the third multiplier, and the output to the second input of the second adder, the output of which is connected to the second input of the first. of the adder and the input of the first delay unit, while the input of the second delay unit is connected to the input of the first multiplier, the output, through the second multiplier, is connected to the third input of the second adder, and the inputs the coefficients of the first, second, and third multipliers are respectively the first, second, and third inputs of the coefficients of the digital recursive filter.