SU1231570A1 - Digital frequency synthesizer - Google Patents

Abstract

The invention relates to radio engineering and provides an extension of the range of synthesized frequencies. In frequency registers 6 and 7, codes of numbers A and B, respectively, are recorded, and the output frequencies of the digital synthesizer are determined. Codes are added to adder code 5. Code A from frequency register 7 through multiplexer 4 enters accumulative adder (NS) 2, consisting of memory register (SP) 8 and adder 9. Code A folds in adder 9 with the contents of SP 8. The pulse of the reference oscillator 1 is the result of the summation of C recorded in TL 8, when C + A P 2, the adder 9 overflows. The remainder after the overflow in the follower cycle is written in TL 8. The transfer signal from HC 2 is fed to the output of the digital frequency synthesizer, and also through delay element 3 passes on control input of multiplexer 4 by switching it. As a result, the A + + B code from the adder of codes 5 passes through HC 2. The next clock cycle in SPM 8 records the number Cj + A + B, and multiplexer 4 switches, skipping code A, 1 Il. i (L N9 WITH SD

Description

The invention relates to radio-technical equipment and can be used in transceiver radio equipment and measurement devices as a range generator of stable frequencies.

The aim of the invention is to expand the range of synthesized frequencies

The drawing shows a structural electrical circuit of a digital frequency synthesizer

The digital frequency synthesizer contains the basic oscillator 1, the accumulative (NS) 2, the delay element 3 5, c the optical monitor 4, the adder codes 5, the first 6 and the second 7 frequency registers. Here, the NS 2 consists of a memory register 8 and an adder 9.

Digital frequency synthesizer works as follows.

Let the first register: re 6 record the number B, and the second register 7 to write the number A, the code for the number A from the output of multiplexer 4 enters the accumulative adder 2 and adds in the adder 9 with the contents of the memory register 8 each pulse from the reference oscillator 1 writes the result of the summation - the number C - to the memory register 8. As a result, C increases until the totalizer 9 overflows. When it overflows, that is. at C- (a transfer signal appears at the output of the adder 9, and the memory register 8 on the next clock cycle will write the number Cj Cj + A - P.) By the same clock pulse, the transfer signal from the output NS 2 passes to the output of the element delay 3 and switches multiplexer 4 to the code input HC 2 from the dryer code 5 begins to receive the code number A + B and summed in it

with the number C,

pi

Therefore, the following

In the memory register 8, the number C A B will be recorded. Simultaneously, on this clock pulse, delay element 3 is triggered, and the signal from its output switches multiplexer 4j so that until the next overflow NA 2, the number A code arrives at its input.

Since after each overflow of the cumulative adder 2 during one period of the reference frequency, the code of the number A-B arrives at it, and not AJ, the equivalent capacitance HC 2 is equal to P-Bj the digital frequency synthesizer allows you to get more frequent

frequency grid. However, its maximum clock frequency is chosen from the conditions 1 / (Tks + Tr), and fj .ul /) where T- ,. - the delayed response of the delay element 3 upon the arrival of the clock pulse; T,

3

20

25

ZK)

3S

40

5Ci

-T

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p) y | (, is the delay of the signals in the combinational adder, register and multiplexer, respectively. For many | | intermittent adders.

(T t - - ms 9 e 5

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To change the output frequency of the digital frequency synthesizer, you must change the codes of the numbers A or B (or both at the same time) recorded: in the first register 6 and in the second register 7. Starting from the next after changing the HC 2 overflow codes, the output pulses will follow with a new frequency

The remainder after overflowing HC 2, recorded in memory register 8, for any B is in the range from zero to A, unlike the prototype in which the residue is in the range from B to B A, i.e. depends on B, This facilitates its conjugation with a controllable delay device, often used in a frequency synthesizer to reduce the level of the side spectral components.

As a reference oscillator 1, a quartz oscillator with a pulse shaper on the drive can be used. Memory registers current 8, the first and second registers 6 and 7 should be able to simultaneously write the incoming code and output the recorded number in the parallel code. The adder code 5 and adder 9 are binary combinational. As a delay element 3, a D-trigger can be used, triggered by a signal, its B-input is connected to the transfer output of adder 9, and the sync code is to the reference generator 1. Multiplexer 4 must switch multi-bit parallel codes of numbers coming from the outputs of the second frequency register 7 and the second adder 5,

The introduction of the delay element 3, as well as the provision of the proposed connections, by the elements, by reducing the delays of the signal in the process of accumulating sum, doubles the maximum operating frequency compared to the prototype. it

31231

is achieved by reducing the total delay of the signal in NS 2 due to the preliminary summation in the adder codes 5 numbers recorded in the first and second registers 6 e and 7. When the adder 9 overflows, the input to its input sums the contents of the first and second registers 6 and 7 with a delay for one period of the frequency of the reference generator 1,

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Claims (1)

Invention Formula A digital frequency synthesizer containing a series-connected j reference oscillator and a cumulative adder is serially connected 5704, The first frequency register and the adder codes, serially connected the second frequency register and the multiplexer, characterized in that, in order to expand the range of synthesized frequencies, between the output of the cumulative adder and the control input of the multiplexer, a delay element is introduced, the multiplexer output is connected to the code input of the cumulative adder, the output of the second frequency register is connected to the second input of the code adder, the output of which is connected to the second input of the multiplexer, and the output of the reference generator is connected to that by the input of the delay element.