SU1261111A2 - Versions of digital accumulator - Google Patents

Abstract

The invention can be used in the frequency-transforming nodes of the equipment of time and reference frequencies of measuring and computing equipment. The purpose of the invention is to increase accuracy by stabilizing the phase. The invention presents two variants of the device implementation. The device according to the first variant contains adders 1 and 3, multiplexers 2 and 10, registers 4, 5 and 6, device input 7, digital storage device input 8, device clock input 9, device output 11 and the input; 12 delays. In the device according to the second variant, a frequency divider 13 is introduced with a controlled division factor, a combination of the multiplexer function 10 and the delay element 12. Using a delay element and a multiplexer 10 or a frequency divider 13 with a controlled division factor, the phase errors at the output 11 of the accumulator become significantly less than the initial errors characteristic of the transfer pulses of the adder 3. Thus, the methodical error of the device, due to the discreteness of the accumulator, is compensated. The resulting phase stability of the output pulses is determined by the stability of the delay. 2 sec. f-ly. 2 Il. I from 7 to 13

Description

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The invention (and its variants) relates to the pulse technique and can be used in the frequency-transforming units of time and reference frequencies of the measuring and computing techniques, in the synchronization devices of the data transmission systems, mainly at the highest demands on the stability of the phase of the output pulses.

The purpose of the invention (its variants) is to increase accuracy by stabilizing the phase.

The goal is achieved in both cases by taking into account the remainder in the first register, indicating the presence of a temporal error.

FIG. 1 shows a block diagram of a digital storage device according to a first embodiment of FIG. 2 is a block diagram of a digital storage device. According to the second variant.

The digital storage device (Fig. 1) contains the first adder 1, the multi-plexer 2, the second adder 3, the first 4, the second 5 and the third 6 registers. The first input 7 of the device is connected to the first inputs of the first adder 1 and the first information inputs of the multiplexer 2, the second information inputs of which are connected to the outputs of the first adder 1, the second inputs of which are connected to the second inputs 8 of the digital storage device. The outputs of the multiplexer 2 are connected to the inputs of the second register 5, the outputs of which are connected to the first inputs of the second adder 3, the outputs of which are connected to the inputs of the first register 4, the outputs of which are connected to the second inputs of the second adder 3, the transfer output of which is connected to the input of the third register 6. Output the latter is connected to the address input of multiplexer 2, and the clock input 9 of the device is connected to the clock inputs of registers 4-6. The output of the additional multiplexer 10 is the device output 11, the address inputs of the additional multiplexer 10 are connected to the outputs of the first register 4, the information inputs of the additional multiplexer 10 are connected to the outputs of the delay element 12, the input of which is connected to the output of the third 6 register

s 10

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thirty

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five

0

five

1112

The 11-digit drive (Fig. 2) contains the first adder 1, the multiplexer 2, the second adder 3, the first 4, the second 5 and the third 6 registers. The first input 7 of the device is connected to the first inputs of the first adder 1 and the first information inputs of the multiplexer 2, the second information inputs of which are connected to the outputs of the first adder 1, the second inputs of which are connected to the second inputs 8 of the digital storage device. The outputs of the multiplexer 2 are connected to the inputs of the second register 5, the outputs of which are connected to the first inputs of the second adder 3, the outputs of which are connected to the inputs of the first register 4, the outputs of which are connected to the second inputs of the second adder 3. The transfer output of the latter is connected to the input of the third register 6, the output of which is connected to the address input of multiplexer 2, and the clock input 9 of the device is connected to the clock inputs of registers 4-6. The output of the frequency divider 13 with a controlled division factor is the output 11 of the digital accumulator and is connected to the reset input of the frequency divider 13 with a controlled division factor, the information inputs and clock input of which are connected respectively to the outputs of the first 4 and third 6 registers.

The device according to the first embodiment operates in the following manner.

The adder 1 sums the input code K coming from the input 7 with the input code M of the capacity control coming from the input 8. The output of the adder 1 forms the code K + M. Thus, the first and second information inputs of multiplexer 2 are continuously received, respectively.

K code and K + M code. I

While the transfer signal of the adder 3 is zero, the multiplexer control input receives a zero signal at each accumulator operation time and a K code is passed to the multiplexer output, which is written to the register 5 by clock pulses. The K code is summed in the adder 3 with the output register code 4, the sum code is applied to the input of register 4 and the next clock pulse is recorded. is in register 4. When in one of the cycles of operation the drive is 31

halfway, i.e. the sum value at the output of the adder 3 reaches or exceeds the capacitance R of the accumulator, a residual is formed in the adder 3, and at the output 11 a transfer signal equals logical 1. At the next clock cycle of the accumulator, the transfer unit is written to the register 6, and the K code , in register 4 is the remainder of adder 3, the code K + M is passed to the output of multiplexer 2, the code K + L is received at the output of the adder, and the transfer signal at output 11 becomes equal to logical O, In the next clock of the accumulator, register 6 is written zero transfer totalizer output 3, to register 5, the K + M code, to register 4, the K1 + L code, to the output of multiplexer 2, the K code is again passed, the 2K + M + L code is received at the output of the adder, and a new drive operation cycle starts capacity is RM, Residual L in register 4 (the remainder from the output of adder 3 at the time of its overflow) is generally not zero. The difference between L and zero indicates that the pulse at the output of register 6 (accumulator overflow pulse) is formed with a certain time error 1, which lies in the interval from O to T (where T is the period of the clock signal), which is a result of discrete

accumulation code K.

Since the entry of the number K into the adder 3 occurs by pulses with a period TD, then any fraction of the number corresponds to the same fraction of time TD. If the numbers K and M are expressed using the same units of time, and the delay quantum is chosen equal to the low-order bit weight of these numbers, then the remainder L always corresponds to the integral delay of the overflow pulse relative to the corresponding sequence number of the ideal sequence. The overflow output pulses from register 6 are fed to the input of multi-tap delay element 12. As a result of the delay, the position of the pulses at the output of the multiplexer 10 is closer to the ideal pulse sequence.

The functions of the delay element 12 and the multiplexer 10 can be combined in the divider 13 frequency control

5 5 0 5 o

five

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114

the dividing coefficient (see Fig. (2)). Clock pulses with a frequency Q / T pass to the input of the divider 13 only when the next pulse arrives at it from register 6. The division factor is determined by the code from register 4.

With the code 00, ..., O the division factor is maximum, with the code 11, ..., 1 the division factor is equal to one. The pulses that have passed to the output of the divider 13, are fed to the input of the installation of the zero divider. Thus, before the arrival of the next pulse from the output of register 6, the divider is again turned off.

As a result of using delay element 12 together with multiplexer 10 or frequency divider 13, with controlled division factor, the phase errors at output 11 of the accumulator become less than the initial errors typical of transfer pulses of the adder 3. Thus, the methodical device boreness, caused by the discreteness of the accumulator, is compensated, and the resulting phase stability of the output pulses is determined by the stability of the delay.

Claims (2)

1. Digital storage device, auth. No. 1162040, characterized in that, with a chain of improved accuracy due to stabilization of the phase of the output pulses, a delay element and an additional multiplexer, the output of which is an output of the device, are added to it, the address inputs of the additional multiplexer are connected to the outputs of the first register, the information inputs of the additional multiplexer connected to the outputs of the delay element, the input of which is connected to the output of the third register. 2. Digital storage by auth. No. 1162640, characterized in that, in order to improve accuracy by stabilization; phase of the pulses, it is additionally introduced to the frequency depot with a controlled division factor, the output of which is the output of the digital storage device and connected to the reset input of the frequency divider 51261111 6 with controllable division factors, which are connected respectively with the information inputs and the clock input with the moves of the first and third registers.