SU1151959A1 - Frequency multiplier - Google Patents

Abstract

MULTIPLIENTER OF FREQUENCY, containing a clock pulse generator, first and second frequency dividers, first and second elements AND, first comparison circuit, synchronization unit, element OR, first and second counters, trigger, first adder, first, second and third registers, with generator output clock pulses are connected to the first input of the first element I, the clock input of the synchronization unit and the counting input of the first frequency divider, the second input of the first element I is connected to the output of the synchronization unit, and the output is connected to the counting input of the first the first counter, the first input of the first counter, the first input of the second element I, the counting input of the second frequency divider and the input resolution of the first register, the information input of the synchronization unit is connected to the senior the bit output of the adder, the remaining bit outputs of the adder are connected respectively to the information inputs of the first register, the inputs of the first group of the adder are connected respectively to the bits output The second register, the inputs of the second group of the adder are connected respectively to the bit outputs of the nepBoko register, the installation input of which is connected to the second input of the installation of the first counter, the enable inputs of the second and third registers, the installation input of the second frequency divider, the first input trigger and the first input of the OR element, the output of which is the output of the frequency multiplier, and the second input is connected to the output of the second element, AND, (L whose second input is connected to the trigger output, the second input of the trigger with Single with the output of the second frequency divider, the output of the higher bit of the first frequency divider is connected to the counting input of the second counter, the first and second groups of inputs of the first comparison circuit are connected respectively to the bit outputs of the third register and the first counter, differing in that in order to reduce the dynamic error by multiplying, a second adder, a second comparison circuit, a direct code to an additional converter, an NOT element, a clocking unit containing two B-triggers and an element First input coupled to a direct output of the first and the mounting Dtriggera Dtriggera input of the second inverse output of which is connected to the second input of the AND gate, clock inputs dvuhB

Description

triggers are combined, a group of n registers (where n is the rounding to the nearest larger number of ratios of the maximum to minimum input frequencies), a group of (n-2) elements and a group of (n-1) triggers, with the 1st trigger (1 1 , ..., and-1) the inverse output is connected to the first input of the 1st element AND, the direct output - to the second input (il) -ro of the element AND, the installation input in 1 i-ro trigger is connected to the output of i-ro element I, the installation input in the O (i + 1) -ro trigger and the recording resolution input (i + 1) -ro register, the synchronization inputs of the first to (n-1) trigger are connected to the output element nta NOT, the input of which is connected to the output of the clock generator, the synchronization input of the AND-triggers of the clock block, the third inputs of the AND elements from the first to (n-2), and the gating input of the second comparison circuit, the output of which is connected to the recording resolution input h- ro register, the setup input in 1 (nl) -ro trigger, the first input of the OR element, the inputs of the first group of the second comparison circuit are connected respectively to the discharge outputs of the first

51959

the frequency divider and the lower-bit inputs of the first register of the group, the inputs of the second group — with the bit outputs, the second counter and the higher-bit inputs of the first register of the group, and the inputs of the third group — with the bit outputs of the n-th register and inputs of the forward code converter in addition, the bit outputs of which are connected respectively to the inputs of the first group of the second adder, the lower bits of the outputs of which are connected respectively to the inputs of the second register, and the high-level outputs to the inputs of the third the register, the inputs of the second group of the second adder are connected respectively to the bit outputs (nl) -ro of the register, the bit outputs of the i-ro register are connected respectively to the bit inputs of the (i + 1) -ro register, the output of the AND unit of the clock unit is connected to the input allowing the recording of the first register of the group and the installation input to the first trigger of the group, the installation, the input of the first E-trigger of the clock unit is connected to the input information; frequency multiplier bus.

I

The invention relates to automation and computational technology and can be used in the processing of information presented in the form of often-impulse sequences.

The purpose of the invention is to reduce the dynamic error of multiplication and increase the uniformity of the output pulses following any non-uniformity of the same pulses.

The drawing shows a block diagram of the frequency multiplier. For the sake of implicitness, we take n 3.

The frequency multiplier contains a generator of 1 clock pulses, connected to output 4 to the first input of the first element I 2, the clock input of the synchronization unit 3, to the counting input of the first 4 frequency divider, to

the synchronization input of the first 5 and second D-flip-flops 6 of the clock unit 7, the input element NO 8, the third input of the third element AND 9, to the gate input of the second comparison circuit 10. The element 2 is connected to the output from the counting input of the first counter 11, and the second input - to the output of the synchronization unit 3. The installation input in O of the synchronization unit 3 is connected to the output of the first comparison circuit 12, to the first input of the installation to O of the counter 11, the first input of the second element AND 13, the counting input of the second frequency divider 14 and the recording resolution input of the first register 15 and the information input to the senior the bit output of the first adder 16; the remaining bit outputs of the adder 16 are connected respectively to the information inputs of the register 15. The inputs of the first group of the adder 16 are connected respectively to the bit outputs of the second register 17, and the inputs of the second groups of adder 16 with bit outputs of register 15, the input of installation O which is connected to the output of the second comparison circuit 10, with the second input of installation O of counter 11, inputs of recording resolution of the second and third registers 17 and 18, the input of installation O of frequency divider 14 , the first input of the first trigger 19, with the enable input of the record of the fourth register 20, with the input set to 1 of the second trigger 21 and the first input of the element OR 22. The output of the element OR 22 is the output of the frequency multiplier, and the second input of the element OR 22 is connected to the output of the element And 13 The second input of which is connected to the output of the trigger 19, connected by the second input to the output of the frequency divider 14. The high-order output of the frequency divider 4 is connected to the counting input of the second counter 23. The first and second input groups of the first comparison circuit 12 are connected respectively to the register 18 output outputs. and the counter 11. The inputs of the first group of the comparison circuit 10 are connected respectively to the bit outputs of the divider 4 frequencies and the lower bits of the fifth register 24, the inputs of the second group to the bit outputs of the counter 23 and high and the bit inputs of the register 24 and the inputs of the third group - with the bit outputs of the register 20 and the inputs of the converter 25, the direct code to the additional, the bit outputs of which are connected respectively to the inputs of the first group of the second adder 26. The lower bit outputs of the adder 26 are connected respectively with the inputs of the register 17, and the upper bit outputs - with the inputs of the register 18. The input of the second group of the adder 26 is connected respectively to the bit outputs of the sixth register 27 and the bit inputs of the register 20. Information inputs of the register 2 7 are connected respectively to the bit outputs of the register 24, and the enable input is a record of the register 27 connected to the output of the element 9, to the INPUT of the installation in O of the trigger 21 and to the input of the installation in 1 of the third trigger 28. The synchronization inputs of the trigger 21 and 28 are connected to the output of the element HE 8. Element AND 9 is connected by the first input to the direct output of flip-flop 21, and the second input is connected with the inverse output of flip-flop 28. Clock unit 7 is a linking circuit synchronized by generator 1 pulses and contains two D-triggers 5 and 6 and element And 29, the first entry is connected to the direct output of the trigger 5 and the information input of the trigger 6, the inverse output of which is connected to the second input of the element AND 29. The output of the element 29 of the clock unit 7 is connected to the input of the recording resolution 24 and the installation input of the trigger 28. The information input of the trigger 5 is connected with input information bus 30 frequency multiplier. The frequency multiplier works as follows. Clock pulses with a period T from the output of the generator 1 are fed through a hp-bit divider 4 with a division factor K equal to the required multiplier factor multiplier to the input of the P-bit counter 23. In response to the j-th input pulse from the input information bus 30 The frequency multiplier arriving at the clock unit 7, the nearest clock pulse of the generator 1 appears at the output of the element 29 of the clock unit 7, this pulse with its leading edge transfers the number from the divider 4 and the counter 23 to the register 24, i.e. fixes the beginning of the j-ro period of the input signal, and prepares the trigger 28 for installation in O. At the same time, the trigger 28 is set to O with the clock edge from the inverter, the clock with the divider 4 and the counter 23 is counted with the same clock edge. The next clock pulse passes through the AND 9 circuit and prepares the trigger 21 to be set to O, and the trigger 28 to set to 1. The leading edge of this pulse transfers information from the register 24 to the register 27, and the falling edge sets the trigger 28 to 1, and trigger 21 in O. As a result of coincidence of codes in register 20, divider 4 to counter 23, the next clock pulse transfers information from register 27 to register 20, sets counter 11 to O, and trigger 21 to 1, the same pulse carries information from the outputs of the adder 26 in the registers 17 and 18, OBN street register 15, divisor 14, trigger 19 and passes through the element OR 22 to the output of the multiplier. The next triggering of the comparison circuit 10 occurs when the number in register 20 is equal to the number recorded in divider 4 and counter 23, i.e., after a time equal to the number of records in register G of watches 24 after the considered one, where N CG is rounded to the nearest integer expression, N - counter capacity 23 (for our example 6Х.1Т.01Х b. TO-K irl with Г1 3 М Since time t is longer than the maximum period of input pulses, during this time at least one pulse transfers the number from divider 4 and counter 23 to register 24 and causes the installation of tr igger 28 to O. Each information transfer pulse into register 20 causes a setting of 1 flip-flop 21 and thus allows the next clock pulse to pass through AND 9 circuit and transfer information from register 24 to register 27. On the other hand, every pulse from the circuit output 10 comparisons appear through time T after a pulse arrives from the output of the clock unit 7 at the register recording resolution input 24 and the installation input to the trigger 28. Thus, the period of the pulses at the output of the code comparison circuit 10 is equal to the period of the input pulses with a time delay m. T. The number recorded in register 20 at the moment of arrival of any delayed pulse from the output of circuit 10 is equal to the number recorded in register 24 at the moment of arrival of the corresponding input pulse from the output of clock unit 7, and the number recorded in this the moment in register 27 is equal to the number recorded in register f 24 by the following input pulse from the output of block 7. In other words, if the input j pulse arrived at the moment .j, then the corresponding delayed pulse comes from the output of the comparison circuit 10 at the moment tj . ig, (+ T, since it is at this moment that the number entered in register 24 at the moment again appears at the outputs of divider 4 and counter 23 after they overflow. At the same time, -tjj in register 27 is the number that was in divider 4 and counter 23 at the time tbx.Cj + f) the arrival of the next (j + 1) -ro input pulse. Thus, by the time i jj, the inputs of the adder 26 receive the direct code of the number written in register 27 and the additional number written in register 20, which forms the code converter 25. As a result, the output of the adder 26 generates a code Nj of the difference of these numbers. This is the j-ro code for the period. input signal. At the moment - good. m bits of the code N; transferred to register 17, and the high bits of register 18. At the same time, register 15, counter 11, divide 14, trigger 19 are zeroed out. Thus, in registers 17 and 18, the fractional and pulses (Ny) entering the input of the divider 4 for the j-th period of the input signal, by a factor K. In the next interval of time. Equal to T, the operation of the described part of the multiplier is similar. -.....-. gcht-, "" "During the delayed jth period, the result N., recorded in register 18, is compared by means of the comparison circuit 12 with the current value of the number of pulses counted about 11. At the moment of coincidence codes at the inputs of the comparison circuit 12, an impulse is formed at its output, which resets the counter t1, and through element 13 the element OR 22 passes through the multiplier output. If, in this case, the AND 2 element is open during the entire period of the multiplied frequency, then the pulses at the output of the comparison circuit 12 appear at intervals of time through the Internet-PI. ™ e 4 are part of the ratio. As a result, at the output of the multiplier, each Pth pulse appears ahead of time (error) by time tp

I1

i i

fractional part

.T.p

where 1 i-

relationship

The reduction of this static error in the operation of the multiplier is as follows. Code

LM residue; from the division of N; on K with youN.

the register 17 enters the first input of the adder 16. Upon the arrival of the first pulse from the output of the comparison circuit 12, this code from the adder 16 is copied to the register 15, and from the output of the register 15 is fed to the second input of the adder 16. Thus, during the period of the frequency multiplied by the adder 16, residual codes are added, the result is increased by uN; with the arrival of each pulse from the output of circuit 12. If the current value of the sum of residuals is equal to or exceeds the number K, then the output of the high bit of the adder 16 generates a signal of logical 1. This signal from the output of the adder 16 is fed to the information input of block 3 ,. given in the initial state by a pulse from the T2 circuit and controlled by the pulses of the generator 1. Block 3 generates a pulse of duration T, which shuts down the T element I 2 for time T, prohibiting the passage to the input of the counter 11 of a single pulse from the output of the generator 1.

As a result, due to the fact that not the (j-1) -ro period code (as in the known device) but the j-ro code value is used to form the output pulses during the j-th input signal period, the dynamic multiplier error is excluded. The multiplier error is practically determined by a static error that does not exceed one.

At the end of the period of the multiplied frequency, the output pulses of the comparison circuit 12 are fed to the counting input of the divider 14 with the coefficient (K-1). If the divider 14 has time to arrive at the counting input (K-1) of the pulses, and the period of the multiplied frequency has not yet expired, then the signal from the output of the divider 14 closes the And 13 element through trigger 19 and stops the delivery of pulses to the output of the multiplier I

Thus, the proposed multiplier allows, in comparison with the known one, to reduce the non-uniformity of the pulse following the output sequence after a high rate of change of the input signal period and to eliminate the dynamic error of frequency multiplication.

Claims (1)

A frequency multiplier comprising a clock, first and second frequency dividers, first and second AND elements, a first comparison circuit, a synchronization unit, an OR element, first and second counters, a trigger, a first adder, first, second and third registers, the generator output clock pulses is connected to the first input of the first element And, the clock input of the synchronization unit and the counting input of the first frequency divider, the second input of the first element And is connected to the output of the synchronization unit, and the output - with the counting input of the first counter Ika, the input of the installation in O ”of the synchronization unit is connected to the output of the first comparison circuit, with the first input of the installation in 0 of the first counter, the first input of the second AND element, the counting input of the second frequency divider and the recording enable input of the first register, the information input of the synchronization unit is connected to the highest bit output of the adder, the remaining bit outputs of the adder are connected respectively to the information inputs of the first register, the inputs of the first adder group are connected respectively, with -bit outputs of the second register, the inputs of the second adder group are connected respectively with the discharge outputs of the first register, the input is set vka 0 which is connected to the second input of the setting at 0 of the first counter, the recording enable inputs of the second and third registers, the setting input to 0 of the second frequency divider, the first input of the trigger and the first input of the OR element, the output of which is the output of the frequency multiplier, and the second input is connected with the output of the second element And, the second input of which is connected to the output of the trigger, the second input of the trigger is connected to the output of the second frequency divider, the high-order output of the first frequency divider is connected to the counting input of the second counter, the first and second groups of inputs of the first comparison circuit are connected respectively to the discharge outputs of the third register and the first counter, characterized in that, in order to reduce the dynamic error of the multiplication, a second adder, a second comparison circuit, a direct code to additional converter, an element NOT are introduced into it, a timing block containing two 2-flip-flops and an AND element, whose first input is soy. dinen with direct output of the first 2 trigger and the installation input of the second D-trigger, the inverse output of which is connected to the second input of the And element, the synchronization inputs of two 2SU .... 1151959 triggers are combined, a group of η registers (where and is rounding to the nearest larger number of ratios maximum to minimum input frequencies), a group of (n-2) AND elements and a group of (n-1) triggers, and the ίth trigger (1 = 1, ..., I ~ 1) is connected by an inverse output to the first input t-ro of the And element, direct output - with the second input (il) -ro of the And element, installation input to the 1st 1-th trigger with it is single with the output of the i-ro element AND, the setup input to the ”0 (i + 1) -ro trigger and the write enable input (i + 1) -ro register, the trigger synchronization inputs from first to (h-1) ~ ft are connected to the output of the element NOT, the input of which is connected to the output of the clock generator, the synchronization input of the D-triggers of the clock unit, the third inputs of the elements AND from the first to (n-2) th, the gate input of the second comparison circuit, the output of which is connected to the recording resolution input η -th register, the input of the installation in 1 (p-1) -th trigger, the first input of the OR element, the inputs of the first groups of the second comparison circuit are connected respectively to the bit outputs of the first frequency divider and the lower bit inputs of the first register of the group, the inputs of the second group to the bit outputs, the second counter and senior bit inputs of the first register of the group, and the inputs of the third group to the bit outputs of the ηth register and the inputs of the direct code to additional converter, the bit outputs of which are connected respectively to the inputs of the first group of the second adder, the lower bit outputs of which are connected respectively with the inputs of the second register ^ the senior bit outputs are with the inputs of the third register, the inputs of the second group of the second adder are connected respectively to the bit outputs of the (n-1) th register, the bit outputs of the регистра-th register are connected respectively to the bit inputs (i + 1) -th register, the output of the AND element of the clock block is connected to the write enable input of the first register of the group and the input to the 0 of the first group trigger, the installation 'input of the first D-trigger of the clock block is connected to the input information. frequency bus of the frequency multiplier.