SU1557561A1 - Counter-type adder - Google Patents

Abstract

The invention relates to automation and computing and can be used in the construction of display devices. The aim of the invention is to extend the functionality by providing a pre-entry of a binary number code. The goal is achieved by the fact that the accumulating adder additionally contains a counter, two NOT elements, a block of comparison elements, a trigger, two AND elements with corresponding links. 1 il.

Description

 The invention relates to automation and computing and can be used in the construction of display devices.

The purpose of the invention is to enhance the functionality of the accumulating adder by providing a preliminary entry of a binary number code.

The drawing shows a structural diagram of the accumulating adder.

The accumulating adder contains adder 1, memory register 2, counter 3, the first element is NOT 4, the block of elements of comparison 5, the second element is NOT 6, the trigger 7, the first element AND 8, the second element AND 9.

The accumulating adder receives the following information and signals: the second input of the adder 1 is the binary code of the summed number; the inputs C2 of the memory register 2 and the input of the second element And 9 - signal Record; at the inputs of the first element HE 4 and S trigger input 7 - signal reset; on

the second input element And 8 - clock frequency (Fr); to the second input of the block of elements of comparison 5 is the binary code of the number of the preliminary recording.

The output of counter 3 is the output of the accumulating adder.

Accumulating adder works as follows.

Consider the operation of the circuit with the arrival of the signal Zero, under the action of which the trigger 7 switches and from its output to the first input of the element And 8 is removed 1.

At the same time, the signal Zero is inverted by the element HE 4, is fed to the input of the zero setting R of the counter 3, and zeroed it.

At the output of counter 3, the value O is set for all bits, which is fed to the adder 1 and the block of elements of the comparison 5.

The value O at the output of counter 3 is maintained for the duration of the Zero signal.

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With the end of the signal, the zeroing clock pulses F through the element And 8 arrive at the input of the direct count (+1) of the reversing counter 3, where the pulses of the clock frequency FT are summed. When the binary number code of the counter 3 becomes equal to the binary number code of the preliminary recording arriving at the block of comparison elements 5, then the signal 1 is output from the output () of the block of comparison elements 5. This signal is inverted by the HE element 6 and fed to the trigger input 7.

Trigger 7 is switched. The passage of clock pulses through the element AND 8 to the counter 3 is stopped, since with the switching of the trigger 7 from the output of the first input of the element And 8, the voltage O is applied.

Thus, before the commencement of the summation, counter 3 of the code of a given binary number is recorded.

Next, the input of the adder 1 is the binary number code, which is added to the contents of the counter 3.

The amount received is written to memory register 2 at the time of the fall of the signal. Record at its input C2. By the same impulse, but with a delay on the element And 9 on the potential O arriving at the input of the preliminary recording C of the counter 3, the binary code of the number from the register of the memory 2 is copied to the counter 3.

With the arrival of the next signal, the recording of the summation cycle is repeated.

As a result of the summation at the output of the accumulating adder, we obtain the value of the binary code S1

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the value of the binary code of the number at the output of the accumulating adder;

- pre-recorded number in the counter before summing;

-code binary number supplied to the adder 1;

- number of signals recording,

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With the arrival of the signal Reset, the whole cycle repeats.

Claims (1)

Invention Formula The accumulating adder containing the adder and the memory register, wherein the output of the adder is connected to the information input of the memory register, and the second input of the adder - to the input of the summed number of the accumulating adder, characterized in that in order to expand the functionality of the device by providing a preliminary code recording binary number, a counter, two NOT elements, a block of comparison elements, a trigger, two AND elements are entered into the accumulating adder, and the output of the memory register is connected to the information input with The sensor whose output is connected to the first inputs of the adder and block of comparison elements, the output of the first element is NOT connected to the installation input of the counter zero, the input of the Direct account of which is connected to the output of the first element And whose first input is connected to the output of the trigger, the installation input to the zero state trigger trigger is connected to the output of the second element NOT, the input of which is connected to the output of the block of comparison elements, the output of the second element I is connected to the pre-record control input of the counter, the preliminary control input recordings of the memory register and the input of the second element I are connected to the input of the signal Record accumulating adder, the input of the first element NOT and the input of setting the trigger state are connected to the input of the signal Resetting the accumulating adder, the second input of the first element I connected to the input of the clock frequency of the accumulating adder, the second input of the unit of comparison elements is connected to the input of the code of the preliminary record of the accumulating adder, and the output of the counter is connected to the output of the accumulating adder. foot vucsra ffb / xoff yam / en 7 li