SU1374426A1 - Digital storage with fractional variable capacitor - Google Patents

Abstract

The invention relates to a pulse technique and can be used in pulse signal processing devices, as well as in digital frequency synthesizers. The purpose of the invention, the expansion of the range of capacitance of a digital storage device, is achieved by the possibility of obtaining a fractional variable storage capacity. For this, a third adder 11, a second multiplexer 12, and a controlled frequency divider 13 are additionally introduced into the digital storage device. The accumulator also contains adders 1 and 3, multiplexer 2, accumulating registers 4, 5 and 6, input code bus 7, control tank 14 of the whole part of M capacitance, bus 15 of control of the fractional part / 5 of capacitance. By changing the value of p, and the division factor o (frequency divider 13, you can get / 5 any value -, which expands w (L functionality of the accumulator. 1 Il.

Description

technology and can be used in devices processing pulse signals, as well as in digital frequency synthesizers.

The purpose of the invention is the expansion of the range of changing the capacity of a digital storage device due to the possibility of obtaining a fractional variable capacity of the storage device.

The drawing shows a structural electrical circuit of a digital storage device.

devices, and the output is connected to the second information input of the second

multiplexer 12. Informational

the input of the controlled frequency divider 13 is connected to the bus 16 for controlling the division ratio of the frequency divider 13. The device works as follows.

in a way.

The adder f1 sums the input control code M for controlling the integral part of the storage capacitor, coming from the bus 14, with the input control / fraction control

The digital storage device contains the first if part of the capacity tank, the incoming adder 1, the first multiplexer from the bus 15, as a result of which 2, the second accumulator 3, the first accumulator output of the adder 11, the code 4 is generated: the second accumulating register 5 and the third accumulating M + 3. Thus, the first and second information inputs of the multiplex register 6. The first input of the first 20 crap 12 continuously receives the codes M of adder 1 connected to the first information and M + /, respectively. If the signal is made by the input of the first multiplexer 2 and bus 7 of the input code K

The device, the first 8 and second 9 outlets of the control input of the multiplexer 12, coming from the output of the controlled frequency divider 13, is zero, the dyes of which are connected respectively 25 to the second input of the adder 1 after the transfer output of the second adder code M. Adder 1 summarizes Pa 3 and the output of the first accumulating code M with the input code K. received from the bus 7. The output of the adder 1 forms the code K + M, resulting in register 4, the clock input of which is connected to the clock input 10 of the drive and the clock inputs of the second 30 th on the first and tue Information Society

the accumulating register 5 and the third accumulating register-6, the output of which is connected to the control input of the first multiplexer 2. The second insusmator 1, and the output of the first multiplexer 2 is connected to the information input of the second register-accumulating input and output of which are connected respectively to the output and information input of the first accumulating

the multiplexer 2 inputs receive the K and K + M codes respectively. While the transfer signal of the adder 3 is zero, the control input of the multiplex input of the first multiplex 35 is 2 and the output of the first body is connected to the output of the first body, zero and. To the output of multiplexer 2, a code K is passed, which by clock pulses is written into accumulating register 5. pa 5, the output of which is connected to the first 40 code K is summed in adder 3 with the input of the second adder 3., the second output code of accumulating register 4, code sum n is given to the input of the register 4 and the next clock pulse is recorded in the

register 4, the device also contains 45 register 4. When in one of the cycles

the third adder 11, the second multiplexer 12, and a controlled frequency divider 13. The clock input of the controlled frequency divider 13 is connected to

the output of the third register is b, and the output 50 is the output 9 of the transfer signal,

equal to logical 1. In the following

connected to the control input of the second multiplexer 12, the output of which is connected to the second input of the first adder, and the first information

The accumulator unit is written to the accumulator 6 in the accumulator register; register 5 is the K code; the input of the third input is connected to the first 55 register 4, the remainder of the adder 3, and on the second adder 11 and the control bus 14, the output of the multiplexer 2 is passed M of the capacitance is the code K + M, at the output of the adder 3 of the device, the second input of the third being the code K t L is formed, and at the output 9

go adder 11 is connected to. tire 15

part of the tank, which comes from the bus 15, as a result of which a code is generated at the output of the adder 11

M + 3. Thus, the first and second information inputs of the multiplex control input of the multiplexer 12, coming from the output of the controlled frequency divider 13, are zero, .to the second input of the adder 1, the M code is received. The adder 1 summarizes

the M code with the input code K. received from the bus 7. At the output of the adder 1, the K + M code is formed, as a result of the drive, i.e. the sum value at the output of the adder 3 reaches or exceeds the capacity R of the Accumulator, in the adder 3 a residual is formed

logical 1 is formed. In the next cycle of operation of the accumulator, the zero from the transfer output of adder 3 is written to accumulating register 6, the K + M code is written to register 5, the K + L code is sent to register 4 c, the K code is again passed to the multiplexer 2 output, code 2 K + + M + L and a new cycle of operation of the accumulator begins, in which the capacitance u will be equal to R - M.

The signal from the output of register 6 is fed to the input of a controlled divider 13, which produces a pulse with a duration equal to the period following the output accumulator overflow pulses and at a frequency determined by the division factor with / programmed. Thus, at the output of the multiplexer 12, the code M + / ь is passed only at the instants of time determined by the power factor of the controlled divider 13, i.e. once per d drive cycles. As a result, in (s / -1) 25 iklah of work of the accumulator of its capacity are equal R - M, and in one - the CYCLE of its work - (R - M - / j).

Thus, the average value of the capacity of the accumulator over the cycles of is-5 DA about:

., (R - M) (o (- 1) + (R - M - L) RC;

 R-M-J

From the expression it follows that by changing the value of the code / i and the division factor of the controlled frequency divider 13, any fraction value b / of can be obtained, which expands the functionality of the device.

Claims (1)

Invention Formula A digital drive with a fractional bandwidth containing the first adder, the first multiplexer, and the second 15 20 25 ZO ) 35  40 The 45th adder, the first, second and third accumulating registers, the first input of the first adder is connected to the first information input of the first multiplexer and the accumulator input code bus, the first and second accumulator outputs are connected respectively to the transfer outputs of the second adder and the first register, the clock input of which is connected to clock input of the accumulator and clock inputs of the second and third accumulation registers, the output of which is connected to the control input of the first multiplexer, the second information input cat The first is connected to the output of the first adder, and the output is connected to the information input of the second accumulating register, the output of which is connected to the first input of the second adder, the second input and the output of which are connected respectively to the output and information input of the first register, characterized in that changes in the capacitance of the accumulator, a third adder, a second multiplexer and a controlled frequency divider, the clock input of which is connected to the output of the third accumulator register, and the output connected the control input of the second multiplexer, the output of which is connected to the second input of the first adder, the first information input to the first input of the third adder and the control bus for the whole part of the storage tank, while the second input of the third adder is connected to the control bus with the fractional part of the storage capacitor, and the output with the second information input of the second multiplexer, wherein the information input of the controlled frequency divider is connected to the control bus of the division ratio of the frequency divider.