SU1277102A1 - Device for extracting root - Google Patents

Abstract

The invention relates to the field of automation, computer technology and can be used in systems of automatic control and monitoring, in particular in digital linearizing devices, as well as in devices for the hardware implementation of mathematical tools for electronic computer. The purpose of the invention is to improve the reproduction accuracy of the function x. The purpose of the invention is achieved by the fact that in the device containing the counter, two accumulating adders, two delay elements, the OR element, two combinations are additionally introduced (one multiplier. 1 Il.

Description

The invention relates to automation, computer technology and can be used in automatic control and monitoring systems, in particular in digital linearizing devices, as well as in hardware implementations of mathematical tools for electronic digital computers.

The purpose of the invention is to increase the accuracy of reproducing the function x

The drawing shows a block diagram of the device for extracting the root

The device for extracting the root contains counter 1, the first combinational multiplier 2 with the first 3 and second 4 groups of inputs, the first accumulating adder 5, the second combinaid multiplier 6 with the first 7 and the second 8 groups of inputs, the second accumulating adder 9, the element OR 10 with the first 11, second: 12 and third 13 inputs, the first 14 and second 15 delay elements,

In the device, the second input 12 of the element OR 10 is connected to the output of the first delay element 14, the first input 11 of the element OR 10 is the input of the device-, the output of the element 10 is connected to the clock input of counter 1, the second of the second delay element 15 is connected to the third input 13 of the element OR 10, the input of the second delay element 15 is connected to the overflow output of the first accumulating adder 5, the clock input of which is connected to the clock input of the counter 1 and to the clock input of the second accumulating adder 9, whose overflow output is connected the input of the first delay element 14, the group of information inputs of the second accumulating adder 9 is connected to the group of outputs of the second combination 1 of the multiplier 6, the first group of inputs of which is connected to the group of inverse bit outputs of counter 1, and the second group of inputs to the group of forward bit outputs counter 1, the group of information inputs of the first accumulating adder 5 is connected to the group of outputs of the first Raman multiplier 2, the first 3 and the second .4 groups of inputs of which are connected to inverse bits of you counter moves 1,

The device works as follows.

five

0

five

In the initial state on accumulation, adders 5 and 9 are in the single state, counter 1 is in the zero state. The increment dx of the input pulse sequence x, which enters the device, causes the output element OR 10 to increment dz of the pulse sequence z and forms in the counter 1 the current value of the number Z. At the inverse outputs of the counter 1, the number zl is formed (wheref is the counter size 1), which is fed to the first 3 and second 4 groups of inputs of the combinational multiplier 2 and to the first group of inputs 7 of the combinational multiplier 6, to the second group of inputs 8 of which the direct code z is fed. We derive the device operation formula for the case when the number (ie, the additional code of the number z). At the output of the combinational multiplier 2, the current value of the number A (2 -z) 2j appears on the code of the combinational multiplier 6 - the current value of the number R - () z. The accumulating adders 5 and 9 are used as the first and second controlled divisors Frequency ,, The control input of the frequency divider is the clock input of the accumulating adder, the output of the controlled divider-frequency is the transfer output of the accumulating adder, the group of control inputs of the controlled frequency divider, to which the code is applied, m divider is a group invariant formatsionngh inputs of the accumulator of the first controllable frequency divider described expression

,(one)

where A is the code, I set the 1: iy factor of 45 division of the first controlled one

frequency divider; dz is the increment of the input pulse sequence z of the first controlled divide- 50 l of frequency;

dy is the increment of the output pulse sequence at the first controlled frequency divider;

55 2n is the size of the group of information inputs of accumulating adder 5 or

0

five

40

...

The operation of the second controlled frequency divider is described by the expression

,

coefficient code

division of the second controlled frequency divider

incrementing the input pulse sequence z of the second controlled frequency divider;

the increment of the output pulse-) j-th sequence 1 of the second controlled frequency divider;

the size of the group of information inputs of the accumulating adder 9,

i - 2 -z) z,., 4

dl -2t; 7dz.С4)

TOR 10 and elements 14 and 15, together with the input, convert the pulsator. therefore

z dx + dy + dl. (5)

together (2), (4), (5), 0

2 -2 idz + - | -) dz; (6)

h

2 -Z

.

Integrating (8), we find the current value of the number z in the counter 1 40

2 2

 X,

Yu

 ) j 20

0

35

0

Denoting, we get

.(P)

Thus, in the form1 cruster counter, the current value of the number is t t k-x,

In the proposed device, the control is carried out by the reverse code, and all relationships are derived in the additional code control suggestions. It is more correct to obtain dependencies to control the reverse code and then to neglect the component caused by the difference between the additional and reverse codes.

Claims (1)

The invention relates to automation, computer technology and can be used in systems of automatic control and monitoring, in particular in digital linearizing devices, as well as devices for the hardware implementation of mathematical tools for electronic computer. The purpose of the invention is to increase the reproducibility of the function x. The drawing shows the block diagram of the device for extracting the root. The device for extracting the root contains counter 1, the first combinational multiplier 2 with the first 3 and second 4 groups of inputs, the first accumulating adder 5, the second combination multiplier 6 s the first 7 and second 8 groups of inputs, the second accumulating adder 9, the element OR 10 with the first 11, the second: 12 and the third 13 inputs, the first 14 and the second 15 delay elements, In the device, the second input 12 of the element OR 10 connect not with the output of the first delay element 14, the first input 11 of the element OR 10 is the input of the device-, the output of the element. JET 10 is connected to the clock input of the counter 1, the output of the second delay element 15 is connected to the third input 13 of the element OR 10, the input of the second ele The delay element 15 is connected to the overflow output of the first accumulating adder 5, the clock input of which is connected to the clock input of the counter 1 and to the clock input of the second accumulating adder 9, the overflow output of which is connected to the input of the first delay element 14, group the formation inputs of the second accumulating adder 9 is connected to the output group of the second combination of 1 multiplier 6, the first group of inputs of which is connected to the group of inverse discharge outputs of counter 1, and the second group of inputs to the group of forward direct discharge outputs of counter 1, the group of information the inputs of the first accumulating adder 5 are connected to the group of outputs of the first combination multiplier 2, the first 3 and the second .4 groups of inputs of which are connected to the inverse discharge outputs of counter 1, the device operates as follows time. In the initial state, the accumulator adders 5 and 9 are in the same state, the counter 1 is in the zero state. The increment dx of the input pulse sequence x, which enters the device, causes the output element OR 10 to increment dz of the pulse sequence z and forms in the counter 1 the current value of the number Z. At the inverse outputs of the counter 1, the number zl is formed (wheref is the counter size 1), which is fed to the first 3 and second 4 groups of inputs of the combinational multiplier 2 and to the first group of inputs 7 of the combinational multiplier 6, to the second group of inputs 8 of which the direct code z is fed. We derive the device operation formula for the case when the number (ie, the additional code of the number z). At the output of the combinational multiplier 2, the current value of the number A (2 -z) 2j appears on the code of the combinational multiplier 6 - the current value of the number R - () z. The accumulating adders 5 and 9 are used as the first and second controlled divisors Frequency ,, The control input of the frequency divider is the clock input of the accumulating adder, the output of the controlled divider-frequency is the transfer output of the accumulating adder, the group of control inputs of the controlled frequency divider to which the code is applied, sets the coefficient t divider is the group of information inputs of the accumulating adder. The operation of the first controlled frequency divider is described by the expression, (1) where A is the code, specifying the 1: dividing ratio of the first controlled frequency divider; dz is the increment of the input pulse sequence z of the first controlled frequency divider; dy is the increment of the output pulse sequence at the first controlled frequency divider; 2n is the size of the group of information inputs of accumulating adder 5 or ... The operation of the second controlled frequency object is described by the expression, where B is the code specifying the division factor of the second controlled frequency divider dz is the increment of the input pulse sequence z of the second controlled divides l frequency; dl is the increment of the output pulse sequence 1 of the second controlled dividing frequency; 2n is the size of the group of information inputs of accumulating adder 9, or i-2-z) z,., Dl -2T; 7dz.C4 Element OR 10 and delay elements 14 and 1 together with the converter input are a pulse adder. Therefore, dz dx + dy + dl. (5) Resh together (2), (4), (5), we get dz dx + 2 -2 idz + - | -) dz; (6) 2 -Z. Integrating (8), we find the current value of the number z in the counter 1 2 2 Denoting, we get. (P) Thus, in the counter1 form the crust the current value of the number z tk-x, In the proposed device, the control is performed by the reverse code, and all the relations are output in the additional code control i suggestions. It is more correct to obtain dependencies for controlling the reverse code and then neglecting the component caused by the difference between the additional and inverse codes. Claims A device for extracting a root, containing a counter, two accumulating adders, an element 1, two delay elements, characterized in that, in order to improve accuracy, it additionally contains first and second combinational multipliers whose outputs are connected to information inputs of the first and second accumulating adders respectively, the overflow outputs of the first and second accumulating adders are connected via the first and second delay elements with the first and second inputs of the OR element, the third input to The second is the input of the device argument, the output of the OR element is connected to the clock inputs of the counter and the first and second accumulating adders, the first and second information inputs of the first combinational multiplier are connected to the direct and first inverse outputs of the counter, respectively, the second and third inverse outputs of which are connected to the first and second information inputs of the second Raman multiplier,