SU1205151A1 - Digital function generator - Google Patents

Description

 ,

The invention relates to automation and computing and can be used in automatic control and monitoring systems, in particular, in digital linearizing devices, as well as in devices for the hardware implementation of digital computer hardware.

The purpose of the invention is to improve the reproduction accuracy of the function ak / k-Q-x

FIG. 1 is a block diagram of a digital functional converter; in fig. 2 - time diagrams of the operation of a pulse subtractor circuit consisting of an L - trigger and an OR element.

The digital functional converter contains input 1, counter 2, multiplier 3 with first 4 and second 5 inputs, accumulating adder 6, element OR 7 with inputs 8 and 9 and output 10, as well as an L-trigger 11 with inputs 12 and 3.

Digital functional Converter works as follows

In the initial state, the accumulating adder 6 is in the single state, the number a is pre-recorded in the counter 2. The increment dx of the input pulse sequence X arriving at input 1 causes the appearance at the output 10 of the element OR 7 the increment A t, the pulse sequence 1, and forms in the counter 2 the current value of the number 7., which is fed to the VC. ODES 4 and, 5 multiplier 3. This causes the occurrence of the current value of the number 2 at the inversion outputs of multiplier 3.

A 2 -and 1,

where 2n is the size of the information inputs of the accumulating adder 6.

Accumulator adder 6 is used as a controlled frequency divider. The control input of the frequency divider is the control input of the summation of the accumulating adder, the output of the controlled frequency divider is the overflow output of the accumulating adder, a group of control inputs of the controlled frequency divider, to which

511

the code defining the division factor are the information inputs of the accumulating adder together with the transfer input from the last bit, which is set to 1.

The operation of the controlled frequency divider is described by the expression:

J i

(one),

de A + 1

a code specifying the division ratio of the controlled frequency divider;

(ix is the increment of the input pulse sequence X of the controlled frequency divider;

djj is the increment of the output pulse sequence of the controlled frequency divider.

h

n2m

(2)

X.

Element OR 7 and Yu-trigger 11 form a pulse subtractor, therefore

c 2 c3x-dy,

(2) and {3) get Jx

-, 2n

(3)

(four)

Integrating (4) taking into account the limits of integration, one finds the current value of the number in counter 2:

. g

about u

.

 )

X

22V

gp

D 2

2n

AND

Denoting K 2, get

C |. |

k-q x

Thus, in counter 2, the current value of the number

gk-a X

Editor L. Pchelinska

Order 8536/51 Circulation 709 Subscription

VNIIPI USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5

Branch PPP Patent, Uzhgorod, st. Project, 4

Compiled by A. Shul Pov

TechredM. Parotsay Proofreader L. Patay

Claims (1)

(.54) A DIGITAL FUNCTIONAL CONVERTER containing a counter, a mixer and an OR element, characterized in that, in order to increase the accuracy of the ak / kax function, an accumulating adder and a D-trigger are introduced into it, and the input of the converter is connected to the first input of the element OR, the control input of the accumulating adder and the C-input of the T> trigger, the output of which is connected to the second input of the OR element, the output of which is connected to the input of the counter, the output of which is connected to the first and second inputs of the multiplier, the output of which is • connected nen to an information input of the accumulator, whose overflow output is connected to AND -triggera -Log D, the last discharge transport accumulator input coupled to an input of unit inverter capacity. SU. „. 1205151> 1205) 5) the code defining the division coefficient are the information inputs of the accumulating adder together with the transfer input from the last digit, which is set to 1. The work of the controlled divider is described by the expression: funds matemCVM. increase in accuracy of ak / k-ah. stota