SU1206957A1 - Number-to-voltage converter - Google Patents

Description

one

The invention relates to the field of computer technology and can be used to restore grid processes as a digital-to-analog converter.

The purpose of the invention is to improve the accuracy of the converter, by forming, before filtering, pulses that are uniformly distributed during the conversion period.

. The drawing shows the functional diagram of the device.

The converter contains a register of a source 2 of the reference voltage, a filter 3 of the low frequencies (LPF), a switch, AND -I elements OR 5, and AND a 1-bit combination adder 6.

The information input of the switch 4 is connected to the output of the source 2 of the reference voltage, and the output to the input of the low-pass filter 3. The first inputs h -1 of the OR elements are, respectively, M -1 b, our input code. The second inputs P – 1 of the elements OR are combined with the transfer input of the low-order bit P – 1 – bit combiner adder 6 and is the h − 1 bus of the input code. The outputs M -1 of the OR element are connected to the corresponding hl first inputs of the h -1-bit Raman adder 6, the second h-1-e inputs of which are connected to the corresponding outputs of the register 1, and the outputs to the corresponding information inputs of the register 1. Transfer output The bit of the adder 6 is connected to the 1st information input of register 1, h is the output of which is connected to the control input of switch 4, and the synchronization input is a sync bus ,, Output LPF 3 is an output bus.

 The Converter operates as follows.

In the initial state, register 1 is cleared. A number is set at inputs 7 of the converter (O ... 0). Inlet 8, pulses with a period T follow. At the output of the source 2 of the reference voltage, a constant voltage acts as UQ. At the control input of switch 4, the level is low, which corresponds to a constant voltage at the output of switch 4 and at the output of the converter, equal to -Uo.

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The inputs 7 receive the binary and bit numbers synchronously with the clock pulses at the input 8, and the change of the number must occur through a time interval that is a multiple of T. 2 T, i.e. for the duration of the number must pass smoothly pulses.

From the moment when 10 on the bus 7 of the converter is set to a binary number, greater (O ... 0) and less (1.0 ... 0), as clock pulses arrive at outputs 1 ... n 1st register 1 is mapped to 1S uniformly increasing number sequence according to

F (i) iN mod, where i 1,2 ....

For some value, a situation occurs in which

N + IN

In this case, at the output of R., the transfer of the senior bit of the adder is 6 2J. a unit appears, which is rewritten by the i + 1st pulse in the nth register bit 1, at the inputs of the sum of the adder 6, connected with and the -1st inputs of register 1, we have the number FN + iN - N. Therefore, i -t- to the 1st pulse, the unit from output P, adder 6 is removed. The unit recorded in the nth digit of de register 1 switches switch 4 and a voltage of +11 from the output of source 2 of the reference voltage occurs at the input of the low-pass filter 3. On the next i + 2nd pulse, the state of the AND th bit of register 1 returns to the initial state. 40

Thus, a single pulse of duration Td and amplitude 211 is formed at the input of the filter, shifted to the negative voltage region by -U (,.

After passing 2 pulses on the sync bus 8, exactly N is generated at the output of the n-th bit.

5Q pulses with duration T and by I ... and -1st bits of register 1 are cleared (on Table I 2 8, and N 5).

From tab. 1 shows that the average

, j the value at the output of the converter is determined from the expression

thirty

and

R

and"

N 2

When the value of N is equal to the maximum conversion code (1.0 ... 0), then a high level of the n-th bit is simultaneously applied to the transfer input of the low bit of the adder 6 and to the inputs of the logic elements OR 5. At the same time, the output of the transfer of the higher bit Yes, adder 6 always has a unit, since overflow is provided by converter inputs as a result of adding the number from the outputs of the elements OR 5, equal to 2 - 1, with the unit at the transfer input of the lower bit of the adder 6.

ZL ILJlTL.ILDZL.JIIlLJ-i

5 27

O 1 o

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Make a table. 2 with n 4 for all values of N and for the sake of consistency, we introduce only the sign of the voltage at the output of switch 4.

5 From table. 2 that when N О O or 2 filtering is not required, since the voltage at the input of the switch 4 is always constant. Consequently, the distribution of the signs of the pulses is relatively uniform and the sign changes as often as possible, which makes it possible to reduce the filtering error and, consequently, to increase the accuracy of the conversion.

Table 1

0

about

Claims (1)

A CODE-VOLTAGE CONVERTER containing a register, a reference voltage source, and a switch, the information input of which is connected to the output of the reference voltage source, and the output is connected to the input of the low-pass filter, heating element, or OR elements, the first inputs of which are respectively h -1 input busbars code, and a -1-bit combiner, the first h -1th inputs of which are connected to the outputs of the corresponding η -I elements OR, the second p -1th inputs - with the corresponding outputs of the register, the outputs - with the corresponding information inputs of the register, Exit MSB summato tsioinymi transfer ra - I-m with an information input register, h-th output is connected to a control input of the switch and the clock input is the synchronization bus; second entrances. AND -1 elements OR combined with the inputs of the transfer of the least significant bit η -1-bit combinational adder and are And - bus input h a-