SU1372593A1 - Digital phase shifter - Google Patents

Abstract

The invention relates to a pulse technique and can be used in control devices, control, synchronization by precision phase change of the signal. The aim of the invention is to improve the accuracy of the digital phase shifter. Phaser contains wired generator 1, line 2 delay, for example, with

Description

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by taps, first group of elements 3.1-3.N, element RSHI 4, RS trigger 5, elements 6, 7 and 16, ring shift register 8, control block 9, -N additional groups of elements 10,1-10 .N, adder 11, digital-analog converter 12, filter 13, N formers 14.1-14.N, shift generator 15, tires 17.1-17.2 up. Sign and output bus 18 phase shifter. The operation of block 9 with a negative phase shift occurs

similar to his work with a positive phase shift. At the same time, with RS buses 17.1- and 17.2, the RS-flip-flop 5 is set to state 1. In case of negative shift, the order of transition from one form of the step signal at the output of the digital analogue converter 12 to the positive one is shifted. form, i.e. a corresponding phase shift occurs. 1 hp f-ly, 5 ill.

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The invention relates to a pulse technique and is intended for monitoring, control and synchronization devices by precisely varying the phase of the signal.

The aim of the invention is to increase the accuracy of the digital phase shifter. FIG. Figure 1 shows the digital phase shifter; in fig. 2 is a structural diagram of one of the N drivers; in fig. 3 is a block diagram of the former switch; in fig. 4 is a block diagram of the control unit; in fig. 5, - timing diagrams of the phase shifter.

The digital phase shifter (Fig. 1) contains the master oscillator 1, the delay line 2, for example, with six taps, the first group of elements AND 3.1-3.N, the element OR 4, the RS flip-flop 5, the first and second elements AND 6 and 7, ring shift register 8, control block 9, N additional groups of elements AND 10.1-10.N, adder 11, digital analog converter 12, filter 13, N drivers 14.1-14.N, generator 15 of shifts and third element 16 of bus 17.1 , 17.2 controls Sign and output bus 18.

The S and R inputs of the RS flip-flop 5, respectively, are connected to buses 17.1, 17.2, and the direct and inverse outputs thereof, respectively, with the first inputs of the And 6 and 7 elements, the second inputs of which are combined and connected to the output of the OR 4 element, and the outputs respectively connected to the inputs of the forward and reverse shift of the register 8. The first inputs of the elements And 3.i, 10. (2i-1),

10.2i in each i-th of the N first and additional groups of elements I are combined and connected to the i-th branch of the line 2 delays, the second inputs of each element I 3.1,)

10.2i are connected to the bit outputs of the corresponding shaper 14.1, and the outputs of the AND 3.1-3.N, 10.1-10.2 elements are connected to the bits of the corresponding operands of the adder 11. The outputs of the adder 11 are connected to the inputs of the digital-to-analog converter 12, the output of which is through a filter 13 is connected to the output bus

18 phase shifter. The outputs of register 8 are connected to informational inputs of drivers 14.1-14.N, the clock inputs of which are combined and connected to the output of element I 16 and to the counting input of block 9, the control inputs of drivers 14.1-14.N are combined and connected to the direct output RS- trigger 5, and transfer and borrow transfer vygods are connected to the inputs of the element OR 4. The inputs of the AND 16 element are respectively connected to the codes of the generator 15 and block 9.

Each of the N drivers 14.1 codes of the amplitudes of the pulses (figure 2) contains the elements And 19 and 20, the switch 21 and the reversible counter 22, the outputs of bits, transfer and borrow transfer of which are respectively connected to the outputs of bits, transfer

and loan transfer shaper 14.1. The first inputs of the elements And 19 and 20, respectively, are connected to the first and second information inputs of the imaging unit 14.1, their second inputs are

are connected to the clock input of the racer 14.i, and the outputs are respectively connected to the first and second information inputs of the switch 21, the control input of the switch 21 is connected to the control input of the shaper 14.1, and the direct and reverse counts to the direct inputs Mobile and reverse counting counter 22,

The switch 21 (FIG. 3) contains elements AND 23-26, elements OR 27 and 28 and element NOT 29, First inputs of elements AND 23, 25 and elements 24, 26 are pairwise combined and respectively connected to the first and second information inputs of switch 21 , the second inputs of the AND 24, 25 elements are combined and connected directly to the control input of the switch 21 and the NO 29 element through the second inputs of the AND 23, 26 elements, And 23, 24 element outputs through the OR 27 element to the output of the forward counting switch 21 , and the outputs of the elements And 25, 26 through the element OR 28 are connected to the output reverse switch accounts 21

The control block 9 (FIG. 4) contains a counter 30 and Py.5-flip-flop 31, S is the RS flip-flop input 31 connected to the input of the correction input (not shown in FIG. 1), the R input to the output of the counter 30, and the output is with the output of block 9, the counting input of the counter 30 is connected to the counting input of the block 9, and the inputs of the parallel recording of information of the counter 30 (not shown in fig. 1) are connected to the inputs of the record of the number of shift samples.

Fig. 5 shows time diagrams of the device operation: a-e, respectively, at the 1-6th taps of the delay line 2; LC - step signal at the output of the digital-to-analog converter 12 at different values of the initial phase of the first harmonic of the given step signal.

The device works as follows.

After switching on from the inputs, the code of the initial state and the write pulse (FIG. 1) in the register 8 for the first bit are written logical 1, and for the rest - O,

In this example implementation of the device with N-6, codes 22, for example, drivers 14.1 and 14.2, are written to counter 22, for example,

0

five

0

five

0

five

0

five

0

five

The maximum binary numbers for these counters. Since in this example the counter :: 22 is three-bit (the number of counters must be equal to the number of elements AND 3.1, 10.J, +1) connected to one of the taps of the delay line 2, binary numbers 111 should be written in them , The counters 22 of the rest of the formers are recorded 000, the installation of the indicated states of the counters is done, for example, from the inputs of Const. 111, Const. 000 (in FIG. 2, these inputs are not shown),

To set the initial, zero state of the RS flip-flop 31 of block 9 into the counter 30 of the block 9 from the input The record of the number of shift samples (Fig. 4) records the maximum binary number for this counter. In this case, at the output of the counter 30, an overflow pulse occurs, setting the RS flip-flop 31 to O,

Pulses with a duty cycle 2 from the output of the generator 1 are received from the taps of the delay line 2 (FIGS. 5a-e) to the inputs of the AND 3.1-1.6, 10.1-10.12 elements, and only the 3.1 elements, 10.1, 10.2 and 3.2, 10.3, 10.4, the second inputs of which are connected to the outputs of the bits of the counters 22 drivers 14.1-14.2, are open, the remaining elements And 10.1 are closed. Thus, during the presence of a pulse at the first tap of the delay line 2, logical 1 is received at the inputs of all three bits of the first operand of the adder 11, which corresponds to the number 7, and during the presence of a pulse at the second tap of the line 2, logical 1 enters the inputs of all the three bits of the second operand of the adder 11. The inputs of all the other operands of the adder 11 receive logical O, which corresponds to the number O,

At the outputs of the adder 11, periodically the sum of the numbers at its inputs is converted by the digital-analog converter 12 into an analog signal, the level of which (FIG. 5g) in accordance with the sum value at the outputs of the adders 11 is equal to 7 in the intervals and is equal to 14 in the interval equal to 0 in the interval ©, e.

Let us take the value of the initial phase of the first harmonic of the stepwise signal formed in this way (fig, 5g) as zero. The first harmonic with zero in this case

the value of the initial phase is allocated by the filter 13 and is fed to the bus 18.

Whether the phase shift in the counter 30 of block 9 is recorded, the required number of shift offsets in the inverse code. From the bus 17.1 and 17.2 marks, the RS flip-flop 5 is set to the state, for example 1, corresponding to the plus sign

input phase shift. On the S-input, an example equal to 111, which corresponds to the RS-flip-flop 31 of block 9 (FIG. 4) is a tenth number 7. This leads to the input. The input of the shift samples is used to change the shape of the step-signal sigic 1. This trigger is The output at the digital-analog output goes to 1 and opens element I 16, the former 12, and therefore, which begins to transmit pulses r to change its initial phase from the output of the generator 15 to its output.

From the output of the element And 16 shift pulses arrive at the clock inputs of the formers 14.1-14.6. Insofar as

howl harmonics. So, at the state 111 of the counter 22 of the former 14.3 to the input of the specified operand of the adder 11 during the presence of a pulse on

in the first discharge of register 8, 20 is recorded on the third lateral of the delay line 2 to 1

and in the others - O, then the number 111 appears and the waveform at the output of the digital-to-analog converter 12 corresponds to that shown in FIG. 5 and. The first harmonic of the decree of the 25th signal has an initial phase of 30 °.

The element AND 19 of only one former is open. 14.3. Through this open element, the shift pulses are fed to the first information input of the switch 21 of the generator 14.3, to the control input of which from the direct output of the RS flip-flop 5 a logical O is received, which determines the sign of the input phase shift. Depending on the potential value at the output of the RS flip-flop 5, the switches 21 of the formers 14.1-14.6 connect pulses from their first and second information inputs, respectively

the number 111 is stepped and the waveform at the output of the digital-to-analog converter 12 corresponds to that shown in FIG. 5 and. In this case, the first harmonic of the indicated signal has an initial phase equal to 30 °.

thirty

During the presence of the next shift pulse (which is chosen negative in this device implementation), a pulse is formed at the output P of the transfer of counter 22 of the former 14.3. This pulse through the element OR 4 and the element I 6 opened from the direct output of the RS flip-flop 5 and 6, on the forward or reverse counting inputs .35, enters the direct shift input of the counters 22 of the same drivers. country 8. Recorded in the register 8 logi- In this case, the pulses arrive at the input of the direct count of the counter 22 of the driver 14.3.

After the arrival of the first shift pulse from the output of block 9, the counter 22 of the former 14.3 enters the state corresponding to the number 001 and, at its bits, logical 1, the lowermost bit of the former 14.3 removes the AND 3.3 element.

During the presence of a pulse in the third branch of the delay line 2 (Fig. 5b), a logical 1 arrives at the input of the low-order bit of another operand of the adder 11. At the output of the digital-to-analog converter 12, a periodic signal appears, amplitude

40

Now, the next shift pulse from the output of block 9 passes to the input of the counting counter 22 of the driver 14.1 through the open logical 1 from the second bit of the register B element 20 and the switch 21 of the same driver. Thanks to this, the counter 22 of the driver 14.1 goes from state 111 to 1VO, which corresponds to a decimal number 6. At the output of the digital-to-analog converter 12, a step signal is generated (Fig. 5kT. The phase shift of the first harmonic of this signal now exceeds 30,

which corresponds to the shown

Upon further arrival of the shift pulses, a decrease occurs in FIG. 5z. The first harmonic of the indicated 55 code at the outputs of the bits of the counter signal has a new value for 22 shaper 14.1, the accompanying phase, i.e. a shift occurs by a further phase shift of the per-phase. your harmonic of the step signal

25936

The following phase pulses transfer the counter 22 of the former 14.3 to its successive states, and the value of the number arriving at the output of the corresponding operand of the adder 11 during the presence of a pulse on the third branch of the delay line 2 increases to the maximum value in this

example equal to 111, which corresponds to the decimal number 7. This leads to a change in the shape of the stepped signal at the output of the digital-to-analog converter 12, and consequently, to a change in the initial phase of its transducer

howl harmonics. So, at the state 111 of the counter 22 of the former 14.3 to the input of the specified operand of the adder 11 during the presence of a pulse on

The third branch of the delay line 2 receives the number 111, and the waveform at the output of the digital-to-analog converter 12 corresponds to that shown in FIG. 5 and. In this case, the first harmonic of the indicated signal has an initial phase equal to 30 °.

During the presence of the next shift pulse (which is chosen negative in this device implementation), a pulse is formed at the output P of the transfer of counter 22 of the former 14.3. This pulse through the element OR 4 and open from the direct output of the RS flip-flop 5, the element AND 6–5 goes to the input of the direct shift of the register 8. Recorded in register 8 is the

0

Now, the next shift pulse from the output of block 9 passes to the input of the counting counter 22 of the driver 14.1 through the open logical 1 from the second bit of the register B element 20 and the switch 21 of the same driver. Thanks to this, the counter 22 of the driver 14.1 passes from the state 111 to the state 1VO, which corresponds to the decimal number 6. The output of the digital-to-analog converter 12 forms a step signal (Fig. 5kT. The phase shift of the first harmonic of this signal now exceeds 30,

output digital-to-analog converter 12 (Fig. 5l).

As soon as the code of said counter 22 decreases to 000, similarly to the overflow pulse, a pulse W is formed, a transfer loan, which, just like the transfer pulse, shifts the logical 1 from the second to the next, the third bit of the register 8. Now, with each successive shift pulse, counter code 22 of driver 14.4 is increased, and, starting from this moment, the operation of the device is equivalent to that previously discussed, only opening elements AND 19, 20 of drivers 14.1-14.6 change in a certain order. During the finding of logical 1, in the latter, in this example, the twelfth bit of register 8, with each counting pulse, counter code 22 of generator 14.6 decreases from 111 through 110 and so on to 001.

After the counter 22 of the driver 14.6 is in its next, zero state, a pulse is formed at its output W of the transfer loan, which through the elements OR 4 and AND 6 enters the input of the forward register shift 8. Because register 8 is selected ring, there is a transition of logical 1 from its last bit to the first. Now the state of the device is no different from its state after turning on the device, the form of the step signal at the output of the digital-to-analog converter 12 is identical to FIG. 5g but since then there has been a shift of the initial phase by 360.

With continued receipt of the shift pulse from the output of block 9, the operation of the device is fully repeated.

Each shift pulse from the output of the element AND 16 except the clock inputs of the formers 14.i enters the counting input of the counter 30 of block 9, increasing the contents of the counter by one. After the counter overflows, a pulse is generated at its output, returning the RS flip-flop 31 to the state O Element II 16 is closed by a logical O from the output of this RS flip-flop, and the further arrival of pulses on

shapers 14.1 terminate. Meanwhile, the clock inputs of which are combined provide a phase shift of a predetermined number of samples.

The operation of unit 9 during phase shift to minus occurs similarly to its carbonones and is connected to the output of the third element AND and to the counting input of the control unit, the control inputs of the N drivers are combined and connected

five

0

five

during phase shift in plus, the RS-flip-flop 5 is set to state 1 from tires 17.1, 17.2. When shifting to minus, the reverse shift from plus to plus shift from one form of the step signal at the digital-to-analog output is provided Converter 12 to its other form, i.e. a corresponding phase shift occurs.

Claims (2)

Invention Formula 1 {A digital phase shifter containing a master oscillator whose output is connected to the first inputs of the first group of AND elements, the OR element, the RS flip-flop, the first and second And elements, the ring shift register and the control unit, R- through the corresponding taps of the delay line with N taps. and the S inputs of the RS flip-flop are connected to the control buses, and the forward and inverse outputs of the RS flip-flop are respectively connected to the first inputs of the first and second And elements, the outputs of which are connected respectively to the forward and reverse shift inputs of the ring register the shift element, the output of the element OR is connected to the second input of the second element I, which is the reason that, in order to improve the accuracy, N additional groups of elements I, sum 5 matrix, digital-analog converter, filter , N drivers, shift generator and the third element AND, the first inputs in each additional group of elements AND are combined and connected to the corresponding taps of the delay line, the second inputs of the additional groups of elements And and the first group of elements And are connected to the bit outputs N5 shapers, and the outputs of all groups of elements I are connected to the inputs of the bits of the adder, respectively, the outputs of which are connected to the inputs of a digital-analog converter, the output of which is connected through a filter to the output bus of the phase shifter, the outputs of the ring shift register are connected to the corresponding information inputs N of the form not connected to the output of the third element I and to the counting input of the control unit; the control inputs of the N drivers are combined and connected; The transfer and transfer transfer terminals are connected to the inputs of the OR element, the output of which is connected to the second input of the first element AND, the first and second inputs of the third element AND are connected to the outputs of the shift generator and the control unit, respectively. 2. Phaser according to claim 1, characterized in that each of the N drivers contains two AND elements, a switch and a reversible counter, the overflow and overflow credit of which are respectively connected to the outputs Perb InterPerby Inspection Shot Cure blot the second information b) sod FIG. J 0 five ten the overflow and transfer bits of the imager, the first inputs of the AND elements are respectively connected to the first and second information inputs of the imager, their second inputs are combined and connected to the clock input of the imager, and the outputs are respectively connected to the first and second information inputs of the switch, the control input of which is connected with the control input of the driver, and the outputs of the forward and reverse counting, respectively, with the inputs of the forward and reverse counting of the reversible counter. FIG. 2 Direct output about revolving account loop  about discrete input coftuza Editor N. Gulko W, ut.f Compiler A, Perfiliev Tehred M.DidykKorrektor O. Kundrik FIG. four W, ut.f