SU1654973A1 - Shift-to-code converter - Google Patents

Abstract

The invention relates to automation and computing and can be used to measure displacement in CNC machines. To the converter to increase its accuracy by increasing the resolution, which contains ACS, a bandpass amplifier, a phase-sensitive pulse driver, four reversible counters, a trigger, two And elements, a decoder, PWM, a reference frequency generator, a frequency divider, two elements delays, a fifth reversible counter, two IL-NES elements, a pulse distributor, and a new implementation, PWM, are introduced. 1 h. item f-ly, 6 ill.

Description

The invention relates to automation and computing and can be used to measure displacement in CNC machines.

The purpose of the invention is to improve the accuracy of the converter by increasing the resolution of the converter.

FIG. 1 shows a converter block diagram; in fig. 2 is a schematic diagram of a pulse distributor; in fig. 3 - timing diagrams explaining the operation of the pulse distributor; in fig. 4 is a schematic diagram of a pulse width modulator; in fig. 5 and 6 are diagrams explaining the operation of the pulse-width modulator.

The displacement transducer to the code contains a sine-cosine sensor 1 (ACS), a band-pass amplifier 2, a phase-sensitive shaper of 3 pulses, a reversible counter 4, a trigger 5, a reversible counter 6, elements I 7 and 8, a decoder 9, elements OR-HE 10 and 11 , reversible counter 12, pulse distributor 13, reversible counters 14 and 15, pulse-width modulator 16, reference frequency pulse generator 17, frequency divider 18, delay elements 19 and 20.

The distributor 13 pulses (Fig. 2) contains a counter 21 and a decoder 22.

Pulse width modulator 16 contains reversible counters 23-26, triggers 27 and 28, element 2И-НЕ 29, elements NOT 30-32, multiplexers 33 and 34, triggers 35 and 36, elements EXCLUSIVE OR 37 and 38, elements 39 and 40, AND-NOT elements 41-44, NOT elements 45 and 46.

The Converter operates as follows.

Reversible counters 14 and 15 store numbers, the sum of which is equal to the absolute intra-step displacement of the inductor head relative to the ruler, forming the ACS 1 and determines the width of the voltage pulses produced by the pulse-width modulator 16 and fed into the sinus and cosine windings sensor 1.

Changing this amount causes a change in the width of the sine and cosine sig (L

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with

with

power supply sensor 1. In a statically consistent position, these signals are such that at the output of sensor 1, the magnitude of the error voltage is close to zero. When moving the movable part of the sensor 1, an error signal appears at its output. The bandpass amplifier 2 amplifies the error signal and extracts the first harmonic of this signal. The amplified error signal is fed to the input of a phase-sensitive driver 3 pulses. The signal from one output of delay element 15 is shifted by of the period from its beginning and is at the maximum of the error signal. If the magnitude of the error is greater than the threshold of the phase-sensitive generator of 3 pulses, then one of its outputs, depending on the phase of the error, produces a pulse. Thus, with positive movement of the movable part of sensor 1, a positive mismatch occurs and the phase-sensitive shaper 3 pulses emit pulses that through the OR-HE element 10 and the decoder 22 arrive at the addition input of either a reversible counter 14 or a reversible counter 15 (depending on the state of the decoder 22) in turn. The reversible counter 21 controls the state of the output signals D and F of the decoder 22 in such a way that the numbers stored in the reverse

The phase-sensitive shaper 3 generates pulses that are fed to the input of the subtraction of the reversible counter 4, and through the element OR-HE 11 and the dispenser 13 pulses are alternately fed to the inputs of the reversing counters 14 and 15.

When the state of the high-order bits of the reversible counter 4 becomes zero, and the sum of the numbers stored in the reversible counters 14 and 15 corresponds to the 10th position of sensor 1, the error signal at the output of sensor 1 will be zero.

If the sensor 1 moves negatively, the overflow pulse of the reversible counter 4 sets the trigger 5 to "O. The signal from the output of the delay element 20, the number from the reversible counter 4 is entered into the reversible counter 6, the decoder 9 gives permission for the passage of the pulses of the generator 17 through the element AND 8, which through the element OR-NOT 11 and the distributor 20 of the pulses are alternately fed to the subtraction inputs reversible counters 14 and 15 and to the summing input of the reversible counter 6. When the state of the reversible counter 6 becomes zero, the decoder 9 will prevent the passage of pulses through elements 7 and 8. Thus, in the higher bits of the reversing the counter 4 will be recorded the number corresponding to the speed of movement of the sensor 1, and in the reversible counters 14 and 15 in each period T

15

25

counters 14 and 15, differ by no more than n; numbers will be recorded, the sum of which corresponds to the current time point corresponds to the current position of sensor 1.

per unit (Fig. 3).

In addition, these pulses are fed to the summing counting input of the reversible counter 12, increasing the number contained in it.

The signal from the output of the delay element 20 (which is shifted by 1-2 T from the beginning of the period) overwrites the number from the higher bits of the reversible counter 4 to the reversible counter 6.

If this number is not equal to zero, the decoder 9 generates a single signal that permits the passage of pulses from the generator 17 pulses through the AND 7 element in the single state of the trigger 5. The pulses from the output of the AND 7 element through the OR-NOT 10 element and the distributor 13 are received alternately on The summing counting inputs of the reversible counters 14 and 15. At the same time, the pulses from the output of the element And 7 arrive at the input of the subtraction of the reversible counter 6. When the number in the reversing counter 6 becomes zero, the decoder 9 prohibits the passage of black pulses Without elements 7 and 8. If the number of pulses arriving each period corresponds to the amount of movement of sensor 1 over a period, then at the output of sensor 1, the error signal is zero. When the positive speed of movement of sensor 1 decreases or when negative movement occurs, a negative mismatch occurs.

The pulse width modulator 16 operates as follows. At the moment when the overflow pulse arrives from the output of the frequency divider 18, the write circuit consisting of 35 elements of the HE 30, 2I-HE 29, D-flip-flops 27 and 28 generates a pulse that overwrites the number (except for the least significant bit) , stored in the counter 14, in the counters 25 and 26. The state of the low-order bit is fixed at the same time in the trigger 36, and the state of the low-order bit of the reversible counter 15 - in the trigger 35.

In the next half-cycle clock frequency, the number (with the exception of the smallest 45 p yes), stored in counter 15, is recorded in counters 23 and 24. At the counting inputs of counters 23 and 25, the clock frequency is supplied directly from the output of the HE element 30 (Fig. 5 ) to the counting inputs of counters 24 and 26 through the elements HE 32 and 31 (Fig. 5).

The multiplexers 33 and 34, controlled by the lower bits of counters 15 and 14, switch 2 higher bits of counters 23-26 in such a way that when sensor 1 is moved one discrete, the output signals of multiplexers 33 and 34 are shifted relative to each other by half-cycle clock frequencies, which ultimately leads to a change in the same

50

55

The phase-sensitive shaper 3 generates pulses that are fed to the input of the subtraction of the reversible counter 4, and through the element OR-HE 11 and the dispenser 13 pulses are alternately fed to the inputs of the reversing counters 14 and 15.

When the state of the high-order bits of the reversible counter 4 becomes zero, and the sum of the numbers stored in the reversible counters 14 and 15 corresponds to 0 the position of sensor 1, the error signal at the output of sensor 1 will be equal to zero.

If the sensor 1 moves negatively, the overflow pulse of the reversible counter 4 sets the trigger 5 to "O. The signal from the output of the delay element 20, the number from the reversible counter 4 is entered into the reversible counter 6, the decoder 9 gives permission to the pulse generator 17 through the element And 8, which through the element OR NOT 11 and the distributor 0 13 pulses are alternately fed to the subtraction inputs reversible counters 14 and 15 and to the summing input of the reversible counter 6. When the state of the reversible counter 6 becomes zero, the decoder 9 will prevent the passage of pulses through elements 7 and 8. Thus, in the higher bits of the reversing Meters withstand 4 is recorded the number corresponding to the movement velocity sensor 1 and a reversible counters 14 and 15 in each period T

five

five

n numbers will be written, the sum of which corresponds to the current position of sensor 1.

The pulse width modulator 16 operates as follows. At the moment the overflow pulse arrives from the output of the frequency divider 18, the recording circuit consisting of 5 of the elements HE 30, 2I-HE 29, D-flip-flops 27 and 28 generates a pulse, over which the number is overwritten (except for the low-order bit) , stored in the counter 14, in the counters 25 and 26. The state of the low-order bit is fixed at the same time in the trigger 36, and the state of the low-order bit of the reversible counter 15 - in the trigger 35.

In the next half period of the clock frequency, the number (with the exception of the smallest time) is stored in counters 23 and 24. At the counting inputs of counters 23 and 25, the clock frequency is fed directly from the output of the HE element 30 (Fig. 5 ) to the counting inputs of counters 24 and 26 through the elements HE 32 and 31 (Fig. 5).

The multiplexers 33 and 34, controlled by the lower bits of counters 15 and 14, switch 2 higher bits of counters 23-26 in such a way that when sensor 1 is moved one discrete, the output signals of multiplexers 33 and 34 are shifted relative to each other by half-cycle clock frequencies, which ultimately leads to a change in the same

0

five

the value of the width of the sensor power pulses

The coincidence circuit, built on elements 37-42, produces impulses of a sinusoidal sensor winding, the coincidence circuit, built on elements 45, 46, 43 and 44, produces impulses of a cosinusoidal winding of the sensor.

Consider the operation of a coincidence circuit (elements 37-46). Let the absolute displacement of the head of the inductosin relative to the ruler is zero. In this case, the key 43 in the first half-period is open to receive the current, and in the second - to the transmission, and the key 44 - vice versa (Fig. 6). The amplitude of the current flowing through the cosine winding is maximum. The keys 41 and 42 for the entire period work on the transfer, so the current in the sinus winding does not leak. When the head is displaced relative to the ruler in the sensor I, the amplitude of the currents flowing through the cosine and sine windings varies according to a periodic law.

Thus, the change in the width of the power pulses when moving by one sampling occurs due to the shift of one of the edges of the power pulses by a half-cycle of the clock frequency, whereas with a known converter, due to the shift of one of the edges of the power pulses by the period of the clock frequency. In this case, the resolution of the converter, as compared with the known one, is increased by 2 times without reducing the carrier frequency of the power supply of the sensor, which makes it possible to increase the measurement accuracy by 2 times as compared with the known converter.

Claims (2)

1. A displacement transducer into a code containing a sine-cosine sensor, the output of which is connected to the first input of a phase-sensitive pulse generator through a band-pass amplifier, the second input of which is connected to one output of the first delay element, and the outputs connected to the corresponding inputs of the first reversible counter, the first and the second outputs of which through a trigger are connected to the first inputs of the first and second elements I, the output of the reference frequency generator is connected to the second inputs of the first and second ele And, the first input of the pulse-width modulator and the input of a frequency divider, the output of which is connected to the inputs of the first and second delay elements, the output of the second delay element is connected to the control input of the second reversible counter, the installation inputs of which are connected to the outputs of the higher-order first bits reversible counter, and the outputs through the decoder connected to the third inputs of the first and second elements And the outputs of which are connected to the counting inputs of the second reversing account five The output of the frequency divider is connected to the second input of a pulse-width modulator, the outputs of which are connected to the inputs of a sine-cosine sensor, the third reversing counter, the inputs and outputs of which are the outputs of the converter, the fourth reversing counter, the output of which is connected to the third input of a width pulse modulator, characterized in that, in order to improve the accuracy of the converter, two elements of IL AND –NE are introduced into it, a fifth reversible counter, a pulse distributor, and a pulse-width modulator contains Um, four reversible counters, four triggers, seven NOT elements, two multiplexers, two elements EXCLUSIVE NOR OR, five AND-NOT elements, informational D inputs of the first trigger and the first and second reversible modulator counters are combined and are the third input of the modulator informational D inputs 0 of the second trigger and the third and fourth reversible modulator counters are combined and are the fourth modulator input, the R-inputs of the modulator reversible counters are connected to the common bus, the C-inputs of the first and second triggers and the first and second reversible modulator counters are combined and its first input, the input of the first element is NOT the second input of the modulator, and the output is connected to one input of the first NAND element, to the counting addition and subtraction inputs of the third and first reversible counters, respectively. The gateway directly and through the second and third elements NOT is with the counting inputs of the addition and subtraction of the fourth and second reversible modulator counters, the output of the first AND-NE element is connected to the C inputs of the third and fourth reversing modulator counters and to the C input of the third trigger, the output of which is connected to the R input of the fourth trigger, the output of which is connected to 0 by another input of the first NAND element, the C input of the fourth trigger is connected to the R input of the third trigger and to the C input of the second reversible modulator counter, the control inputs of the first and second multiplexers are connected to the outputs of the first and second triggers, respectively, two high the bits of the first and second reversible counters, respectively, are pairwise connected to the first and second groups of information inputs of the first multiplexer; two older bits of the third and fourth reversible counters, respectively, are pairwise connected Inen with the first and second groups of inputs of the second multiplexer, the outputs of the first and second multiplexers are connected to the inputs of the first and second 5 elements EXCLUSIVE OR, respectively, the outputs of which are directly connected to one input of the second and third elements AND-NOT, respectively, and through the fourth and fifth elements are NOT - with 0 five five 0 sixteen  7 other inputs of the third and second IS-NE elements, respectively, whose outputs are one output of a pulse-width modulator, the first outputs of the first and second multiplexers are directly connected to one inputs of the fourth and fifth AND-NOT elements, respectively, and through the sixth and seventh the elements are NOT with other inputs of the fifth and four torus elements AND-NOT, respectively, whose outputs are other outputs of the modulator, one inputs of the elements OR are NOT connected to the corresponding outputs of the phase-sensitive formati l pulses, others - with the outputs of the corresponding elements And, and the outputs - with the corresponding inputs of the third reversible counter and pulse distributor, the outputs of which are pairwise connected with the corresponding 0 five eight by the inputs of the fourth and fifth reversible counters, the output of the fifth reversible counter is connected to the fourth input of the pulse-width modulator. 2. The converter according to claim 1, characterized in that the pulse distributor comprises a counter and a decoder, the increment and decrement inputs of the counter are the inputs of the distributor and are connected to the first and second inputs of the decoder, the first control input of which is connected to the output of the lower-order counter and the second control input, the decoder sampling enable input and the counter reset input are connected to a common bus; the first and second outputs of the first and second groups of outputs of the decoder are pairwise outputs of the pulse distributor. THEIR u fi 2 Exit EL Exit behind. HI 32.31 Vyh.el.ZZ Vsh. email 34 Out ep. 33 Exit.el.34 iS i ° - / 2. 3 45 6 f 8 -Y SO U / & 4 l i wfouod I ZUM L  TLGTs- J LTLJT 5 LTLTU