SU1305661A1 - Device for shifting information - Google Patents

Abstract

The invention relates to computing and can be used to shift in processing units of an average-capacity computer. The purpose of the invention is to increase speed. This is achieved by the fact that the device containing the shift registers t, 2, the mode setting node 7 and the synchronization node 8, contains counters 3, 4 and the AND-IDN elements 5,6 with corresponding links. 4 il. 1 tab.

Description

eleven

The invention relates to computing and can be used in processing blocks of average-capacity computers.

The purpose of the invention is to increase speed.

FIG. 1 shows a diagram of an apparatus for shifting information; in fig. 2 is a diagram of the synchronization node; in fig. 3 is a schematic diagram of a mode setting node; 4 - time diagram of the device.

The device for shifting information (Fig. 1) contains the first shift register 1, the second shift register 2, the first counter 3, the second counter 4, the first AND-OR element 5, the second AND-OR element 6, the task node 7

bench, node 8 synchronization, input 9

device setup, input 10, the device shifts number, device data input 11, device start input 12, device shift direction input 13, device sync input 14, device result output 15, device operation end output 16, node 8 outputs 17-21 synchronization, the outputs 22 and 23 of the node 7 setting the mode, the inputs 24, and 25 of the node 8 synchronization.

The node 8 synchronization (Fig. 2) contains the elements OR 26-29, elements AND 30-33 and the element 34 of the delay.

The mode setting node 7 (FIG. 3) contains an HE element 35, the AND 3 and 37 elements and the OR elements 38-42.

The first shift register 1 is designed to organize shifts by four bits. The left shift register 1 contains n bits (n is a multiple of four) and consists of four independent shift registers, each of which has a bit width n / 4. All four registers have common control and general synchronization.

If the input information is split into n / 4 four-digit digits, the like digits of each digit are entered in their n / 4-bit register. The first n / 4-bit register puts bits 1, 5, 9n-3, during

the second n / 4-bit register - bits 2,6,10, ..., p-2; the third n / 4-bit register - bits 3, 7, 11, .., p-1, in the fourth n / 4-bit register - bits 4, 8, 12, ..., p.

On a separate clock pulse, each of the n / 4-bit registers was

five

0

12

there is a shift in the information stored therein by one bit B, the bits being released are shifted by zeros.

The second shift register 2 is designed to form the final shift result, it contains n bits (n is a multiple of four). This register allows the shift to RCD. When the first shift register 1 is shifted by four bits, the second shift register 2 operates in the recording mode and after each shift resets the information shifted by four bits in the first shift register 1. The transfer of information from the first shift register 1 to the second shift register 2 is carried out in accordance with the table.

If the shift to four bits is completed, one shift needs to be made, the second shift register 2 from the overwrite mode goes into the shift mode and performs the missing shift.

II

III

1 2 3

p / 4

one

2

3

p / 4

one

2

3

p / 4

one

5 9 p-3

1 5 9 p-3

Continuation of table 3

Iziei

Shifts are controlled by the first and second counters 3 and 4. The first counter controls shifts by one bit. The second counter, A, controls the shifts by four bits.

The mode setting unit 7 determines the operation modes of the first and second shift registers 1 and 2. For these registers, the operation mode is determined by the state of the inputs S-, S.

The following modes of operation are available: 00 - storage, 01 - left shift, 10 - right shift, 11 - entry.

The single input state S of counters 3 and 4 determines the recording mode. If, for counters 3 and 4

set modification mode to - 1

. The device works as follows.

When a signal appears at the input 9 of the device, a single state for counters 3 and 4 is established directly. For the first shift register, the entry mode is set via the OR elements 38 and 39. For the second shift register, the next three sync pulses make the remaining shift to the left by

The entry pressure is set by the elements OR 41 and 40 under the control of an elec- tron four, at the end of the last OR 42. The falling edge of the next of them in the first and second shift sync pulse is carried out by the output registers 1 and 2 entering information into counters 3 and 4 maci is shifted to the left by 16 bits and into registers 1 and 2. The impulse is registered, and the content of the second counter 4 becomes equal to zero. In this case, the OR element 27 blocks the AND 30 element, which stops the supply of synchro- (pulses to the first shift register 1. The I.PI element 27 also blocks the AND-OR 5 element and removes the blocking of the AND-OR element 6. Non-zero state of the first counter 3 through element OR 28 permits modification of the first counter 3. Modification of the second countershift lengths in the first and second counters 3 and 4 is formed by element AND 31. An impulse of entering information into the first shift register 1 is formed by the element OR 26 controlled by element AND 31. - pho The second shift register 2 is issued with a delay in relation to the previous pulse, which is generated by the OR element 29 under control

element 26 or delay element 34.

A single value is fed to the input 13 of the device when shifting to the left, in the opposite case a shift to the right.

Consider the left shift operation for 17 bits. In this case, it is necessary to carry out four shifts on the discharge cell and one shift per discharge to the left in the device. In this case, a single signal is applied to the input 12 of the device.

Before the start of the operation, the shift at the input 13 of the device is set to 1, 4 is entered into the second counter 4, 1 is entered into the first counter 3, and the initial information is entered into the shift registers 1 and 2. Non-zero state of the second counter

4 through the OR element 27 blocks the AND-OR 6 element. This modifies the contents of the second counter 4 and prevents the contents of the first counter 3 from being modified. The OR element 27 through AND 37 and the OR elements 38 and 39 for the first shift register 1 sets the left-shift mode and for the second shift register 2, the recording mode.

Through the AND 30 element and the OR element 26, the gate of the first shift register 1 is formed by the next clock pulse and through the delay element 34 and the OR element 29 is the gate of the second shift register 2. For these gates, the first register is shifted by 4 bits to the left, and the second case is the re-memorization of the shifted information. At the same time, the content of the second counter 4 is modified to -1.

I

The next three clock pulses make the remaining left shift by

four digits, at the end of the last of them in the first and second shift registers 1 and 2 there is information that is shifted to the left by 16 bits

four digits, at the end of the last of them in the first and second shift registers 1 and 2 there is information that is shifted to the left by 16 bits

Dov, and the contents of the second counter 4 becomes zero. In this case, the OR element 27 blocks the AND 30 element, which stops the supply of synchro- (pulses to the first shift register 1. The I.PI element 27 also blocks the AND-OR 5 element and removes the blocking of the AND-OR element 6. Non-zero state of the first counter 3 through the OR element 28 allows modification of the first counter 3. Modification of the second counter 4 is blocked. Elements 38 and 39 set the mode for the first SDBig register 2, elements OR 41 and 40 set the left-shift mode.

The second shift register 2 and the gate of the first counter 3 are formed through the AND 32 element and the OR element 29 of the second sync pulse. This gate shifts left the contents of the second shift register 2 by one bit and modifies the contents of the first counter 3 by -1. Since after this modification the contents of the first counter 3 becomes equal to zero, the OR element 28 blocks the AND 32 element, which prohibits the clock pulse to the second shift register 2

The zero state of the counters 3 and 4 through the elements OR 28 and 27 and the element AND 33 determines the output at the end 16 of the operation of the sign of the completion of the shift operation. At output 15, the result is information shifted to the left by 17 bits.

Claims (1)

Invention Formula 30 And a synchronization node, the output of the fourth element OR of which is connected to the first inputs of the second group of the first and second elements AND-OR and to the synchronization input of the second shift A device for shifting information containing two shift registers, a mode setting node containing two OR elements and two AND elements, a synchronization node containing two AND elements and two OR elements, with the register input, inputs of the device mode setting bits connected to which information is connected respectively with the outputs of the third and fourth OR elements of the mode setting node, the device start input is connected to the second 40 inputs of the second group of the first and second AND-OR elements and to the first input of the third AND element of the synchronization node, the output of the fourth AND element which is the output of the end of - the bridges of the first element OR of which are connected to the device, the direct output is secondary, respectively, with the outputs of the first element OR of the synchronization node of the second and second elements AND of the syn- thetic node connected to the third input of the second grouping, direct output the second element of the first element I-IPI, whose direct output OR is connected to the input of the third element OR and inverse inputs of the first and second element 5o the output of the second element OR of the synth node AND setting mode node, the outputs of the chronization are connected respectively with those that are connected respectively with the first and fourth inputs of the second output inputs of the first and second element of the second element AND-OR, primogtov OR of the mode setting node, and the element in the setting node that, with a goal of 55 that is NOT connected to the second input of the second speed increase, it contains the AND element and with the first input of the third one there are two counters, two AND-OR elements, the OR element, the second input of which is the node for setting the datum: IM contains an element connected to the first input of the fourth cop. the third OR element and the output of the fifth eleuioHHbiM input of the first shift register, the output of which is connected to the information input of the second shift register, the output of which is the output of the device result. The synchronization input is connected to the first inputs of the first and second elements AND of the synchronization node, the synchronization node contains a delay element, the third and fourth elements are AND, the third and fourth elements of ILT-i, and the input of the number of shifts g of the device is connected to the information inputs of the first and second counters whose mode inputs are connected to the second inputs of the first and second OR elements of the task node O mode, with the second input of the second element I of the synchronization node and with the input of the initial installation of the device, the input of the shear direction of which is connected to the input of the element NOT of the 5 Dani mode node, the outputs of the first and second OR elements of which are connected respectively to the inputs of the bits of the first shear mode setting register, the synchronization input of which is connected to the output of the first OR element of the synchronization node, the inputs of the second and third OR elements of which are connected respectively to the output of the second and the first tchikov, clock inputs which are connected respectively to the outputs of the first and second elements AND-OR, the inputs of the first group of which are connected to the output of the second element 0 AND the synchronization node, the output of the fourth element OR of which is connected to the first inputs of the second group of the first and second elements AND-OR and to the synchronization input of the second shift  register, the inputs of the bits for setting the mode of which are connected respectively OR, whose inputs are connected respectively to the outputs of the first and second, OR elements, the output of the element is NOT connected to the second inputs of the first AND element and the fourth OR element; moreover, in the synchronization node, the output of the first OR element is connected to the first input of the fourth element OR, the second input of which is connected to the output of the third element AND, the first and second inputs of which are connected respectively to the second and first inputs of the first element AND, the third input of which is connected to the direct output of the second element enta OR, the inverse output of which is connected to the third input of the third element AND, and to the first input of the fourth element AND, the second input of which is connected to the inverse output of the third element OR, the direct output of which is connected to the fourth input of the third element I. Fy.g Fig.Z Fy