SU1164886A1 - Number-to-pulse-width code converter - Google Patents

Abstract

1 .COD-PWM CONVERTER containing two OR elements, four AND elements, the first register whose information inputs are connected to the corresponding first code buses, the recording input to the output of the second RSHI element and the input of the delay unit, and the sign output to the first inputs the second and fourth elements And through the inverter to the first inputs of the first and third elements And, and a controlled pulse generator, the first input of which and the first input of the first element SH are connected to the output of the initial reset unit, the second input is. with the Start bus and the first input of the second SLI element, and the first output - with the second inputs of the first and second elements AND, the outputs of which are respectively connected to the first and second inputs of the reversible counter, the third input of which is connected to the output of the delay unit and the C input of the first G- the trigger, the E-input of which is connected to the bus of the permitting level, the R-input to the output of the first CMM element, and the output to the second inputs of the third and fourth And elements, the outputs of which are respectively connected to the output wide-. HaMii, characterized in that, in order to increase reliability and expand functionality, a frequency divider is introduced in it, the first and second inputs of which are connected respectively to the second output of the controlled pulse generator and Start bus, and the output to the second input of the second element OR , while the third and fourth inputs of the fixed pulse generator are connected respectively to the output of the second OR element and the third input (L of the reversible counter, whose inputs are respectively connected with the discharge outputs of the first register, and the output is connected to the second input of the first element OR, and the fifth inputs of the controlled pulse generator are respectively connected to the second c-bus. 2. The converter according to claim 1, about 4 00 00 Odl and ch yu-y and with the fact that the variable pulse generator is made on a reference geyrator, pulse counter, the fifth and sixth AND elements, the second register and the second D flip-flop, the R and C inputs of which are connected respectively to the first and second control inputs pulse generator. D-INPUT - to the bus of the resolution level, and the output - to the first inputs of the fifth and sixth elements. I. the outputs of which are respectively connected with the first and second outputs of the controlled pulse generator, the third and fourth inputs of which

Description

Go, respectively, are connected to the input of the second register and the input of the pulse counter, and the fifth inputs are connected to the corresponding information inputs of the second register, the outputs of which are connected

to the corresponding information inputs of the pulse counter, the output of which is connected to. the second input of the fifth element And, and the counting input with the output of the reference generator and the second input of the sixth element I.

The invention relates to automation and can be used in digital control systems for positional electric drives of industrial robots, machine tools with numerical control, etc. The known converter is a PWM code containing a pulse generator, the first input of which is connected to the Start bus, and the first output to the first input of the counter, a register for D-triggers, the output of the sign charge of which is connected to the input of the element NOT and to the first input of the first element And, output, the element is NOT connected to the first input of the second element, AND, I-flip-flop, comparator unit and block 2I-OR., the first input of the generator of pulses is connected respectively to the second input of the count, C-inputs D-trigger register and the first input of the second element And, block 2 I-Ш111, the output of which is connected to the C-input of the D-flip-flop, D-INPUT of which is connected to the first output of the comparison unit, the second output of which is connected to the first input of the first element AND of the 2IILI unit, the second inputs of which are connected to the second output of the pulse generator the second input of the last is connected to the output of the B-flip-flop and with the second and the inputs of the first and second elements AND, the code inputs of the register are connected to the code buses, the outputs of the counter and the register are connected to the corresponding inputs of the comparison block C. The disadvantages of this converter are from the possibility of adjusting the steepness of the static characteristic, as well as the need to present the input information in the forward code. The closest to the invention to the technical nature is the converter code - PWM, comprising a generator, two WL elements, four AND elements, the first register, whose information inputs are connected to the corresponding first code buses, the write input to the output of the second element and the input of the delay unit and the sign output to the first inputs of the second and fourth elements I, and through the inverter to the first inputs of the first and third elements I, and a controlled pulse generator, the first input of which is connected to the first input of the first element OR and the output of the initial reset unit, the second input is with the Start bus and the first input of the second element OR, and the first output is with the second inputs of the first and second AND elements, the outputs of which are connected to the first and second inputs of the reversible counter, respectively, the third input of which is connected to the output of the delay unit and the C input of the nepi 2) trigger, the D input of which is connected to the resolution bus, the R input to the output of the first element OR, and the output to the second inputs of the third and fourth elements. And the outputs of which are respectively connected to you input buses., wherein the bit outputs of the first register are respectively connected to the first inputs of the comparison unit, the output of which is connected to the second input of the first OR element, and the second inputs to the corresponding outputs of the reversing counter, the third input of which is connected to the reset input of the pulse counter, counting the input of which is connected to the first output of the controlled pulse generator, and the information inputs to the corresponding outputs of the second register, whose recording input is connected to the output of the second element S1I, and nformatsionnye inputs - with wo sponding to the second code C2L tires This converter static characteristic steepness oppede- L by the expression K | D2 (and controlled by varying the Ag, which is equivalent to the repetition period of change of steering momenta Those T (2. - A I) However, this limits the range of regulation k, since decreasing k breaks the condition of the continuity of the motor current. The system with an adjustable frequency of control pulses has low reliability due to the possibility of electromechanical resonance in it at the subharmonic frequency of PWM. The reliability of the known device is also low due to the presence of a comparison unit, the complexity of which increases with increasing error code depth. Thus, the disadvantages of the known converter are limited scope due to the small range of slope variation and low reliability due to the possibility of electromechanical resonance at the subharmonic PWM frequency. The purpose of the invention is to increase reliability and expand functional capabilities. The goal is achieved by the fact that, in the converter, the code -, SHI contains two S1I elements, four AND elements, the first register, informational inputs of which are connected to the corresponding first code wiring, the recording input - to the output of the second OR element and the input of the delay unit, and the sign output goes to the first inputs of the second and fourth elements I and through the inverter to the first inputs of the first and third elements I and the controlled pulse generator, the first input of which and the first input of the first element of the W) are connected to the output of the initial ssr ca, the second input is with the Start bus and the first input of the second I / I element, and the first output is with the second inputs of the first and second elements And the outputs of which are connected to the first and second inputs of the reversible counter, respectively, the third input of which is connected to the output of the block delays and C-input of the first D-flip-flop, the D-input of which is connected to the resolution bus, the R-input to the output of the first OR element, and the output to the second inputs of the third and fourth And elements, the outputs of which are respectively p. with output tires, additionally enter The frequency divider, the first and second inputs of which are connected, is consistent with the second output of the controlled pulse generator and the Start bus, and the output is connected to the second input of the second OR element, while the third and fourth inputs of the controlled pulse generator are connected respectively to the output the second OR element and the third input of the reversible counter, the fourth inputs of which are respectively connected to the bit outputs of the first register, and the output is connected to the second input of the first OR element, and the fifth inputs are upg. equal pulse generator, respectively, are connected to the second code bus. In addition, the controlled pulse generator is made on a reference generator, a pulse counter, the fifth and sixth elements AND, the Second register and the second 3) trigger, R and Taps which are connected respectively to the first and second inputs of the controlled pulse generator, D-INPUT - to the bus of the permitting level, and the output to the first inputs of the fifth and sixth elements AND, which are respectively connected to the first and second outputs of the controlled pulse generator, the third and fourth inputs of which are respectively connected to the input of the first the second register and the write input of the pulse counter, and the fifth inputs are connected to the corresponding information inputs, the second register, the outputs of which are connected to the corresponding information inputs of the pulse counter, the output of which is connected to the second input of the fifth element, and the counting input to the reference output generator and the second input of the sixth element I.. FIG. a structural electrical converter circuit code - BAT} is shown in FIG. 2 — controlled pulse generator, option. Converter code g-SHIM contains the first register 1, the reversible counter 2, the first D-trigger 3, block 4 initial reset, the first and second elements OR 5 and 6, the block 7 delay, the first 1 second, third and fourth elements And 8 - II, inverter 12, controlled generator of 13 pulses, frequency divider 14, first 15 and second 16 code buses, output buses 17, Start bus 18 and bus 19 of the enable level. The first input of the first element OR 5 is connected to the first input of the controlled generator 13 and the output of the initial reset unit 4, and to the cR input of the first D-flip-flop 3, the first inputs of the first register and 1 are connected to the corresponding first code buses 15, and the second input to the output of the second element OR 6, the sign output of the first register 1 is connected to the first inputs of the second and fourth elements. AND 9, 11 and across the inverter 12 to the first inputs of the first and third elements AND 8, .10, the first output of the controlled oscillator 13 pulses is connected through a trans and the second The elements 8 and 9, respectively, to the first and second inputs of the reversible counter 2, the third input through which the delay unit 7 is connected to the output of the second element ШШ6, the second inputs of the controlled impulse generator 13 and the second element OR 6 are connected to the Start 18 bus, С the input of the first) trigger 3 is connected via a delay unit 7 to the output of the second element OR 6, and the D input is connected to the enable level bus 19, the output of the first D flip-flop 3 is connected to the second inputs of the third and fourth elements 10, 11, outputs that are connected to the corresponding output bus 17, the first and second inputs of the divider 14 are connected respectively to the second output of the controlled generator 13 pulses and bus Start 18 and the output to the first input of the second element OR 6, the third and fourth inputs of the controlled generator 13 pulses connected respectively to the output of the second element ISH 6 and the output of the delay unit 7, the bit outputs of the first register 1 are connected to the fourth (informational) inputs of the reversible counter.2, the output is connected to the second input of the first element OR 5, the third input of the controlled generator 13 impzl s connected to respective word lines NJ. The control generator 13 comprises a reference generator 20, a second .p-flip-flop 21, a second register 22, a pulse counter 23, fifth and sixth elements AND 24, 25, and a resolution bus 26, with Ri. The C inputs of the second) -trigger are connected respectively to the first and second inputs of the controlled generator 13 pulses, and the output through the fifth element I 24 to the first output of the controlled generator 13 pulses and through the sixth element I 25 to the second output of the controlled generator 13 pulses. The output of the reference generator 20 is connected to the counting input of the counter 23. And through the sixth element I 25 to the second output of the controlled generator 13 pulses, the information inputs of the second register 22 are connected to the corresponding fifth inputs of the controlled generator 13 pulses, and the second input to the third the input of the controlled generator 13 pulses, the information inputs of the counter 23 are connected to the outputs of the second register 22, and the output with the second input of the fifth element And 24, the fourth input of the controlled generator 13. pulses connected to the input of the account ika 23, D-input of the second D-flip-flop 2 is connected to a bus 26 allowing a level divider 14 is provided to a pulse counter, the counting input of which is connected to the first input of the divider,. and the installation input to zero - to the second input of the divider. The output of the divider is the transfer output of the counter. The device works as follows. When the power supply unit is turned on. 4 of the initial reset forms a short impulse j which through the first element. OR 5 sets the first D-trigger 3 to the zero state. At the same time, this pulse arrives at the first input of the control generator 13 of pulses and sets the second D-flip-flop 21 to the zero state. Thus, the zero signal from the output of the D-flip-flop 21 does not solve the passage of the frequency of the reference oscillator 20 through the fifth and sixth elements AND 24, 25 to the first and second outputs of the controlled oscillator 13 pulses. The inputs of the first register 1 are supplied with a modulated signal S presented in the additional code. The sign is encoded 1, the sign + is encoded O. To the inputs of the second register 22, an N code is applied, which determines the frequency of the controlled generator of 13 pulses on the first f ,, fc, / (). where the frequency of the reference generator; 1 / T ..., is the frequency at the first output of the controlled generator of 13 pulses; m is the number of bits of the second counter 23. The steepness of the static characteristic of the converter is determined by the expression K - -: t 1EI where T is the pulse period at the output of the divider 14; - the duration of the output pulse. When the Start impulse signal is given, the corresponding bus enters the first input (e-input) of the second D-trag 21 and sets it to state 1 on the leading edge, thereby resolving the passage of frequency from the output of counter 23 through AND 24 to the first and the frequency fo from the output of the reference generator 20 through the element 25, respectively, to the second outputs of the controlled generator of 13 pulses. On the leading edge of the pulse from the output of the second element OR 6, information is recorded in the first and second 22 registers. The same impulse with delay Tj, determined by block 7 with delay, is fed to the third input (record input) of the reversible counter 2, to the fourth input of the controlled generator 13 a pulse. ow (the entry entry of the counter 23 and sets the first D-flip-flop 3 to 1. Thus, the counter N is written in the counter 23, and the code E in the reversing counter 2. The number of inverter pairs 7 of the delay unit 7 is chosen from At the moment of writing the pulse to the inputs of the reversible counter 2 and counter 23, codes and N. were written to the corresponding registers. 6 Consider the case. The signal is presented in the additional code. Because the sign of the first register 1 is O, then the pulses from the first output controlled generator 13. pulses proh d through the element AND 8 to the first (subtractive) input of the reversible counter 2. At the moment when all the output bits of the reversible counter 2 become zero, a single pulse appears at its output, shifted in phase by the value T | E1T, - , d relative to the pulse at the C input of the D-flip-flop 3, which through the element OR 5 enters the R-input of the D-flip-flop 3 and sets the latter to the O state. A sequential pulse from the output of the divider 14 writes to the first 1 and second registers new information, and through the time determined by the delay unit 7, the census information into the reversible counter 2 and counter 23, and also sets the first D-flip-flop 3 to state 1, the duration modulated pulses appear at the output of the third element 10, after which the work cycle repeats. If the error code recorded in the first register is negative (in the sign bit 1, then the pulses from the first generator output 13 pulses through the second element 9 will go to the second (summing) input of the reversible counter 2, and the output signal of the converter will be removed from the fourth of element 11. The rest of the operation of the circuit is similar. The steepness of the static characteristic of the converter is determined by the expression K (2 -), (here T A T - the division ratio of the de K-value - indicates. The duty cycle corresponds to the code E 00 ... 01. Whence it follows that by changing the Ng code recorded in the second register, it is possible to change the static characteristic characteristic of the converter - BAT in a wide range. If necessary, stop the modulator, close the key in the initial reset unit 4. At the output, a pulse is generated at its output, setting in O triggers 3 and 21, and on the Outputs of the converter, zero signals are obtained, which are stored for an arbitrarily long time. The fifth and sixth elements H 24, 25 are closed and the frequency does not pass on the first and second pulse generators. Restarting the converter is possible only by the PS signal. Start on bus 1 8. . In the proposed device, when the reference oscillator frequency is 10 MHz, it is possible to achieve a change in the steepness of the static characteristic in the 1: 256 range with a resolution of 0.1% (if counter 23 has eight bits). In the known device, with such parameters, it is possible to obtain a range of variation of a steepness of 1: 1.3 with an uneven discreteness of 2.10 or less. At the same time, technical tasks require, as a rule, a large range of tuning, as well as greater discreteness and uniformity of variation of the steepness of the static characteristic . Thus, the technical and economic effect of the use of the invention lies in the fact that the proposed device allows to convert numbers, presented in an additional code, into a pulse-width modulated signal

77

cpuz.1 86 also make adjustment of the steepness of the static characteristic without changing the frequency of the control pulses. The use of this converter is especially effective in digital control systems of the degrees of mobility of the manipulator operating in the time division mode. At the same time, the reduction of the mass, size and cost parameters of the system is achieved by using one microprocessor and one code-PWM converter for up to seven degrees of mobility, which are controlled by a unified service program. The only way to compensate for imperfect-. The drive is the adjustment of the steepness of the static characteristic of the converter. In this case, each drive will correspond to the new code value. In addition, using such converters, high-quality digital adaptive systems can be built in which the gain is purposefully changed during the control process. In this case, the possibility of electromechanical resonance at the subharmonic frequency of the PWM is completely excluded, since the period of the following pulses of the PWM is constant.

FIG. 2

Claims (2)

1. A CODIM converter, containing two OR elements. there are four AND elements, the first register, the information inputs of which are connected to the corresponding first code buses, the recording input is to the output of the second OR element and the input of the delay unit, and the sign output is to the first inputs of the second and fourth AND elements and through the inverter to the first inputs the first and third AND elements, and a controlled pulse generator, the first input of which and the first input of the first OR element are connected to the output of the initial reset unit, the second input -. with the Start bus And the first input of the second OR element, and the first output with the second inputs of the first and second AND elements, the outputs of which are respectively connected to the first and second inputs of the reverse counter, the third input of which is connected to the output of the delay unit and the C-input of the first P- a trigger whose D-input is connected to the bus of the enable level, the R-input is to the output of the first OR element, and the output is to the second inputs of the third and fourth AND elements, the outputs of which are respectively connected to the output buses, by us, characterized in that, to increase I reliably and expand the functionality, a frequency divider is introduced into it, the first and second inputs of which are connected respectively to the second output of the controlled pulse generator and the Start bus, and the output is connected to the second input of the second OR element, while the third and fourth inputs of the controlled pulse generator .connected respectively to the output of the second OR element and the third input of the reverse counter, the inputs of which are respectively connected to the discharge outputs of the first register, and the output is connected to the second input of the first element OR, and the fifth inputs of the controlled pulse generator are respectively connected to the second code buses. 2. The converter according to π. 1, characterized in that the controllable pulse generator is made on a reference generator, pulse counter, fifth and sixth AND elements, a second register and a second C-trigger, whose R and C inputs are connected respectively to the first and second inputs of the controlled generator pulses. D-input - to the bus permission level, and the output - to the first inputs of the fifth and sixth elements. I. the outputs of which are respectively connected to the first and second outputs of the controlled pulse generator, the third and fourth inputs of which SU. 1164886 1 164886, respectively, are connected to the recording input of the second register and the input of the pulse counter recording, and the fifth inputs are connected to the corresponding information inputs of the second register, the outputs of which are connected to the corresponding information inputs of the pulse counter, the output of which is connected to. the second input of the fifth element And, and the counting input with the output of the reference generator and the second input of the sixth element I.