SG93197A1 - Etching solution for etching porous silicon, etching method using the etching solution and method of preparing semiconductor member using the etching solution - Google Patents

Etching solution for etching porous silicon, etching method using the etching solution and method of preparing semiconductor member using the etching solution

Info

Publication number
SG93197A1
SG93197A1 SG9901639A SG1999001639A SG93197A1 SG 93197 A1 SG93197 A1 SG 93197A1 SG 9901639 A SG9901639 A SG 9901639A SG 1999001639 A SG1999001639 A SG 1999001639A SG 93197 A1 SG93197 A1 SG 93197A1
Authority
SG
Singapore
Prior art keywords
etching
etching solution
porous silicon
solution
semiconductor member
Prior art date
Application number
SG9901639A
Other languages
English (en)
Inventor
Kiyofumi Sakaguchi
Nobuhiko Sato
Takao Yonehara
Original Assignee
Canon Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP3148164A external-priority patent/JPH04346418A/ja
Priority claimed from JP3149297A external-priority patent/JPH04349621A/ja
Application filed by Canon Kk filed Critical Canon Kk
Publication of SG93197A1 publication Critical patent/SG93197A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/0203—Making porous regions on the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Weting (AREA)
SG9901639A 1991-02-15 1992-02-14 Etching solution for etching porous silicon, etching method using the etching solution and method of preparing semiconductor member using the etching solution SG93197A1 (en)

Applications Claiming Priority (49)

Application Number Priority Date Filing Date Title
JP4221391 1991-02-15
JP4221291 1991-02-15
JP5560391 1991-02-28
JP5561391 1991-02-28
JP5561091 1991-02-28
JP5561291 1991-02-28
JP5560291 1991-02-28
JP5561191 1991-02-28
JP5560491 1991-02-28
JP5560991 1991-02-28
JP5561491 1991-02-28
JP5560191 1991-02-28
JP5560791 1991-02-28
JP5560691 1991-02-28
JP5560891 1991-02-28
JP5560591 1991-02-28
JP8575591 1991-03-27
JP14816191 1991-05-24
JP14816091 1991-05-24
JP14816391 1991-05-24
JP3148164A JPH04346418A (ja) 1991-05-24 1991-05-24 半導体基材の作製方法
JP14931191 1991-05-27
JP14930191 1991-05-27
JP14930291 1991-05-27
JP14930791 1991-05-27
JP14930991 1991-05-27
JP3149297A JPH04349621A (ja) 1991-05-27 1991-05-27 半導体基材の作製方法
JP14930691 1991-05-27
JP14929891 1991-05-27
JP14930891 1991-05-27
JP14929991 1991-05-27
JP14931091 1991-05-27
JP14930091 1991-05-27
JP15099391 1991-05-28
JP15099491 1991-05-28
JP15098991 1991-05-28
JP15098591 1991-05-28
JP15099091 1991-05-28
JP15098191 1991-05-28
JP15098391 1991-05-28
JP15099291 1991-05-28
JP15098091 1991-05-28
JP15098491 1991-05-28
JP15098291 1991-05-28
JP15099191 1991-05-28
JP15224891 1991-05-29
JP15225191 1991-05-29
JP15225091 1991-05-29
JP15224991 1991-05-29

Publications (1)

Publication Number Publication Date
SG93197A1 true SG93197A1 (en) 2002-12-17

Family

ID=27586982

Family Applications (2)

Application Number Title Priority Date Filing Date
SG9901639A SG93197A1 (en) 1991-02-15 1992-02-14 Etching solution for etching porous silicon, etching method using the etching solution and method of preparing semiconductor member using the etching solution
SG1996006372A SG47089A1 (en) 1991-02-15 1992-02-14 Etching solution for etching porous silicon etching method using the etching solution and method of preparing semiconductor member using the etching solution

Family Applications After (1)

Application Number Title Priority Date Filing Date
SG1996006372A SG47089A1 (en) 1991-02-15 1992-02-14 Etching solution for etching porous silicon etching method using the etching solution and method of preparing semiconductor member using the etching solution

Country Status (8)

Country Link
US (1) US5767020A (enExample)
EP (2) EP1347505A3 (enExample)
KR (1) KR960007640B1 (enExample)
CN (1) CN1099905A (enExample)
AT (1) ATE244931T1 (enExample)
CA (1) CA2061264C (enExample)
MY (1) MY114349A (enExample)
SG (2) SG93197A1 (enExample)

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US6171512B1 (en) * 1991-02-15 2001-01-09 Canon Kabushiki Kaisha Etching solution for etching porous silicon, etching method using the etching solution and method of preparing semiconductor member using the etching solution
CA2069038C (en) * 1991-05-22 1997-08-12 Kiyofumi Sakaguchi Method for preparing semiconductor member
TW211621B (enExample) * 1991-07-31 1993-08-21 Canon Kk
DE69232347T2 (de) * 1991-09-27 2002-07-11 Canon K.K., Tokio/Tokyo Verfahren zur Behandlung eines Substrats aus Silizium
DE69233314T2 (de) * 1991-10-11 2005-03-24 Canon K.K. Verfahren zur Herstellung von Halbleiter-Produkten
JP3112106B2 (ja) * 1991-10-11 2000-11-27 キヤノン株式会社 半導体基材の作製方法
JP3237888B2 (ja) * 1992-01-31 2001-12-10 キヤノン株式会社 半導体基体及びその作製方法
JP3416163B2 (ja) * 1992-01-31 2003-06-16 キヤノン株式会社 半導体基板及びその作製方法
TW330313B (en) * 1993-12-28 1998-04-21 Canon Kk A semiconductor substrate and process for producing same
US7148119B1 (en) 1994-03-10 2006-12-12 Canon Kabushiki Kaisha Process for production of semiconductor substrate
US6103598A (en) * 1995-07-13 2000-08-15 Canon Kabushiki Kaisha Process for producing semiconductor substrate
EP0926709A3 (en) * 1997-12-26 2000-08-30 Canon Kabushiki Kaisha Method of manufacturing an SOI structure
JP3218564B2 (ja) 1998-01-14 2001-10-15 キヤノン株式会社 多孔質領域の除去方法及び半導体基体の製造方法
TW405234B (en) * 1998-05-18 2000-09-11 United Microelectronics Corp Method for manufacturing a polysilicon fuse and the structure of the same
US6376859B1 (en) 1998-07-29 2002-04-23 Texas Instruments Incorporated Variable porosity porous silicon isolation
US6410436B2 (en) 1999-03-26 2002-06-25 Canon Kabushiki Kaisha Method of cleaning porous body, and process for producing porous body, non-porous film or bonded substrate
US6680900B1 (en) * 1999-06-04 2004-01-20 Ricoh Company, Ltd. Optical-pickup slider, manufacturing method thereof, probe and manufacturing method thereof, and probe array and manufacturing method thereof
DE19935446A1 (de) * 1999-07-28 2001-02-01 Merck Patent Gmbh Ätzlösung, Flußsäure enthaltend
US6653209B1 (en) 1999-09-30 2003-11-25 Canon Kabushiki Kaisha Method of producing silicon thin film, method of constructing SOI substrate and semiconductor device
US6790785B1 (en) 2000-09-15 2004-09-14 The Board Of Trustees Of The University Of Illinois Metal-assisted chemical etch porous silicon formation method
WO2002103752A2 (en) 2000-11-27 2002-12-27 The Board Of Trustees Of The University Of Illinois Metal-assisted chemical etch to produce porous group iii-v materials
US20030134486A1 (en) * 2002-01-16 2003-07-17 Zhongze Wang Semiconductor-on-insulator comprising integrated circuitry
JP2004228150A (ja) * 2003-01-20 2004-08-12 Canon Inc エッチング方法
US20050132332A1 (en) * 2003-12-12 2005-06-16 Abhay Sathe Multi-location coordinated test apparatus
US7244659B2 (en) * 2005-03-10 2007-07-17 Micron Technology, Inc. Integrated circuits and methods of forming a field effect transistor
US7972910B2 (en) 2005-06-03 2011-07-05 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of integrated circuit device including thin film transistor
US7557002B2 (en) * 2006-08-18 2009-07-07 Micron Technology, Inc. Methods of forming transistor devices
JP2010505728A (ja) * 2006-10-05 2010-02-25 日立化成工業株式会社 高配列、高アスペクト比、高密度のシリコンナノワイヤー及びその製造方法
US7989322B2 (en) * 2007-02-07 2011-08-02 Micron Technology, Inc. Methods of forming transistors
EP2104140A1 (en) * 2008-03-21 2009-09-23 Rise Technology S.r.l. Conductive microstructure obtained by converting porous silicon into porous metal
CN102037560B (zh) * 2008-03-21 2012-09-26 Rise技术有限责任公司 通过将多孔硅转变成多孔金属或陶瓷来制作微结构的方法
IT1391596B1 (it) * 2008-11-04 2012-01-11 Rise Technology S R L Microstrutture ottenute convertendo silicio poroso
US8387230B2 (en) * 2010-08-27 2013-03-05 Transducerworks, Llc Method of making an ultrasonic transducer system
EP2630669A4 (en) 2010-10-22 2014-04-23 California Inst Of Techn PHONONIC NANOMESH STRUCTURES FOR HEAT ENERGY TRANSFORMATION MATERIALS WITH LOW HEAT-CONDUCTIVITY
US20130019918A1 (en) 2011-07-18 2013-01-24 The Regents Of The University Of Michigan Thermoelectric devices, systems and methods
WO2013109729A1 (en) 2012-01-17 2013-07-25 Silicium Energy, Inc. Systems and methods for forming thermoelectric devices
US9136134B2 (en) 2012-02-22 2015-09-15 Soitec Methods of providing thin layers of crystalline semiconductor material, and related structures and devices
WO2013149205A1 (en) 2012-03-29 2013-10-03 California Institute Of Technology Phononic structures and related devices and methods
JP6353447B2 (ja) 2012-08-17 2018-07-04 マトリックス インダストリーズ，インコーポレイテッド 熱電デバイスを形成するためのシステム及び方法
WO2014070795A1 (en) 2012-10-31 2014-05-08 Silicium Energy, Inc. Methods for forming thermoelectric elements
DE102014103303A1 (de) 2014-03-12 2015-10-01 Universität Konstanz Verfahren zum Herstellen von Solarzellen mit simultan rückgeätzten dotierten Bereichen
US9263662B2 (en) 2014-03-25 2016-02-16 Silicium Energy, Inc. Method for forming thermoelectric element using electrolytic etching
JP2019523391A (ja) 2016-05-03 2019-08-22 マトリックス インダストリーズ，インコーポレイテッド 熱電デバイス及びシステム
USD819627S1 (en) 2016-11-11 2018-06-05 Matrix Industries, Inc. Thermoelectric smartwatch
CN112221010B (zh) * 2020-11-09 2022-08-09 中国科学技术大学 一种采用金属辅助湿法刻蚀制备硅基微针的制备方法及其应用
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US4983251A (en) * 1985-06-20 1991-01-08 U.S. Philips Corporation Method of manufacturing semiconductor devices

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US4171242A (en) * 1976-12-17 1979-10-16 International Business Machines Corporation Neutral pH silicon etchant for etching silicon in the presence of phosphosilicate glass
US4983251A (en) * 1985-06-20 1991-01-08 U.S. Philips Corporation Method of manufacturing semiconductor devices

Also Published As

Publication number Publication date
KR960007640B1 (en) 1996-06-07
MY114349A (en) 2002-10-31
EP1347505A2 (en) 2003-09-24
EP0499488B1 (en) 2003-07-09
EP0499488B9 (en) 2004-01-28
ATE244931T1 (de) 2003-07-15
CN1099905A (zh) 1995-03-08
US5767020A (en) 1998-06-16
CA2061264C (en) 1999-11-16
EP1347505A3 (en) 2004-10-20
EP0499488A2 (en) 1992-08-19
EP0499488A3 (enExample) 1995-03-01
SG47089A1 (en) 1998-03-20
CA2061264A1 (en) 1992-08-16

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