SG171714A1 - Strain engineered composite semiconductor substrates and methods of forming same - Google Patents

Strain engineered composite semiconductor substrates and methods of forming same Download PDF

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Publication number
SG171714A1
SG171714A1 SG2011029006A SG2011029006A SG171714A1 SG 171714 A1 SG171714 A1 SG 171714A1 SG 2011029006 A SG2011029006 A SG 2011029006A SG 2011029006 A SG2011029006 A SG 2011029006A SG 171714 A1 SG171714 A1 SG 171714A1
Authority
SG
Singapore
Prior art keywords
strained
substrate
nitride material
strain
seed layer
Prior art date
Application number
SG2011029006A
Other languages
English (en)
Inventor
Fabrice Letertre
Jean-Marc Bethoux
Alice Boussagol
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Publication of SG171714A1 publication Critical patent/SG171714A1/en

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005Processes
    • H01L33/0062Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005Processes
    • H01L33/0093Wafer bonding; Removal of the growth substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Recrystallisation Techniques (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Semiconductor Lasers (AREA)
SG2011029006A 2008-12-19 2008-12-19 Strain engineered composite semiconductor substrates and methods of forming same SG171714A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/IB2008/003597 WO2010070377A1 (en) 2008-12-19 2008-12-19 Strain engineered composite semiconductor substrates and methods of forming same

Publications (1)

Publication Number Publication Date
SG171714A1 true SG171714A1 (en) 2011-07-28

Family

ID=40949292

Family Applications (1)

Application Number Title Priority Date Filing Date
SG2011029006A SG171714A1 (en) 2008-12-19 2008-12-19 Strain engineered composite semiconductor substrates and methods of forming same

Country Status (6)

Country Link
EP (1) EP2377153A1 (ja)
JP (1) JP2012513113A (ja)
KR (1) KR101226073B1 (ja)
CN (1) CN102246291B (ja)
SG (1) SG171714A1 (ja)
WO (1) WO2010070377A1 (ja)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101659738B1 (ko) * 2010-07-08 2016-09-26 엘지이노텍 주식회사 발광 소자 제조방법
FR2978605B1 (fr) * 2011-07-28 2015-10-16 Soitec Silicon On Insulator Procede de fabrication d'une structure semi-conductrice comprenant une couche fonctionnalisee sur un substrat support
KR102002898B1 (ko) 2012-09-04 2019-07-23 삼성전자 주식회사 반도체 버퍼 구조체 및 이를 포함하는 반도체 소자
JP7201141B2 (ja) * 2016-01-20 2023-01-10 マサチューセッツ インスティテュート オブ テクノロジー キャリア基板上のデバイスの製造
JP7028547B2 (ja) * 2016-06-20 2022-03-02 株式会社アドバンテスト 化合物半導体装置の製造方法
CN106449368B (zh) * 2016-11-24 2020-05-12 清华大学 半导体结构以及制备方法
TWI701715B (zh) * 2017-06-06 2020-08-11 黃知澍 N-face III族/氮化物磊晶結構及其主動元件與其積體化之極性反轉製作方法
CN112585305B (zh) * 2018-08-09 2023-03-28 信越化学工业株式会社 GaN层叠基板的制造方法
JP7253994B2 (ja) * 2019-07-23 2023-04-07 株式会社ディスコ 光デバイスの移設方法
CN112735944A (zh) * 2021-01-05 2021-04-30 西安电子科技大学 氮极性面GaN材料及其制作方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2871172B1 (fr) * 2004-06-03 2006-09-22 Soitec Silicon On Insulator Support d'epitaxie hybride et son procede de fabrication
US8334155B2 (en) * 2005-09-27 2012-12-18 Philips Lumileds Lighting Company Llc Substrate for growing a III-V light emitting device
US7638410B2 (en) * 2005-10-03 2009-12-29 Los Alamos National Security, Llc Method of transferring strained semiconductor structure
JP5604102B2 (ja) * 2006-06-21 2014-10-08 独立行政法人科学技術振興機構 安熱法による成長で作製された、窒素面またはM面GaN基板を用いた光電子デバイスと電子デバイス

Also Published As

Publication number Publication date
KR101226073B1 (ko) 2013-01-25
EP2377153A1 (en) 2011-10-19
CN102246291A (zh) 2011-11-16
JP2012513113A (ja) 2012-06-07
CN102246291B (zh) 2015-12-16
WO2010070377A1 (en) 2010-06-24
KR20110081331A (ko) 2011-07-13

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