SG166047A1 - Method for transferring a layer from a donor substrate onto a handle substrate - Google Patents

Method for transferring a layer from a donor substrate onto a handle substrate

Info

Publication number
SG166047A1
SG166047A1 SG201001743-2A SG2010017432A SG166047A1 SG 166047 A1 SG166047 A1 SG 166047A1 SG 2010017432 A SG2010017432 A SG 2010017432A SG 166047 A1 SG166047 A1 SG 166047A1
Authority
SG
Singapore
Prior art keywords
transferring
layer
substrate
donor substrate
onto
Prior art date
Application number
SG201001743-2A
Other languages
English (en)
Inventor
Sebastien Kerdiles
Walter Schwarzenbach
Aziz Alami-Idrissi
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Publication of SG166047A1 publication Critical patent/SG166047A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02032—Preparing bulk and homogeneous wafers by reclaiming or re-processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
SG201001743-2A 2009-04-29 2010-03-12 Method for transferring a layer from a donor substrate onto a handle substrate SG166047A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP09290314.5A EP2246882B1 (en) 2009-04-29 2009-04-29 Method for transferring a layer from a donor substrate onto a handle substrate

Publications (1)

Publication Number Publication Date
SG166047A1 true SG166047A1 (en) 2010-11-29

Family

ID=41116012

Family Applications (1)

Application Number Title Priority Date Filing Date
SG201001743-2A SG166047A1 (en) 2009-04-29 2010-03-12 Method for transferring a layer from a donor substrate onto a handle substrate

Country Status (7)

Country Link
US (2) US8476148B2 (ko)
EP (1) EP2246882B1 (ko)
JP (1) JP2010263187A (ko)
KR (1) KR101650166B1 (ko)
CN (1) CN101877308B (ko)
SG (1) SG166047A1 (ko)
TW (1) TWI487014B (ko)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2246882B1 (en) * 2009-04-29 2015-03-04 Soitec Method for transferring a layer from a donor substrate onto a handle substrate
JP5799740B2 (ja) * 2011-10-17 2015-10-28 信越半導体株式会社 剥離ウェーハの再生加工方法
FR3007576B1 (fr) * 2013-06-19 2015-07-10 Soitec Silicon On Insulator Procede de transfert d'une couche de circuits.
FR3036223B1 (fr) * 2015-05-11 2018-05-25 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de collage direct de substrats avec amincissement des bords d'au moins un des deux substrats
DE102015210384A1 (de) * 2015-06-05 2016-12-08 Soitec Verfahren zur mechanischen Trennung für eine Doppelschichtübertragung
US20180033609A1 (en) * 2016-07-28 2018-02-01 QMAT, Inc. Removal of non-cleaved/non-transferred material from donor substrate
FR3076393A1 (fr) * 2017-12-28 2019-07-05 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de transfert d'une couche utile
TWI741911B (zh) * 2020-12-16 2021-10-01 環球晶圓股份有限公司 磊晶層去除方法
CN117393422B (zh) * 2023-12-11 2024-03-01 青禾晶元(天津)半导体材料有限公司 一种制造碳化硅复合衬底的方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11288858A (ja) * 1998-01-30 1999-10-19 Canon Inc Ｓｏｉ基板の再生方法及び再生基板
JP3932369B2 (ja) * 1998-04-09 2007-06-20 信越半導体株式会社 剥離ウエーハを再利用する方法および再利用に供されるシリコンウエーハ
JP4313874B2 (ja) * 1999-02-02 2009-08-12 キヤノン株式会社 基板の製造方法
JP3943782B2 (ja) 1999-11-29 2007-07-11 信越半導体株式会社 剥離ウエーハの再生処理方法及び再生処理された剥離ウエーハ
KR100359483B1 (ko) * 2000-10-24 2002-10-31 고려용접봉 주식회사 가스 쉴드 아아크 용접용 플럭스 코어드 와이어
FR2892228B1 (fr) * 2005-10-18 2008-01-25 Soitec Silicon On Insulator Procede de recyclage d'une plaquette donneuse epitaxiee
FR2852445B1 (fr) * 2003-03-14 2005-05-20 Soitec Silicon On Insulator Procede de realisation de substrats ou composants sur substrats avec transfert de couche utile, pour la microelectronique, l'optoelectronique ou l'optique
JP4415588B2 (ja) * 2003-08-28 2010-02-17 株式会社Ｓｕｍｃｏ 剥離ウェーハの再生処理方法
FR2860842B1 (fr) * 2003-10-14 2007-11-02 Tracit Technologies Procede de preparation et d'assemblage de substrats
WO2006037783A1 (fr) * 2004-10-04 2006-04-13 S.O.I.Tec Silicon On Insulator Technologies Procédé de transfert d'une couche mince comprenant une perturbation controlée d'une structure cristalline
US7402520B2 (en) 2004-11-26 2008-07-22 Applied Materials, Inc. Edge removal of silicon-on-insulator transfer wafer
EP1911085B1 (en) * 2005-07-08 2011-10-12 S.O.I.Tec Silicon on Insulator Technologies Method of production of a film
CN2923902Y (zh) * 2006-07-27 2007-07-18 白宝鲲 点支式幕墙的吊装系统
FR2907966B1 (fr) * 2006-10-27 2009-01-30 Soitec Silicon On Insulator Procede de fabrication d'un substrat.
FR2917232B1 (fr) * 2007-06-06 2009-10-09 Soitec Silicon On Insulator Procede de fabrication d'une structure pour epitaxie sans zone d'exclusion.
EP2246882B1 (en) 2009-04-29 2015-03-04 Soitec Method for transferring a layer from a donor substrate onto a handle substrate

Also Published As

Publication number Publication date
US8476148B2 (en) 2013-07-02
CN101877308A (zh) 2010-11-03
CN101877308B (zh) 2016-03-09
JP2010263187A (ja) 2010-11-18
US8728913B2 (en) 2014-05-20
KR20100118932A (ko) 2010-11-08
EP2246882A1 (en) 2010-11-03
US20130295696A1 (en) 2013-11-07
TW201113939A (en) 2011-04-16
KR101650166B1 (ko) 2016-08-23
TWI487014B (zh) 2015-06-01
US20100279487A1 (en) 2010-11-04
EP2246882B1 (en) 2015-03-04

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