EA201691900A1 - Способ повторного использования подложек и несущих подложек - Google Patents

Способ повторного использования подложек и несущих подложек

Info

Publication number
EA201691900A1
EA201691900A1 EA201691900A EA201691900A EA201691900A1 EA 201691900 A1 EA201691900 A1 EA 201691900A1 EA 201691900 A EA201691900 A EA 201691900A EA 201691900 A EA201691900 A EA 201691900A EA 201691900 A1 EA201691900 A1 EA 201691900A1
Authority
EA
Eurasian Patent Office
Prior art keywords
substrate
substrates
forming
buffer layer
layers
Prior art date
Application number
EA201691900A
Other languages
English (en)
Inventor
Хильми Волькан Демир
Свее Тиам Тан
Original Assignee
Наньян Текнолоджикал Юнивёрсити
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Наньян Текнолоджикал Юнивёрсити filed Critical Наньян Текнолоджикал Юнивёрсити
Publication of EA201691900A1 publication Critical patent/EA201691900A1/ru

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/08—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6835—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during build up manufacturing of active devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Led Devices (AREA)
  • Separation, Recovery Or Treatment Of Waste Materials Containing Plastics (AREA)

Abstract

Согласно различным вариантам осуществления изобретения предложен способ повторного использования несущих подложек. Способ содержит обеспечение несущей подложки, формирование буферного слоя путем нанесения подходящего материала на несущую подложку, формирование одного или более слоев компонентов поверх буферного слоя, отделение указанных одного или более слоев компонентов от несущей подложки так, что после отделения по меньшей мере часть буферного слоя остается на несущей подложке, и формирование дополнительного буферного слоя из части буферного слоя после процесса отделения путем нанесения подходящего материала, чтобы повторно использовать несущую подложку. Также предложен способ повторного использования подложки, который содержит формирование на подложке изолирующего слоя, удаление первой части изолирующего слоя так, чтобы первая часть подложки оказалась открытой, формирование одного или более слоев компонентов поверх первой части подложки и отделение указанного одного или более слоев компонентов от подложки, чтобы повторно использовать подложку.
EA201691900A 2014-03-31 2015-02-16 Способ повторного использования подложек и несущих подложек EA201691900A1 (ru)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201461972575P 2014-03-31 2014-03-31
PCT/SG2015/000048 WO2015152817A1 (en) 2014-03-31 2015-02-16 Methods of recycling substrates and carrier substrates

Publications (1)

Publication Number Publication Date
EA201691900A1 true EA201691900A1 (ru) 2017-05-31

Family

ID=54240965

Family Applications (1)

Application Number Title Priority Date Filing Date
EA201691900A EA201691900A1 (ru) 2014-03-31 2015-02-16 Способ повторного использования подложек и несущих подложек

Country Status (5)

Country Link
EP (1) EP3127143A4 (ru)
CN (1) CN106463451B (ru)
EA (1) EA201691900A1 (ru)
TW (1) TW201601192A (ru)
WO (1) WO2015152817A1 (ru)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7059518B2 (ja) * 2017-04-03 2022-04-26 住友電気工業株式会社 半導体光素子を作製する方法
CN109037263A (zh) * 2017-06-09 2018-12-18 美商晶典有限公司 具有透光基材的微发光二极管显示模块及其制造方法
CN109728142B (zh) * 2017-10-31 2021-02-02 展晶科技(深圳)有限公司 发光二极管晶粒的制造方法
JP2021170595A (ja) * 2020-04-15 2021-10-28 国立大学法人東海国立大学機構 窒化ガリウム半導体装置およびその製造方法
CN112967992B (zh) * 2020-12-07 2022-09-23 重庆康佳光电技术研究院有限公司 外延结构的转移方法
TWI741911B (zh) * 2020-12-16 2021-10-01 環球晶圓股份有限公司 磊晶層去除方法
CN112786762B (zh) * 2021-01-04 2022-05-17 华灿光电（浙江）有限公司 发光二极管外延片及其制备方法
CN113257971B (zh) * 2021-06-30 2021-10-22 南昌凯捷半导体科技有限公司 一种红光mini-LED芯片的制作方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030189215A1 (en) * 2002-04-09 2003-10-09 Jong-Lam Lee Method of fabricating vertical structure leds
KR100755656B1 (ko) * 2006-08-11 2007-09-04 삼성전기주식회사 질화물계 반도체 발광소자의 제조방법
JP4721017B2 (ja) * 2008-04-07 2011-07-13 ソニー株式会社 半導体デバイスの製造方法
US8236583B2 (en) * 2008-09-10 2012-08-07 Tsmc Solid State Lighting Ltd. Method of separating light-emitting diode from a growth substrate
US8581229B2 (en) * 2009-11-23 2013-11-12 Koninklijke Philips N.V. III-V light emitting device with thin n-type region
US7781242B1 (en) * 2009-12-10 2010-08-24 Walsin Lihwa Corporation Method of forming vertical structure light emitting diode with heat exhaustion structure
TWI452621B (zh) * 2010-11-01 2014-09-11 Univ Nat Cheng Kung Separation method of epitaxial element
WO2013004188A1 (zh) * 2011-07-07 2013-01-10 厦门市三安光电科技有限公司 太阳能电池，系统，及其制作方法
TWI447952B (zh) * 2011-08-22 2014-08-01 Lextar Electronics Corp 發光二極體裝置的製造方法及發光半導體結構
WO2013123241A1 (en) * 2012-02-17 2013-08-22 The Regents Of The University Of California Method for the reuse of gallium nitride epitaxial substrates

Also Published As

Publication number Publication date
EP3127143A1 (en) 2017-02-08
TW201601192A (zh) 2016-01-01
WO2015152817A1 (en) 2015-10-08
CN106463451B (zh) 2019-07-16
CN106463451A (zh) 2017-02-22
EP3127143A4 (en) 2017-11-29

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