SG11202102573QA - Process for producing an advanced substrate for hybrid integration - Google Patents

Process for producing an advanced substrate for hybrid integration

Info

Publication number
SG11202102573QA
SG11202102573QA SG11202102573QA SG11202102573QA SG11202102573QA SG 11202102573Q A SG11202102573Q A SG 11202102573QA SG 11202102573Q A SG11202102573Q A SG 11202102573QA SG 11202102573Q A SG11202102573Q A SG 11202102573QA SG 11202102573Q A SG11202102573Q A SG 11202102573QA
Authority
SG
Singapore
Prior art keywords
producing
hybrid integration
advanced substrate
advanced
substrate
Prior art date
Application number
SG11202102573QA
Inventor
Walter Schwarzenbach
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Publication of SG11202102573QA publication Critical patent/SG11202102573QA/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H01L27/1207Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)
  • Pressure Sensors (AREA)
  • Addition Polymer Or Copolymer, Post-Treatments, Or Chemical Modifications (AREA)
  • Polymers With Sulfur, Phosphorus Or Metals In The Main Chain (AREA)
  • Macromolecular Compounds Obtained By Forming Nitrogen-Containing Linkages In General (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
SG11202102573QA 2018-09-14 2019-09-11 Process for producing an advanced substrate for hybrid integration SG11202102573QA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1800972A FR3086096B1 (en) 2018-09-14 2018-09-14 PROCESS FOR MAKING AN ADVANCED SUBSTRATE FOR A HYBRID INTEGRATION
PCT/EP2019/074276 WO2020053306A1 (en) 2018-09-14 2019-09-11 Method for producing an advanced substrate for hybrid integration

Publications (1)

Publication Number Publication Date
SG11202102573QA true SG11202102573QA (en) 2021-04-29

Family

ID=65200879

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11202102573QA SG11202102573QA (en) 2018-09-14 2019-09-11 Process for producing an advanced substrate for hybrid integration

Country Status (9)

Country Link
US (2) US11476153B2 (en)
EP (1) EP3850659A1 (en)
JP (1) JP7392242B2 (en)
KR (1) KR20210055749A (en)
CN (1) CN113039635A (en)
FR (1) FR3086096B1 (en)
SG (1) SG11202102573QA (en)
TW (1) TWI787545B (en)
WO (1) WO2020053306A1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3086096B1 (en) 2018-09-14 2021-08-27 Soitec Silicon On Insulator PROCESS FOR MAKING AN ADVANCED SUBSTRATE FOR A HYBRID INTEGRATION
US10862610B1 (en) * 2019-11-11 2020-12-08 X Development Llc Multi-channel integrated photonic wavelength demultiplexer
US11187854B2 (en) 2019-11-15 2021-11-30 X Development Llc Two-channel integrated photonic wavelength demultiplexer
WO2024107824A1 (en) * 2022-11-18 2024-05-23 Microchip Technology Incorporated Method for fabricating a patterned fd-soi wafer

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3435930B2 (en) * 1995-09-28 2003-08-11 株式会社デンソー Semiconductor device and manufacturing method thereof
JP4144047B2 (en) * 1997-08-20 2008-09-03 株式会社デンソー Manufacturing method of semiconductor substrate
JPH11112000A (en) * 1997-10-06 1999-04-23 Denso Corp Semiconductor device
US7049660B2 (en) * 2003-05-30 2006-05-23 International Business Machines Corporation High-quality SGOI by oxidation near the alloy melting temperature
FR2875947B1 (en) * 2004-09-30 2007-09-07 Tracit Technologies NOVEL STRUCTURE FOR MICROELECTRONICS AND MICROSYSTEMS AND METHOD OF MAKING SAME
FR2897982B1 (en) * 2006-02-27 2008-07-11 Tracit Technologies Sa METHOD FOR MANUFACTURING PARTIALLY-LIKE STRUCTURES, COMPRISING AREAS CONNECTING A SURFACE LAYER AND A SUBSTRATE
FR2906078B1 (en) * 2006-09-19 2009-02-13 Commissariat Energie Atomique METHOD FOR MANUFACTURING A MIXED MICRO-TECHNOLOGICAL STRUCTURE AND A STRUCTURE THUS OBTAINED
FR2910702B1 (en) * 2006-12-26 2009-04-03 Soitec Silicon On Insulator METHOD FOR MANUFACTURING A MIXED SUBSTRATE
CN101617219B (en) 2007-02-23 2012-11-21 塞莫尼根分析技术有限责任公司 Hand-held, self-contained optical emission spectroscopy (OES) analyzer
FR2932789B1 (en) * 2008-06-23 2011-04-15 Commissariat Energie Atomique METHOD FOR MANUFACTURING AN ELECTROMECHANICAL STRUCTURE COMPRISING AT LEAST ONE MECHANICAL REINFORCING PILLAR
JP2013149811A (en) 2012-01-20 2013-08-01 Sony Corp Semiconductor device, manufacturing device and method, and image pickup element
JP2015041718A (en) * 2013-08-23 2015-03-02 マイクロン テクノロジー, インク. Semiconductor device and manufacturing method of the same
FR3052592B1 (en) 2016-06-08 2018-05-18 Soitec STRUCTURE FOR RADIO FREQUENCY APPLICATIONS
FR3062517B1 (en) 2017-02-02 2019-03-15 Soitec STRUCTURE FOR RADIO FREQUENCY APPLICATION
FR3086096B1 (en) 2018-09-14 2021-08-27 Soitec Silicon On Insulator PROCESS FOR MAKING AN ADVANCED SUBSTRATE FOR A HYBRID INTEGRATION

Also Published As

Publication number Publication date
TW202025390A (en) 2020-07-01
KR20210055749A (en) 2021-05-17
FR3086096A1 (en) 2020-03-20
TWI787545B (en) 2022-12-21
FR3086096B1 (en) 2021-08-27
US11476153B2 (en) 2022-10-18
US20230063362A1 (en) 2023-03-02
EP3850659A1 (en) 2021-07-21
JP7392242B2 (en) 2023-12-06
CN113039635A (en) 2021-06-25
US20220051934A1 (en) 2022-02-17
JP2022500869A (en) 2022-01-04
WO2020053306A1 (en) 2020-03-19

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