JPH11112000A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, wherein, without increasing the number of processes, two kinds of low withstand voltage system and high withstand voltage system transistors are manufactured. SOLUTION: On a silicon substrate 1, a low-voltage MOS transistor Q1 and a high-voltage MOS transistor Q2 are formed via an insulating film. In the low-voltage MOS transistor Q1, a polysilicon gate electrode 6 is provided on a single-crystal silicon layer 3 comprising a source/drain channel region via a first gate insulating film 5. In the high-voltage MOS transistor Q2, a polysilicon gate electrode 17 is provided under a single-crystal silicon layer 4 comprising a source/drain channel region via a second gate insulating film 2a of a thickness different from that of the first gate insulating film 5. A channel length L1 of the low-voltage MOS transistor Q1 is differs from a channel length L2 of the high-voltage MOS transistor Q2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a technology effective for a semiconductor device such as a DSP or CPU for a portable device which employs an SOI structure and is used at a low voltage.

[0002]

2. Description of the Related Art Conventionally, in addition to a logic LSI driven at a low voltage of, for example, about 1.5 volts, an analog LSI driven at a high voltage, one input element from a sensor or the like, or one output element to various actuators. In this case, it is necessary to separately form a low-voltage driving element and a high-voltage driving element. In this case, it is particularly important to ensure the withstand voltage of the high-voltage driving element. For example, in the manufacture of MOSFETs, two types of gate oxide films are separately formed by at least two thermal oxidation steps and one photolithography step. The withstand voltage of the voltage driving LSI has been increased.

[0003]

However, this method has a problem that the manufacturing cost is increased due to an increase in the number of steps.

An object of the present invention is to provide a semiconductor device capable of manufacturing two types of transistors, a low breakdown voltage system and a high breakdown voltage system, without increasing the number of steps.

[0005]

According to a first aspect of the present invention, there is provided a semiconductor device comprising: a first MOS transistor having a source / drain / channel region on a first semiconductor layer via a first gate insulating film; A second gate insulating film having a thickness different from that of the first gate insulating film under a second semiconductor layer having source / drain / channel regions in the second MOS transistor; The second gate electrode is disposed via the first gate electrode.

Therefore, when forming the low-voltage transistor and the high-voltage transistor on the same substrate, the first and second gate insulating films having different thicknesses are formed without greatly increasing the number of steps. be able to.

Here, if the channel length of the first MOS transistor is made different from the channel length of the second MOS transistor, it is practically preferable.

[0008] According to a third aspect of the present invention, the first type is provided.
MOS transistor having a third gate electrode formed in the same step as the second gate electrode,
It is practically preferable that the second MOS transistor has a fourth gate electrode formed in the same step as the first gate electrode, and holds the third gate electrode and the fourth gate electrode at a predetermined potential. Become something.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic sectional view of a semiconductor device in which both a low-voltage MOS transistor (first MOS transistor) Q1 and a high-voltage MOS transistor (second MOS transistor) Q2 are mounted. FIG. 2 also shows low-voltage and high-voltage MOS transistors Q1, Q2.
FIG. 1 is a schematic plan view of a semiconductor device on which a semiconductor device is mounted.

An insulating film 2 is formed on a silicon substrate 1 as a semiconductor substrate, and a single-crystal silicon layer (SOI layer) 3 as a first semiconductor layer and a second
A single crystal silicon layer (SOI layer) 4 as a semiconductor layer is formed. As the insulating film 2, a silicon oxide film is used. Polysilicon layer 6 is formed on single crystal silicon layer 3 with insulating film 5 interposed. Further, a polysilicon layer 8 is formed on the single crystal silicon layer 4 with an insulating film 7 interposed therebetween.
Are formed. A silicon oxide film is used for the insulating films 5 and 7.

A source region 9, a drain region 10 and a channel region 11 are formed in the single crystal silicon layer 3 constituting the low voltage MOS transistor Q1. In addition, a polysilicon layer 12 is embedded in the insulating film 2 below the single crystal silicon layer 3.

In the single crystal silicon layer 4 constituting the high voltage MOS transistor Q2, a source region 13, a drain region 14, and a channel region 15 are formed. In the channel region 15, an electric field relaxation region 16 is formed at the end on the drain side. In addition, the single crystal silicon layer 4
A polysilicon layer 17 is buried in the insulating film 2 below the polysilicon film. That is, the polysilicon layer 17 is arranged below the single-crystal silicon layer 4 via the insulating film 2a.

As described above, in the present embodiment, the polysilicon layers 12 and 17 are formed in the insulating film (oxide film) 2 below the single-crystal silicon layers (SOI layers) 3 and 4, and the polysilicon layers 12 and 17 are formed. A voltage can be applied by using a back gate electrode 17.

As an electrical connection structure, as shown in FIG. 2, the source region 9 and the polysilicon layer 12 of the low-voltage MOS transistor Q1 and the polysilicon layer 8 and the source region 13 of the high-voltage MOS transistor Q2 are grounded. Line (GND line). In addition, MO for low voltage
The drain region 10 of the S transistor Q1 is connected to a drain line, and the polysilicon layer 6 is connected to a low voltage power supply line. Further, the drain region 14 of the high voltage MOS transistor Q2 is connected to a drain line, and the polysilicon layer 17 is connected to a high voltage power supply line.

As described above, the polysilicon layer 6 as the first gate electrode is arranged on the single crystal silicon layer 3 with the first gate insulating film 5 interposed therebetween in the low voltage MOS transistor Q1. In the high-voltage MOS transistor Q2, a polysilicon layer 17 as a second gate electrode is provided below the single-crystal silicon layer 4 via a second gate insulating film 2a having a thickness different from that of the first gate insulating film 5. Is arranged.

That is, the high voltage MOS transistor Q2
, A polysilicon layer (back gate) 17 is used as a gate electrode, a source region 13 and a drain region 14 are formed in the upper SOI region (4), and a region between the source and the drain is a channel region 15. Also, an oxide film between the SOI layer 4 and the polysilicon layer (back gate) 17 is used as a gate insulating film 2a to ensure a high breakdown voltage.

As shown in FIG. 2, the channel length (source-drain distance) of the low-voltage MOS transistor Q1 is indicated by L1, and the channel length of the high-voltage MOS transistor Q2 is indicated by L2. In the high voltage MOS transistor Q2, an electric field relaxation region 16 is provided, and the presence of the electric field relaxation region 16 makes the channel length L2 of the high voltage MOS transistor Q2 longer than the channel length L1 of the low voltage MOS transistor Q1. .

The process can be further simplified if the source / drain regions 13 and 14 of the high voltage MOS transistor Q2 are implanted simultaneously with the source / drain regions 9 and 10 of the low voltage MOS transistor Q1.

In this case, the high voltage MOS transistor Q
The threshold value of 2 is controlled as follows. (I) In the case of gate oxide film thickness; oxide film thickness t1 between SOI layer 4 and polysilicon layer (back gate electrode) 17
Can be arbitrarily selected within a range satisfying the specifications of the low-voltage MOS transistor Q1. If the threshold value can be controlled by the film thickness t1, the number of steps does not increase. (Ii) In the case of the gate length: In general, the high-voltage MOS transistor Q2 does not require high-speed response and high integration for its purpose, and does not need a fine gate length, so that a large gate length can be used. It is. As described above, even when the threshold control using the short channel effect can be performed by the gate length, the number of steps does not increase.

In the low-voltage MOS transistor Q1, the polysilicon layer 12 serves as a third gate electrode, and in the high-voltage MOS transistor Q2, the polysilicon layer 8 serves as a fourth gate electrode. The third gate electrode 12 and the polysilicon layer (fourth gate electrode) 8 are held at the ground potential.

That is, the high voltage MOS transistor Q2
A polysilicon layer (8) used as a gate electrode of the low-voltage MOS transistor Q1 is also left on the upper part of the gate. By setting the polysilicon layer 8 to a predetermined potential, the threshold value of the high-voltage MOS transistor Q2 is controlled. can do. Furthermore, the high voltage MOS transistor Q2
Can be ensured by increasing the gate length or forming the electric field relaxation region 16 at the drain end. In forming the electric field relaxation region 16, a polysilicon layer (8) used as a gate electrode of the low-voltage MOS transistor Q1 is left above the high-voltage MOS transistor Q2, and ion implantation is performed by self-alignment using this. doing.

The polysilicon layer 8 shown in FIGS.
May be eliminated. In this case, the above (i),
If the threshold cannot be controlled by the method (ii), impurities are introduced into the channel region 15 by ion implantation.
On the high voltage MOS transistor Q2, a low voltage MO
Since there is no polysilicon layer (8) used as the gate electrode of the S transistor Q1, it is possible to implant impurities only in the region by patterning the gate polysilicon and implanting ions over the entire surface. In this case, the number of ion implantation steps is increased. However, the photolithography process does not increase.

FIG. 3 shows a more specific example of the schematic diagram of the semiconductor device shown in FIG. In FIG. 3, a bonding polysilicon film 20 is formed on a silicon substrate 1, and an insulating film 21 is disposed thereon. Polysilicon film 20
Polysilicon layers 12 and 17 covered with oxide films 22a and 22b are arranged between the gate electrode and the insulating film 21.
The single crystal silicon layer 3 is formed above the polysilicon layer 12, and the single crystal silicon layer 4 is formed above the polysilicon layer 17. A silicon oxide film 23 is formed on single crystal silicon layers 3 and 4.

In the low voltage MOS transistor Q1, a metal wire 24 for electrical connection with the source region 9 is formed, and a metal wire 25 for electrical connection with the drain region 10 is formed. In the high voltage MOS transistor Q2, a metal wiring 26 for electrical connection with the source region 13 is formed, and a metal wiring 27 for electrical connection with the drain region 14 is formed.
Further, a metal wiring 30 for electrical connection with the polysilicon layer 20 is formed. The surfaces of the silicon oxide film 23 and the metal wirings 24 to 27 and 30 are covered with a protective film 31.

Next, a method of manufacturing the semiconductor device shown in FIG. 3 will be described. 4 to 13 show a schematic process of the semiconductor device. First, as shown in FIG.
0 is set to, for example, 0.15 μm except for a portion to be an SOI region
Etch to the extent. Then, as shown in FIG. 5, an insulating film (oxide film) 21 of, for example, about 100 nm is deposited by thermal oxidation or CVD.

Further, as shown in FIG. 6, a polysilicon layer 41 of, eg, about 0.4 μm is deposited by CVD, and the resistance is reduced by a technique such as phosphorus deposition or ion implantation. Thereafter, as shown in FIG. 7, the polysilicon layer 41 is patterned to form a polysilicon layer 1 serving as a back gate electrode.
2, 17. Thus, the polysilicon layer 12 of the low-voltage MOS transistor Q1 and the polysilicon layer 17 of the high-voltage MOS transistor Q2 are formed in the same step.

Further, oxide films 22a, 22a are formed by CVD.
2b is deposited, for example, to a thickness of 100 nm. Subsequently, as shown in FIG. 8, a polysilicon film 20 of, eg, 5 to 10 μm is deposited by CVD. And, as shown in FIG.
This polysilicon film 20 is flattened by polishing, and FIG.
As shown in FIG. 0, the wafer is bonded to a silicon substrate (second silicon wafer) 1 by a wafer direct bonding technique.

Further, as shown in FIG. 11, the silicon substrate (first silicon wafer) 40 is ground and polished by, for example, selective polishing until the surface of the insulating film (oxide film) 21 is exposed.

Then, as shown in FIG.
The insulating films 5, 7 and the polysilicon layers 6, 8 are formed according to the I step. Thus, the low-voltage MOS transistor Q1
Polysilicon layer 6 and high voltage MOS transistor Q2
Is formed in the same step.

Next, as shown in FIG. 13, a through hole 42 for contacting the polysilicon layer 20 is opened by dry etching. Finally, as shown in FIG. 3, a wiring 30 to the polysilicon layer 20 is formed by a general wiring technique.
To form

As described above, this embodiment has the following features. (A) In the low-voltage MOS transistor Q1, a first gate electrode 6 is formed on a single-crystal silicon layer (first semiconductor layer) 3 having a source / drain / channel region via a first gate insulating film 5. And a second gate insulating film 5 having a thickness different from that of the first gate insulating film 5 under the single-crystal silicon layer (second semiconductor layer) 4 having source / drain / channel regions in the high-voltage MOS transistor Q2.
The second gate electrode 17 is arranged via the gate insulating film 2a.

Therefore, when forming the low-voltage and high-voltage MOS transistors Q1 and Q2 on the same substrate, a significant step is required when forming the first and second gate insulating films having different thicknesses. Can be done without increase. (B) Channel length L of low voltage MOS transistor Q1
1 and the channel length L2 of the high-voltage MOS transistor Q2.
Are made different from each other, which is practically preferable. (C) The low-voltage MOS transistor Q1 has the third gate electrode 12 formed in the same step as the second gate electrode 17, and the high-voltage MOS transistor Q2
Has a fourth gate electrode 8 formed in the same step as the first gate electrode 6, and has a third gate electrode 12
And the fourth gate electrode 8 are maintained at a predetermined potential, which is practically preferable. (Second Embodiment) Next, a second embodiment will be described with reference to the first embodiment.
The following description focuses on the differences from this embodiment.

In this embodiment, a support substrate is used as a gate electrode instead of the back gate in the first embodiment. FIG. 14 shows a schematic diagram thereof. In this case, impurities are introduced into the silicon substrate (support substrate) 1 for element isolation. For example, an impurity is introduced so that only the region used as the gate has one of N or P conductivity type, and the impurity diffusion region 50,
The gate region is separated by introducing an impurity having a conductivity type opposite to that of 51.

In the case where the conductivity type of the substrate 1 is opposite to that of the gate region (impurity diffusion regions 50 and 51) in advance, this impurity do not need to be introduced. In the case where a bonded substrate is used, this impurity introduction can be performed in advance by ion implantation or impurity introduction means such as phosphorus deposition on the second silicon substrate to be bonded. Alternatively, after the SOI region is formed by bonding and selective polishing, ion implantation may be performed at a high acceleration voltage so as to pass through the SOI layer. This method is also effective for a substrate in which impurities cannot be introduced into the supporting substrate in advance, such as a SIMOX substrate. (Third Embodiment) Next, a third embodiment will be described with reference to the first embodiment.
The following description focuses on the differences from this embodiment.

This embodiment is shown in the schematic diagram of FIG. In this example, the size of the polysilicon layer (back gate) 17 is set to be equal to or larger than the entire area of the SOI layer 4 forming the MOSFET.

That is, in the semiconductor device according to the first embodiment, in order to reduce the characteristic variation of the element due to the inability of self-aligned ion implantation of the source and drain to the back gate serving as the gate electrode, The size of the silicon layer (back gate) 17 is MOSF
By setting the area to be equal to or larger than the entire area of the SOI layer 4 forming the ET, stable characteristics can be obtained even if the ion implantation positions of the source and the drain are slightly shifted.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment.

FIG. 2 is a schematic plan view of the same semiconductor device.

FIG. 3 is a more specific cross-sectional view of the semiconductor device.

FIG. 4 is a cross-sectional view for explaining a manufacturing process.

FIG. 5 is a cross-sectional view for explaining a manufacturing process.

FIG. 6 is a cross-sectional view for explaining a manufacturing process.

FIG. 7 is a cross-sectional view for explaining a manufacturing process.

FIG. 8 is a cross-sectional view for explaining a manufacturing process.

FIG. 9 is a cross-sectional view for explaining a manufacturing process.

FIG. 10 is a sectional view for explaining a manufacturing process.

FIG. 11 is a sectional view for explaining a manufacturing process.

FIG. 12 is a cross-sectional view for explaining a manufacturing process.

FIG. 13 is a cross-sectional view for explaining a manufacturing process.

FIG. 14 is a schematic cross-sectional view of a semiconductor device according to a second embodiment.

FIG. 15 is a schematic cross-sectional view of a semiconductor device according to a third embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Insulating film, 2a ... Insulating film, 3 ... Single crystal silicon layer, 4 ... Single crystal silicon layer, 5 ... Insulating film,
6 polysilicon layer, 8 polysilicon layer, 9 source region, 10 drain region, 11 channel region, 12
... polysilicon layer, 13 ... source region, 14 ... drain region, 15 ... channel region, 17 ... polysilicon layer, Q
1: MOS transistor for low voltage, Q2: MO for high voltage
S transistor, L1 ... channel length, L2 ... channel length.

Continued on the front page (51) Int.Cl. ⁶ identification code FI H01L 29/78 626C 627D 627A

Claims (3)

[Claims] 1. A semiconductor device in which first and second MOS transistors are formed on a semiconductor substrate via an insulating film, wherein the first MOS transistor has a source, a drain,
A first gate electrode is disposed on a first semiconductor layer having a channel region via a first gate insulating film, and a second semiconductor layer having a source, drain, and channel region in a second MOS transistor A second gate electrode disposed under the first gate insulating film via a second gate insulating film having a thickness different from that of the first gate insulating film. 2. The semiconductor device according to claim 1, wherein a channel length of said first MOS transistor is different from a channel length of said second MOS transistor. 3. The semiconductor device according to claim 1, further comprising a third gate electrode formed in the same step as the second gate electrode in the first MOS transistor, wherein the third gate electrode is formed in the same step as the first gate electrode in the second MOS transistor. The semiconductor device according to claim 1, further comprising a fourth gate electrode formed, wherein the third gate electrode and the fourth gate electrode are kept at a predetermined potential.