JPH11330452A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the structure of a MOS transistor with small on-resistance, and its manufacturing method. SOLUTION: A specific region of a first insulation layer 10 is opened on a low-concentration N-type semiconductor layer 1, and a gate electrode 6 is formed in the opening, a drain offset region with a higher impurity concentration than that of the semiconductor layer 1 is formed close to a body region 2, by forming an intermediate concentration N-type drain offset region 9 and the medium-concentration P-type body region 2 with the gate electrode 6 as a mask, thus reducing on-resistance. In a succeeding process, a source region 3 is formed with the gate electrode 6 as a mask, and the source region 3 and the body region 2 are connected through a metal electrode 8.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a double diffusion type MOS transistor having a small on-resistance and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, as electronic devices have become multifunctional, semiconductor devices used therefor are required to have higher breakdown voltage and higher power, and double-diffused MOS transistors are employed. Opportunities are increasing. A semiconductor device (including an IC) in which the same double-diffused MOS transistor for high breakdown voltage, high power, and a bipolar transistor for controlling them can be integrated in one chip. ) Development is desired.

A conventional double-diffused MOS transistor will be described below with reference to FIG. 10, reference numeral 1 denotes a semiconductor layer of an N-type impurity formed on a main surface of a semiconductor substrate; 2, a body region of a P-type impurity formed in the semiconductor layer 1; The source region 4 made of impurities has a high N concentration.
A drain contact region formed of a type impurity, 5 an insulating film formed on a semiconductor substrate, 6 a gate electrode buried in the insulating film 5, 7 a metal electrode for a drain, 8 a metal electrode for a source It is.

In this double-diffused MOS transistor, the source region 3 and the body region 2 are connected by a metal electrode 8, and the drain contact region 4 is connected to a metal electrode 7 for the drain in order to improve the connection. The semiconductor layer 1 functions as a drain region. When a voltage is applied to the gate electrode 6, the gate electrode 6
A channel is formed in the vicinity of the surface of the body region 2 immediately below, and conducts between the drain and the source. When the gate voltage applied to the gate electrode 6 is controlled, the width of the channel is controlled, and the magnitude of the drain current can be controlled.

In manufacturing this double-diffused MOS transistor, the gate electrode 6 is used as a part of a mask, and after the body region 2 is used as a mask for ion implantation, the source region 3 is ion-implanted. It is also used as a mask when performing. When the drain contact region 4 is formed, an opening is formed in a predetermined region of the insulating film 5 formed on the surface of the semiconductor substrate, and then ion implantation is performed using the insulating film 5 as a mask.

[0006]

When various diffusion layers and electrodes are formed in a semiconductor chip, photolithography steps are provided in accordance with the number of steps, and patterning is performed using a mask dry plate. If only the above-mentioned double diffusion type MOS transistor is formed in the same chip, the number of mask dry plates used in the photolithography process may be about five. However, if different types of transistors are to be formed in the same chip, a photolithography process is required for each type of transistor, and the number of processes is inevitably increased. In a process with a large number of steps, when the mask for the diffusion step after several steps is combined after the initial diffusion step, the mask shift becomes large, so it is necessary to set a large separation between the diffusion steps. 10, the gate electrode 6 and the drain contact region 4
The distance between is set large. This is a factor that increases the variation in the electrical characteristics of the transistor.

In the case where a low-voltage high-voltage transistor and a high-voltage transistor are integrated in the same chip, the impurity concentration of the semiconductor layer 1 is reduced in order to secure the characteristics of the high-voltage transistor. At the same time, it is necessary to increase the thickness of the semiconductor layer 1. Further, when an attempt is made to form a high-power MOS transistor using the same semiconductor layer 1, there is a problem that the on-resistance of the high-power MOS transistor becomes large, and the current capability cannot be secured with a transistor having a small shape. I was

An object of the present invention is to solve such a problem, and an object of the present invention is to provide a high-power MOS transistor having a small on-resistance even when a thick low-concentration semiconductor layer is used as a drain region. And

A second object of the present invention is to provide a method for manufacturing a large power MOS transistor having a small on-resistance with a small variation.

[0010]

According to the present invention, there is provided a semiconductor device comprising:
A semiconductor substrate having a semiconductor layer of one conductivity type impurity on one main surface, a body region of an opposite conductivity type impurity deeply diffused in the semiconductor layer, and a semiconductor region of one conductivity type impurity diffused shallowly in the body region; A source region, a drain offset region of one conductivity type impurity diffused into the semiconductor layer and separated from the source region and close to the body region, and on a region between the source region and the drain offset region. And a gate electrode formed to cover the source region and the body region.

With this configuration, a channel is formed near the surface of the body region sandwiched between the drain offset region and the source region, and operates as a lateral MOS transistor. Since the drain offset region is formed close to the body region, the on-resistance of the MOS transistor can be reduced.

Further, a method of manufacturing a semiconductor device according to the present invention
A predetermined region of an insulating film on a semiconductor substrate having a semiconductor layer of a low-concentration one-conductivity-type impurity on one main surface is opened, and a gate insulating film and a gate electrode are selectively stacked on the semiconductor layer in the opening. A method of manufacturing a semiconductor device by forming a first opening and a second opening with the gate electrode interposed therebetween, and then introducing an impurity into the semiconductor layer by a self-alignment method. Forming a body region by selectively introducing an impurity of the opposite conductivity type from the opening; and forming a drain offset region by selectively introducing an impurity of the one conductivity type from the second opening. Forming a patterned resist layer on a semiconductor substrate, introducing a one-conductivity-type impurity using the resist layer and the gate electrode as a mask, and forming a high-concentration one-conductivity-type impurity source region in the body region; , Serial and forming a drain contact region of high concentration first conductivity type impurity into drain offset region, a structure for connecting and said after their process source region and the body region.

With this configuration, the body region and the source region are formed on one side of the gate electrode while the drain region is formed on the other side of the gate electrode by using the gate electrode as a mask. The semiconductor device can be manufactured without causing displacement, and keeping the lateral distance between the source region and the body region and the distance between the body region and the drain offset region substantially constant.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a semiconductor device according to a first embodiment comprises a semiconductor substrate having a semiconductor layer of an impurity of one conductivity type on one main surface and an impurity of an opposite conductivity type deeply diffused in the semiconductor layer. A body region, a source region of one conductivity type impurity diffused shallowly in the body region, and a source region of one conductivity type impurity diffused into the semiconductor layer in a distance from the source region and close to the body region. A drain offset region and a gate electrode formed so as to cover a region between the source region and the drain offset region are connected to the source region and the body region.

With this configuration, a channel is formed near the surface of the body region sandwiched between the drain offset region and the source region, and operates as a lateral MOS transistor. Since the drain offset region is formed close to the body region, the on-resistance of the MOS transistor can be reduced.

The semiconductor device according to the second embodiment includes a semiconductor substrate having a semiconductor layer of a low-concentration one-conductivity-type impurity on one main surface, and a medium-concentration reverse-conductivity-type impurity deeply diffused in the semiconductor layer. And a source region of a high-concentration one-conductivity-type impurity that is shallowly diffused in the body region; and a medium-concentration impurity that is separated from the source region and is deeply diffused in the semiconductor layer in contact with the body region. A drain offset region of a conductivity type impurity, a drain contact region of a high concentration one conductivity type impurity diffused shallowly in the drain offset region, and a region formed between the source region and the drain offset region. And a gate electrode connected to the source region and the body region.

According to this structure, the diffusion is expanded in the lateral direction as the drain offset region and the body region are deeply diffused, and collides with each other immediately below the vicinity of the center of the gate electrode to form a channel in the body region. Since the drain offset region having a high impurity concentration is formed adjacent to the MOS transistor, the ON resistance of the MOS transistor can be reduced.

Further, the semiconductor device according to the third embodiment has a semiconductor substrate of a reverse conductivity type having an epitaxial island of a low-concentration one conductivity type impurity on one principal surface thereof, and A buried diffusion region of high-concentration one-conductivity-type impurity formed in a predetermined region at the interface with the substrate; a body region of medium-concentration reverse-conductivity-type impurity deeply diffused in the epitaxial island; and a shallow diffusion in the body region. A source region of high-concentration one-conductivity-type impurity, a drain-offset region of medium-concentration one-conductivity-type impurity diffused in the epitaxial island, and a region formed between the source region and the drain-offset region. And a gate electrode connected to the source region and the body region.

According to this structure, the high impurity concentration drain offset region serves as a main current path for flowing a drain current, but the high impurity concentration buried diffusion region formed in the lower layer portion of the epitaxial island also functions as a current path. The current paths are in parallel, and the on-resistance can be sufficiently reduced.

Next, in a method of manufacturing a semiconductor device according to a fourth embodiment, a predetermined region of an insulating film on a semiconductor substrate having a semiconductor layer of a low-concentration one-conductivity-type impurity on one main surface is opened.
A gate insulating film and a gate electrode are selectively stacked on the semiconductor layer in the opening, and a first opening and a second opening are formed with the gate electrode interposed therebetween. A method of manufacturing a semiconductor device by introducing impurities by an align method, wherein a step of selectively introducing impurities of the opposite conductivity type from said first opening to form a body region; A step of forming a drain offset region by selectively introducing one conductivity type impurity, forming a patterned resist layer on the semiconductor substrate, and using the resist layer and the gate electrode as a mask to form the one conductivity type impurity. And forming a source region of the high concentration one conductivity type impurity in the body region and forming a drain contact region of the high concentration one conductivity type impurity in the drain offset region. Has the door, a structure for connecting the those steps after the source region and the body region.

With this structure, the body region and the source region are formed on one side of the gate electrode using the gate electrode as a mask, and the drain region is formed on the other side of the gate electrode. The semiconductor device can be manufactured without causing displacement, and keeping the lateral distance between the source region and the body region and the distance between the body region and the drain offset region substantially constant.

The manufacturing method of the invention according to the fifth embodiment is similar to that of the fourth embodiment.
In addition to the configuration of the manufacturing method of the embodiment, the diffusion of the drain offset region is advanced by heat treatment in each step so that the final diffusion length of the drain offset region is substantially equal to the width of the gate electrode. . Thus, after the impurity is introduced into the source region and the drain offset region with the gate electrode interposed therebetween, the source region and the drain offset region are positioned immediately below the center of the gate electrode due to the lateral spread of the diffusion accompanying the downward diffusion spread. A MOS transistor that is diffused to form a junction and has a low on-resistance can be formed.

In the manufacturing method according to the sixth embodiment, a predetermined region of an insulating film on a semiconductor substrate having a semiconductor layer of a low-concentration one-conductivity-type impurity on one main surface is opened, and then the semiconductor layer in the opening is opened. The gate insulating film and the gate electrode are selectively laminated on
A first step of forming a first opening and a second opening with the gate electrode interposed therebetween, and then covering the at least the first opening with a first resist layer to form the second opening; A second step of removing the first resist layer and performing a heat treatment to form a drain offset region in the semiconductor layer after ion-implanting one conductivity type impurity from a portion, and then forming at least the second opening After the portion is covered with a second resist layer and an impurity of the opposite conductivity type is ion-implanted from the first opening, the second resist layer is removed and heat treatment is performed to form a body region in the semiconductor layer. Step 3, and then forming a patterned third resist layer on the semiconductor substrate, and using a mask of the third resist layer and the gate electrode to form a third opening in the body region. Forming and the drain A fourth step of forming a fourth opening by the third resist layer in emissions offset region,
Next, one-conductivity-type impurities are ion-implanted through the third opening and the fourth opening to form a high-concentration one-conductivity-type impurity source region at a location corresponding to the third opening. And a fifth step of forming a drain contact region of high-concentration one-conductivity-type impurity at a position corresponding to the fourth opening, and after these steps, connecting the source region and the body region. Configuration.

With this configuration, the drain offset region is formed by ion implantation from the second opening using the first resist layer and the gate electrode as a mask, and using the second resist layer and the gate electrode as a mask. A body region is formed by performing ion implantation from the first opening, and thereafter, the third opening and the fourth opening are formed by using a mask of the third resist layer and the gate electrode formed on the semiconductor substrate. And a source region and a drain contact region are formed by ion-implanting high-concentration one-conductivity-type impurities through the third and fourth openings. Since each diffusion region is formed in a self-aligned manner using the gate electrode as a mask, the diffusion regions are formed close to each other while maintaining a relatively constant relative distance between the diffusion regions, thereby reducing the ON resistance of the MOS transistor. It is possible to reduce the manufacturing variation.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a sectional view showing a completed semiconductor device according to an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a semiconductor layer of a low-concentration N-type impurity formed on a semiconductor substrate; 2, a body region of a medium-concentration P-type impurity; 3, a source region of a high-concentration N-type impurity; A drain contact region, 6 a gate electrode, 7 a metal electrode for the drain, 8
Is a metal electrode for a source, 9 is a drain offset region by a medium concentration N-type impurity, 10 and 11 are insulating films, 12
Is a gate insulating film. The low concentration is, for example, in the range of 1 × 10 ¹⁴ to 1 × 10 ¹⁶ cm ⁻³ , and the medium concentration is 1 × 10 ¹⁶ to 1 × 10 ¹⁸ cm 3.
^The high concentration in the range of ^-3 is an impurity concentration of 1 × 10 ¹⁸ cm ⁻³ or more.

The semiconductor layer 1 is formed of low-concentration impurities, and the impurity relationship with each of the other diffusion layers is unified into one conductivity type and the opposite conductivity type, which is the opposite relationship. If so, it may be a P-type impurity or an N-type impurity. In this embodiment, an example is described in which a low-concentration N-type impurity layer is used. An N-type epitaxial layer formed on a P-type semiconductor substrate may be used. The N-type well layer may be formed, or an N-type semiconductor substrate in which N-type impurities are introduced into the entire substrate may be used.

In the semiconductor device shown in FIG. 1, ions are implanted using the gate electrode 6 as a mask, and the body region 2 of the medium-concentration P-type impurity and the source region of the high-concentration N-type impurity are interposed between the gate electrode 6. 3 and a drain offset region 9 made of a medium concentration N-type impurity is formed on the other side. Further, since the ion-implanted impurities are diffused in the vertical and horizontal directions by the heat treatment, the body region 2 and the drain offset region 9 are configured to be in contact with the gate electrode 6 immediately below the center thereof. A drain contact region 4 made of a high-concentration N-type impurity is formed in the drain offset region 9. A drain electrode is taken out from the metal electrode 7 formed on the drain contact region 4 and formed on the source region 3. The source electrode is taken out from the metal electrode 8 to form a double diffusion MOS transistor.

In this configuration, the metal electrode 8 for the source is grounded, a load resistance (not shown) is connected to the metal electrode 7 for the drain, a predetermined positive potential is applied, and a control voltage is applied to the gate electrode 6. And the source region 3 and the drain offset region 9
A channel region is formed near the surface of the body region 2 sandwiched between the drain region and the drain region. The magnitude of the drain current (current between the drain and the source) is varied according to the control voltage (input signal), and a signal amplified from the metal electrode 7 for the drain can be taken out. Works as

The current path through which the drain current mainly flows is the drain contact region 4 → the drain offset region 9 → the channel region (near the surface of the body region 2) → the source region 3, but the channel region (the body region 2).
(In the vicinity of the surface of the transistor), the drain offset region 9 of a relatively high concentration of N-type impurity is provided, so that the on-resistance when turned on by the transistor operation is small, and the device structure drives a large current. It is suitable as.

The double diffusion type MOS transistor shown in FIG. 1 employs a form in which the source region 3 and the body region 2 are short-circuited by the metal electrode 8. This is performed in order to stabilize the operation of the transistor by giving an order, and is a configuration in a general use state. However, the source region 3 and the body region 2 may be separated and taken out to separate metal electrodes (not shown). In this case, between the source region 3 and the body region 2, several tens (Ω) to
Connecting several (KΩ) external resistors (not shown) has the following advantages. When a switching operation is performed by connecting an inductive load to the drain, the drain potential may be lower than the potential of the body region 2. At that time, the body region 2 and the drain (the semiconductor layer 1 and the drain offset region 9)
PN junction (parasitic diode) conducts in the forward direction. The magnitude of the current that such a parasitic element conducts is
It can be limited by the external resistance connected between source region 3 and body region 2.

More specifically, in a state where a plurality of epitaxial islands are formed on a single semiconductor substrate, and a similar double-diffused MOS transistor is formed in the islands, a semiconductor integrated circuit device is formed. When the parasitic diode becomes forward conducting, it triggers and the latch-up phenomenon occurs at a considerable frequency. However, when an external resistor is connected between the source region 3 and the body region 2 as described above, conduction of the parasitic diode can be suppressed, and the latch-up phenomenon can be eliminated.

Next, a method for manufacturing the above-described semiconductor device will be described with reference to FIGS.

FIG. 1 is a cross-sectional structure diagram of a completed semiconductor device, and FIGS. 2 to 6 are process cross-sectional views for explaining a process flow. The manufacturing method will be described in the order of the processes. First, in a first step, a first surface is formed on a surface of a semiconductor substrate having a semiconductor layer 1 of a low concentration N-type impurity on one main surface.
After the insulating film 10 is formed, a predetermined portion of the insulating film 10 is opened. Then, an insulating film for the gate insulating film 12,
A polycrystalline silicon film serving as a gate electrode 6 is sequentially deposited and laminated thereon (see FIG. 2). Then, the deposited layer of the insulating film and the polycrystalline silicon film is patterned to form the first layer.
The deposited layer of the gate insulating film 12 and the gate electrode 6 is selectively left at the center of the opening so as to divide the opening of the insulating film 10. Then, a first opening A and a second opening B exposing the main surface of the semiconductor layer 1 are formed with the gate electrode 6 interposed therebetween.

Next, in a second step, after a first resist layer 13 is applied and formed on the semiconductor substrate (see FIG. 3),
The first resist layer 13 is exposed so that the second opening B is exposed.
Is slightly larger than the second opening B, and arsenic ions are implanted through the second opening B with the first opening A covered with the first resist layer 13 (FIG. 4). See).
After that, the first resist layer 13 is removed, and the drain offset region 9 is formed below the second opening B by heat treatment.

Next, in a third step, a second resist layer 14 is applied and formed on the semiconductor substrate, and then the second resist layer 14 is patterned so that the first opening A is exposed. The second resist layer 14 is opened larger than the first opening A, and the second opening B is formed in the second resist layer 1.
Cover with 4. In this state, after boron ions are implanted through the first opening A, the second resist layer 14 is removed. Then, heat treatment is performed to form the body region 2 below the first opening A. The diffusion of the drain offset region 9 also proceeds by the heat treatment at this time (see FIG. 5).

Next, in a fourth step, a third resist layer 15 is applied and formed on the semiconductor substrate, and thereafter, the third resist layer 15 is patterned. As a result, the gate electrode 6
The third resist layer 15 is patterned so that a third opening 16 is formed in the body region 2 so that the end of the third resist layer 15 is exposed, while a fourth opening 17 is formed in the drain offset region 9. Then, the third resist layer 15 is patterned (see FIG. 6). Then, after arsenic ions are implanted through the third opening 16 and the fourth opening 17, the third resist layer 15 is entirely removed and a heat treatment is performed to form the source region 3 of the high-concentration N-type impurity. Then, a drain contact region 4 of a high concentration N-type impurity is formed.

In a subsequent step, after the second insulating film 11 is formed on the semiconductor substrate, the opening of the second insulating film 11 is formed at a position straddling the body region 2 and the source region 3 and at a position of the drain contact region 4. Are formed, and a source electrode 8 and a drain electrode 7 are formed corresponding to the openings, thereby completing the double diffusion type MOS transistor shown in FIG.

Here, the channel length of the semiconductor device of the present invention will be described in detail with reference to FIG.

FIG. 7 is a schematic sectional view of a semiconductor device according to the present invention, in which only essential parts are shown. 7, 1 is a semiconductor layer, 2 is a body region, 3 is a source region, 4 is a drain contact region, 6 is a gate electrode, 9 is a drain offset region, W is the gate width of the gate electrode 6, X
j is the vertical diffusion length of the drain offset region, and CL is the channel length of the double diffusion MOS transistor.

First, arsenic ions are implanted into the semiconductor layer 1 using the left end of the gate electrode 6 in FIG. 7 as a mask. At this time, arsenic ions are removed from the gate electrode 6 except immediately below the gate electrode 6.
Is introduced in the vicinity of the surface of the semiconductor layer 1 adjacent to the drain offset region 9, and the drain offset region 9 is diffused by a subsequent heat treatment. Boron ions are implanted into the semiconductor layer 1 using the right end of the gate electrode 6 in FIG. 7 as a mask, and boron is introduced into the vicinity of the surface of the semiconductor layer 1 adjacent to the gate electrode 6 except immediately below the gate electrode 6. The body region 2 is formed by a subsequent heat treatment.
Is formed by diffusion. The diffusion of the drain offset region 9 and the diffusion of the body region 2 are performed both in the vertical direction and the horizontal direction.
The horizontal diffusion progresses about 70% of the vertical diffusion. Therefore, the lateral diffusion of the drain offset region 9 proceeds to the semiconductor layer 1 immediately below the gate electrode 6 toward the body region 2, while the lateral diffusion of the body region 2 directly extends below the gate electrode 6 toward the drain offset region 9. Proceed to semiconductor layer 1. Final diffusion length X of drain offset region 9
j is the gate width W of the gate electrode 6 (4 μm in the experimental example)
When the diffusion in the vertical direction is substantially equal to that of the gate electrode 6, the lateral diffusion of the body region 2 and the drain offset region 9 collides near the center of the gate electrode 6, and those having a high impurity concentration form a PN junction. Since the diffusion progress of arsenic is slow, the diffusion progress of boron catches up with the progress of arsenic diffusion even if the ion implantation for the drain offset region 9 is performed first and then the boron ions for the body region 2 are implanted. Finally, the diffusion length of the body region 2 and the diffusion length of the drain offset region 9 become substantially equal.

The source region 3 is diffused by performing ion implantation and heat treatment for the body region 2 and then implanting and heat-treating arsenic ions using the right end of the gate electrode 6 in FIG. 7 as a mask. 3, the diffusion regions of the source region 3 and the body region 2 do not overlap with each other.

Thus, the body region 2, the source region 3 and the drain offset region 9 are diffused,
When a predetermined bias is applied to the gate electrode 6, the source region 3 and the drain offset region 9, a channel is formed near the surface of the body region 2 immediately below the gate electrode 6, and the MO
It operates as an S transistor. The channel length CL of this MOS transistor depends on the source region 3 and the body region 2
Corresponds to the distance from the PN junction formed by the above to the PN junction formed by the body region 2 and the drain offset region 9, and is less than half the gate length W of the gate electrode 6.

The above-described method of manufacturing a double-diffused MOS transistor has been described as an example of a discrete type in which one double-diffused MOS transistor is formed on one semiconductor substrate. However, the present invention is also applicable to a semiconductor integrated circuit device in which a plurality of MOS transistors or a MOS transistor and a bipolar transistor are formed on one semiconductor substrate. That is, if a well region (corresponding to the semiconductor layer 1) of an N-type impurity having a higher concentration is formed in a plurality of places on a semiconductor substrate having a low concentration of a P-type impurity, and the above-described process is performed in the well region, A plurality of MOS transistors can be integrated on one semiconductor substrate.

Further, the above-mentioned low-concentration N-type semiconductor layer 1 (epitaxial layer) is electrically separated by employing an oxide film separation technique or a PN junction separation technique so that a plurality of epitaxial islands can be converted to a low-concentration P-type. A plurality of MOS transistors can also be integrated on one semiconductor substrate by forming them on a semiconductor substrate and performing the above-described steps in the plurality of epitaxial islands.

Next, another embodiment of the present invention will be described with reference to FIG. 8, the same parts as those in the embodiment of FIG. 1 are denoted by the same reference numerals, 2 is a body region of a medium concentration P-type impurity, 3 is a source region of a high concentration N-type impurity, and 4 is a high concentration N-type impurity. A drain contact region of an impurity, 6 a gate electrode, 7 a metal electrode for a drain, 8 a metal electrode for a source, 9 a drain offset region of a medium concentration N-type impurity, 19 a semiconductor substrate of a low concentration P-type impurity, 20 is an epitaxial island of low concentration N-type impurity, 21 is an isolation layer, 22
Denotes an insulating film, and the insulating film 22 formed in several steps is shown in a simplified manner. Also, the separation layer 21
The epitaxial layer is divided into a plurality of islands and electrically isolated from each other. The epitaxial layer 20 may be formed of a P-type impurity semiconductor having a conductivity type opposite to that of the epitaxial island 20 and may be separated by a PN junction isolation method. Alternatively, they may be separated by an insulator such as an oxidizing substance or a dielectric substance.

In the embodiment shown in FIG. 8, an epitaxial layer of a low-concentration N-type impurity is deposited on a main surface of a semiconductor substrate 19 of a low-concentration P-type impurity. This is a case where an island 20 (corresponding to the semiconductor layer 1 of the embodiment of FIG. 1) is formed, and the above-described double-diffused MOS transistor is formed in the epitaxial island 20. However, in the above embodiment, the drain offset region 9 is formed by implanting arsenic ions.
In this embodiment, the drain offset region 9 is formed by performing a heat treatment after phosphorus ions are implanted. In this respect, unlike the above-described embodiment, in the subsequent steps, similarly to the above-described embodiment, heat treatment is performed after boron ions are implanted to form the body region 2, and a predetermined portion in the body region 2 and the drain region are formed. Arsenic ions are implanted into predetermined locations in the offset region 9 to form the source region 3 and the drain contact region 4.

Therefore, the diffusion speed of phosphorus is higher than that of arsenic and almost equal to the diffusion speed of boron. Since the ion implantation of phosphorus is performed before the body region 2 is formed, the drain offset region 9 in the embodiment of FIG. Are diffused deeper than body region 2. Since the drain offset region 9 contacts the end of the body region 2 over a wide range, the MOS transistor can be operated with a small on-resistance.

This embodiment is effective when the thickness of the epitaxial island 20 is 10 μm or more, and the device for high breakdown voltage is formed by increasing the thickness of the epitaxial island and separating the other epitaxial islands insulated by the separation layer 21. (Not shown)
On the other hand, a double-diffused MOS transistor can be formed on the epitaxial island 20 to form a semiconductor integrated circuit device that drives a large current. A buried diffusion region described later (23 in FIG. 9) , The on-resistance can be reduced.

Next, another embodiment of the present invention will be described with reference to FIG. 9, the same parts as those in the embodiment of FIG. 1 are denoted by the same reference numerals, 2 is a body region of a medium concentration P-type impurity, 3 is a source region of a high concentration N-type impurity, 6 is a gate electrode, 7 Is a metal electrode for a drain, 8 is a metal electrode for a source, 19 is a semiconductor substrate of a low concentration P-type impurity, 2
0 is an epitaxial island of low concentration N-type impurity, 21 is an isolation layer, 22 is an insulating film, 23 is a buried diffusion region of high concentration N-type impurity, and 24 is a drain offset region of medium concentration N-type impurity. Shows a simplified view of what is formed several times. The isolation layer 21 is for dividing the epitaxial layer into a plurality of islands and electrically isolating them from each other. The isolation layer 21 is made of a P-type impurity semiconductor having a conductivity type opposite to that of the epitaxial island 20 and is formed by a PN junction isolation method. And may be separated by an insulator such as an oxidizing substance or a dielectric substance.

Next, in the embodiment shown in FIG.
High concentration N in a predetermined region on the main surface of
After diffusing the n-type impurity, an epitaxial of low-concentration N-type impurity is deposited, and a high-concentration N-type impurity is
A buried diffusion region 23 of the type impurity is formed. afterwards,
An isolation layer 21 is selectively formed, and a predetermined portion of the epitaxial layer is partitioned to form an epitaxial island 20 (corresponding to the semiconductor layer 1 in the embodiment of FIG. 1). This is an example in which a MOS transistor is formed. In this case, the epitaxial island 20 is self-aligned using the gate electrode 6 as a mask.
After ion implantation of boron into the body region 2 of the medium concentration P-type impurity, arsenic ion implantation is performed in a self-aligned manner using the gate electrode 6 as a mask, and a high concentration N-type The source region 3 of the impurity and the drain offset region 24 of the medium concentration N-type impurity are formed shallowly in the epitaxial island 20. This embodiment is different from the embodiment of FIG. 8 in that the drain offset region 9 having a large diffusion length is eliminated, and the drain contact region 4 is extended to just below the end of the gate electrode 6 so that the drain offset region 9 having a small diffusion length is formed. 8 in that a buried diffusion region 23 of a high-concentration N-type impurity is provided in a lower region of the epitaxial island 20, in other words, in a predetermined region at the interface between the epitaxial island 20 and the semiconductor substrate 19. Different from form.

In this embodiment, the epitaxial thickness is 6 μm.
This is effective when a double-diffused MOS transistor is formed on a thin epitaxial island 20 having a thickness of not more than m. That is,
Since the current supplied from the drain metal electrode 7 flows through the drain offset region 24 of the medium concentration N-type impurity to the vicinity of the body region 2, the resistance component of the current path is reduced. On the other hand, the drain offset region 2 is placed just below the metal electrode 7 so as to be separated from the metal electrode 7.
4 → Epitaxial island 20 → Current is transmitted downward along the path of the buried diffusion region 23, current is transmitted laterally through the buried diffusion region 23 of the high concentration N-type impurity, and the buried diffusion immediately below the channel of the body region 2 is formed. The resistance component of the bypass route, which is transmitted upward in the route of the region 23 → the epitaxial island 20 → the body region 2, can also be reduced, and the on-resistance can be reduced. Therefore, when the thickness of the epitaxial layer is increased, for example, it exceeds 10 μm and becomes 20 μm.
When the thickness is increased, the effect of reducing the on-resistance is almost eliminated.

Another embodiment will be described with reference to FIGS. 8 and 9. FIG. In the embodiment of FIG. 8, the case where the epitaxial thickness is 10 μm and the high withstand voltage device is formed on the other islands separated by the separation layer 21 has been described above. At this time, a semiconductor integrated circuit device utilizing a multilayer wiring process of forming an interlayer insulating film (not shown) on the insulating film 22 and the metal electrodes 7 and 8 of FIG. A circuit that does not apply a large voltage between the source metal electrode 8 and the drain electrode 7 but provides a high potential to the epitaxial island 20 may be integrated in the semiconductor integrated circuit device. At this time, a large voltage may be applied between the metal electrode 7 and the wiring running thereover, which may cause a problem that the interlayer insulating film is damaged. In this case, a buried diffusion region (corresponding to 23 in FIG. 9) is formed in a predetermined region at the interface between the N-type epitaxial island 20 and the P-type semiconductor substrate 19 in FIG. The PN junction with the region 23 is broken down, and the breakdown phenomenon limits the potential of the epitaxial island 20 to prevent damage to the interlayer insulating film. By the function of 9, the on-resistance can be reduced.

[0053]

As described above, the semiconductor device of the present invention has the following features.
Since the drain offset region with a higher impurity concentration than the semiconductor layer is formed close to the body region,
The resistance component from the drain metal electrode to the channel region can be reduced, the ON resistance of the MOS transistor can be reduced, and a large current can be driven.

The method of manufacturing a semiconductor device according to the present invention
Since the body region, the source region, and the drain offset region are formed by a self-alignment method using the gate electrode as a mask, a MOS transistor having a small on-resistance and a small on-resistance can be easily manufactured.

[Brief description of the drawings]

FIG. 1 is a cross-sectional structural view when a semiconductor device according to an embodiment of the present invention is completed.

FIG. 2 is a process cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a process sectional view for illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;

FIG. 4 is a process cross-sectional view for explaining the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 5 is a process sectional view for illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 6 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;

FIG. 7 is an essential part cross-sectional structure diagram for explaining diffusion length Xj in the embodiment.

FIG. 8 is a sectional structural view of a semiconductor device according to another embodiment of the present invention.

FIG. 9 is a sectional structural view of a semiconductor device according to another embodiment of the present invention.

FIG. 10 is a sectional structural view of a conventional semiconductor device.

[Explanation of symbols]

 Reference Signs List 1 low-concentration N-type semiconductor layer 2 P-type body region 3 high-concentration N-type source region 4 high-concentration N-type drain contact region 6 gate electrode 7 metal electrode for drain 8 metal electrode for source 9 drain offset region DESCRIPTION OF SYMBOLS 10 1st insulating film 11 2nd insulating film 12 Gate insulating film

Claims (8)

[Claims] 1. A semiconductor substrate having a semiconductor layer of one conductivity type impurity on one main surface, a body region of an opposite conductivity type impurity deeply diffused in the semiconductor layer, and a shallow diffusion in the body region. A source region of one conductivity type impurity, a drain offset region of one conductivity type impurity separated from the source region and diffused in the semiconductor layer in proximity to the body region; and the source region and the drain offset region. And a gate electrode formed so as to cover a region between the source region and the body region. 2. A semiconductor substrate having a semiconductor layer of a low-concentration one-conductivity-type impurity on one main surface; a body region of a medium-concentration reverse-conductivity-type impurity deeply diffused in the semiconductor layer; A source region of a high-concentration one-conductivity-type impurity diffused shallowly; a drain-offset region of a medium-concentration one-conductivity-type impurity that is separated from the source region and is deeply diffused into the semiconductor layer in contact with the body region; A drain contact region of high-concentration one conductivity type impurity diffused shallowly in the drain offset region; and a gate electrode formed so as to cover a region between the source region and the drain offset region. A semiconductor device in which a source region and the body region are connected. 3. The semiconductor device according to claim 2, wherein the diffusion length of the drain offset region is substantially equal to the gate width of the gate electrode. 4. A semiconductor substrate of a reverse conductivity type having an epitaxial island of a low concentration one conductivity type impurity on one principal surface; a body region of a medium concentration reverse conductivity type impurity deeply diffused in the epitaxial island; A source region of high-concentration one-conductivity-type impurity diffused shallowly in the region; a drain-offset region of middle-concentration one-conductivity-type impurity deeply diffused in the epitaxial island in contact with the body region and separated from the source region. A drain contact region of high-concentration one-conductivity-type impurity diffused shallowly in the drain offset region; and a gate electrode formed so as to cover a region between the source region and the drain offset region. A semiconductor device in which the source region and the body region are connected. 5. A semiconductor substrate of an opposite conductivity type having an epitaxial island of a low-concentration one-conductivity-type impurity on one principal surface, and formed in a predetermined region at an interface between the semiconductor substrate and a lower layer of the epitaxial island. A buried diffusion region of one conductivity type impurity, a body region of medium concentration reverse conductivity type impurity deeply diffused in the epitaxial island, and a source region of high concentration one conductivity type impurity diffused shallowly in the body region. A drain offset region of a medium-concentration one-conductivity-type impurity that is shallowly diffused into the epitaxial island in a distance from the source region and close to the body region; and covers a region between the source region and the drain offset region. And a gate electrode formed as described above, wherein the source region and the body region are connected to each other. 6. A predetermined region of an insulating film on a semiconductor substrate having a semiconductor layer of a low-concentration one-conductivity-type impurity on one principal surface is opened.
A gate insulating film and a gate electrode are selectively stacked on the semiconductor layer in the opening, and a first opening and a second opening are formed with the gate electrode interposed therebetween. A method of manufacturing a semiconductor device by introducing impurities by an align method, wherein a step of selectively introducing impurities of the opposite conductivity type from the first opening to form a body region, and a step of forming the second opening A step of forming a drain offset region by selectively introducing one conductivity type impurity, forming a patterned resist layer on the semiconductor substrate, and using the resist layer and the gate electrode as a mask to form a one conductivity type impurity. By introducing, a source region of high concentration one conductivity type impurity is formed in the body region, and a drain contact region of high concentration one conductivity type impurity is formed in the drain offset region. And a degree, a method of manufacturing a semiconductor device that the source region after their process and characterized by connecting the said body region. 7. The method according to claim 6, wherein the diffusion of the drain offset region is advanced by the heat treatment in each step so that the final diffusion length of the drain offset region becomes substantially equal to the width of the gate electrode. A method for manufacturing a semiconductor device. 8. After opening a predetermined region of an insulating film on a semiconductor substrate having a semiconductor layer of a low concentration one conductivity type impurity on one main surface, a gate insulating film and a gate electrode are formed on the semiconductor layer in the opening. Selectively laminated, and the first
Forming a first opening and a second opening, and then covering at least the first opening with a first resist layer and ion-impacting one conductivity type impurities from the second opening. After the implantation, a second step of removing the first resist layer and performing a heat treatment to form a drain offset region in the semiconductor layer. Next, at least the second opening is formed by a second resist layer. A third step of forming a body region in the semiconductor layer by removing the second resist layer and performing a heat treatment after ion-implanting an impurity of the opposite conductivity type through the first opening to cover the semiconductor layer; Forming a patterned third resist layer on the semiconductor substrate, forming a third opening in the body region by using a mask of the third resist layer and the gate electrode, and forming a drain offset region; Before in A fourth step of forming a fourth opening with a third resist layer; and then ion-implanting one conductivity type impurity through the third opening and the fourth opening. Forming a source region of high-concentration one-conductivity-type impurity at a location corresponding to the third opening and forming a drain contact region of high-concentration one-conductivity-type impurity at a location corresponding to the fourth opening; And a method of connecting the source region and the body region after the steps.