JPH1041512A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can suppress decreasing of operating speed due to a voltage drop by a resistance element of wiring by means of a new constitution. SOLUTION: A single crystal silicon layers 8, 9 and 10 are formed on a silicon substrate 5 via a silicon oxide film 7. MOSFETs 13, 14 and 15 are constituted of the single crystal silicon layers 8, 9 and 10 and an impurity doped polisilicon layer (back gate electrode) 16 which is electrically insulated from other parts is provided at the position which faces a channel region of the MOSFETs at least. Each MOSFET is divided at 5 regions a to c according to lengths of power source wirings and threshold voltage of a MOSFET at the region of which wiring length is the longer is made the lower by varying film thicknesses t1, t2 and t3 of the silicon oxide films 7.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a power supply voltage is supplied to a plurality of MOSFETs formed on a substrate by power supply wiring, and more particularly, to a portable device constituted by a large-area circuit by a gate array system. DS for use etc.
This technology is effective for semiconductor devices such as P and CPU.

[0002]

2. Description of the Related Art In information communication device ICs, high speed
A low power consumption operation is an essential technology, and a thin film SOIMOSFE in which a MOSFET is formed on a silicon thin film on an insulating film.
T can completely separate the element region by etching, and has an effect of suppressing the short channel effect by the base insulating film, reducing the junction capacitance of the source / drain, and improving the mobility by relaxing the electric field in the vertical direction. It is the best device for the application. In particular, a bonded substrate using wafer direct bonding as an SOI structure substrate is SIMOX (Separation by Implanted Oxygen) using oxygen ion implantation.
Since the crystallinity of the silicon layer is superior to that of the above, the substrate also exhibits excellent characteristics in the above characteristics, and thus is a substrate more suitable for ICs for information communication equipment. S on the bonded substrate
The variation in OI film thickness is large.
The OSFET has a problem that the variation in threshold voltage is large, but a second gate electrode (back gate electrode) is provided at least in a region facing the channel region of the MOSFET in the insulating film, and a voltage is applied thereto. Or by injecting a charge and holding it,
It is possible to adjust the threshold voltage of the SFET (JP-A-2-294076, JP-A-6-22).
No. 4433).

Further, the circuit scale increases with the demand for high processing performance, but on the other hand, a gate array system which realizes a short delivery time is effective due to intensifying market competition.
In a large-scale integrated circuit using a gate array, the chip area increases, so that the length of a power supply wiring for supplying a power supply voltage to each element increases. For example, in a 1 cm square chip, when a power supply voltage is supplied to an element in a certain region in the chip where the wiring length from the power supply terminal is about 5 mm,
When the wiring material is Al (aluminum) with ρ _s = 60 mΩ / □ and the wiring width is 10 μm, the wiring resistance is 300
mΩ, the current consumption during operation of this element is 20 m
In the case of A, a voltage drop of 0.6 V occurs. That is, even in the same chip, elements near the center of the chip are effectively driven under a low power supply voltage due to a voltage drop due to the resistance component of the wiring. The delay time T of the inverter is T∝1 / (V
_DD -V _th) is represented by ^2, since the delay time T with decreasing power supply voltage V _DD when the threshold voltage V _th is constant is increased, the operation speed of the circuit delay time in this region Is rate-limiting, and the net operating speed of the entire circuit is reduced.

In order to prevent the operation speed from decreasing,
A technique for suppressing the voltage drop is effective. For this purpose, the entire circuit is surrounded by wiring having a sufficiently wide width and negligible resistance components, and a normal wiring (branch line) for supplying a power supply voltage to each MOSFET uses one or two layers of wiring with the thick wiring as a main line. The entire circuit is arranged in stripes or meshes at appropriate intervals, and each MO constituting the circuit is arranged.
The SFET can be connected to the nearest branch line to minimize the substantial wiring distance and thereby reduce the voltage drop. Further, by arranging a thick wiring inside the circuit and using this as a main line, it is possible to further suppress the voltage drop.

[0005]

However, when a striped power supply wiring of one layer wiring is used to suppress the voltage drop, the voltage drop can be suppressed only in a direction parallel to the extending direction of the power supply wiring. Can not. Also, when a mesh-like power supply wiring with two-layer wiring is used, the effect of suppressing the voltage drop near the center of the chip is still small, although better than the case of single-layer wiring, and the power supply wirings intersect closely. Therefore, the degree of freedom in circuit layout is reduced. Further, when a thick power supply wiring (main line) is arranged inside the circuit, the effect of suppressing the voltage drop is great, but since the power supply wiring region cannot be formed with a MOSFET, the degree of freedom in circuit layout is reduced. When the degree of freedom in circuit layout is small as described above, for example, in a gate array, the use efficiency of gates is reduced, and a larger number of MOs are used as a master slice.
There is a problem that the chip area increases because it is necessary to prepare an SFET.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device capable of suppressing a reduction in operation speed due to a voltage drop due to a resistance component of a wiring with a novel configuration.

[0007]

According to a first aspect of the present invention, in a semiconductor device having an SOI structure and having a back gate electrode, each MOSFET is formed in a plurality of regions according to the length of a power supply wiring. Divided into MOSFE
The thickness of the insulating film between the channel region of T and the back gate electrode is varied for each region, so that MOS
The feature is that the threshold voltage is lower for FETs. Therefore, the MOSFET in the region where the power supply wiring is longer has a more effective drop in the power supply voltage, but since the threshold voltage is lower, the decrease in the operation speed due to the drop in the power supply voltage is prevented. Thus, it is possible to suppress a decrease in operation speed due to a voltage drop due to a resistance component of the wiring.

According to a second aspect of the present invention, in a semiconductor device employing an SOI structure and having a back gate electrode, each MOSFET is divided into a plurality of regions according to the length of the power supply wiring. A back gate electrode is provided independently for each region, and a voltage applied to the back gate electrode or an amount of injected charge is made different for each region, so that a MOSFET in a region having a longer wiring has a lower threshold voltage. Therefore, the MO in the region where the power supply wiring is long is
An SFET causes a more effective drop in power supply voltage, but the threshold voltage is lower, so that a decrease in operating speed due to a drop in power supply voltage is prevented. Thus, it is possible to suppress a decrease in operation speed due to a voltage drop due to a resistance component of the wiring.

According to a third aspect of the present invention, each MOSFET
Is divided into a plurality of areas according to the length of the power supply wiring, and the MOS
By changing the impurity concentration or the type of impurity in the channel region of the FET for each region, MO
The feature is that the threshold voltage is lower for SFETs. Therefore, the MOSFET in the region where the power supply wiring is longer has a more effective drop in the power supply voltage, but since the threshold voltage is lower, the decrease in the operation speed due to the drop in the power supply voltage is prevented. Thus, it is possible to suppress a decrease in operation speed due to a voltage drop due to a resistance component of the wiring.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view of a chip (semiconductor substrate) 1. The chip 1 has a vertical and horizontal dimension of about 1 cm × 1 cm, and the semiconductor device of the present embodiment constitutes a CMOS gate array having a relatively large chip area.

A power supply wiring 2 having a rectangular ring shape is arranged in a peripheral portion of the chip 1, and the power supply wiring 2 is connected to a power supply pad 3 (power supply terminal) arranged in a peripheral portion of the chip 1. Further, the power supply wiring 2 is wide enough so that the resistance component can be ignored and is a trunk line. In a circuit formation region surrounded by the power supply wiring 2, a plurality of power supply wirings (branch lines) 4 having a width smaller than that of the power supply wiring (main line) 2 are extended in parallel and at equal intervals, and these branch lines 4 are connected to the main line 2. Have been. That is, the wirings 4 are arranged in stripes. Here, each MOS
Assuming that the operation rates of the FETs are equal and the amount of current flowing through the branch line is equal, as shown in FIG. 1, the potential gradient (effective power supply voltage) of the branch line 4 is lowest at the center, high at both ends, and linear between the ends. It becomes a gradient.

Each of the MOSFETs is supplied with a power supply voltage V _DD from a nearest power supply wiring (branch line) 4. That is, the voltage applied to the source (or drain) of each MOSFET constituting a circuit
4 supplied. The number of the power supply lines (branch lines) 4 is large, and the voltage drop is small as the interval is as narrow as the distance between the MOSFETs.

Although the branch lines 4 are arranged in the horizontal direction in FIG. 1, they may be arranged in stripes in the vertical direction. Here, the voltage drop due to the resistance component of the power supply wiring will be described. The wiring length from the power supply pad 3 (power supply terminal) is 5 mm, Al (aluminum) with ρ _s = 60 mΩ / □ is used as the wiring material, and the wiring width is 10 μm. In this case, the wiring resistance is 300 mΩ. Therefore, if the current consumption during the operation of the device is 20 mA, a voltage drop of 0.6 V occurs. At this time, assuming that the power supply voltage V _DD is 3 V, as shown in FIG. 1, the element at the circuit end has the power supply voltage of 3 V, and the element at the center has the power supply voltage of 2.4 V. At this time, each MOSFET is divided into five regions a to e according to the length of the power supply wiring. That is, the circuit is divided into five equal parts in the direction in which the branch line 4 extends, and the respective areas a, b, c, d,
e (in the figure, a, b, and
c, d, e areas). The effective power supply voltage in the regions a, b, c, d, and e is 2.9 V, 2.7 V, 2.5
V, 2.7 V, and 2.9 V, and the potential difference in each region is 0.
2V.

FIG. 2 is a longitudinal sectional view of the portion A in FIG. 2, a silicon oxide film 7 as an insulator layer is formed on a single-crystal silicon substrate 5 with a bonding polysilicon film 6 interposed therebetween. On the surface of the silicon oxide film 7, thin single-crystal silicon layers (hereinafter, referred to as thin-film SOI layers) 8, 9, and 10 as single-crystal semiconductor layers are formed. As described above, in this embodiment, the SOI substrate 30 is used as a semiconductor substrate.

A polysilicon gate electrode 12 is arranged on each of the thin film SOI layers 8 to 10 with a gate oxide film 11 interposed therebetween. A channel region (impurity diffusion region) is formed in the thin film SOI layers 8 to 10 below the polysilicon gate electrode 12, and the polysilicon gate electrode 1
2 are formed with impurity diffusion regions serving as source / drain regions. Thus, the thin SOI layer 8
The MOSFETs 13, 14, 15 are formed by using. In each of the MOSFETs 13 to 15, the thickness of the SOI layers 8 to 10 is smaller than the maximum depletion layer width of the channel region, so that the SOI layers 8 to 10 are completely depleted during channel formation.

In FIG. 2, the MOSFETs 13, 14, 1
5 is shown, the SOI substrate 30 has each FET 1
Channel-type MOSFETs different from 3, 14, and 15 are respectively formed, and each constitutes a C-MOS circuit.

A back gate electrode 16 is buried in a surface layer portion in a region where the polysilicon film 6 is arranged.
The back gate electrode 16 uses an impurity-doped polysilicon layer doped with an impurity, and a charge storage conductor layer is formed by the impurity-doped polysilicon layer. The surface of the back gate electrode (charge storage impurity doped polysilicon layer) 16 is covered with a silicon oxide film 17. The back gate electrode 16 extends below the thin film SOI layers 8 to 10 constituting the MOSFET.

As described above, the back gate electrode 16 which is electrically insulated from other portions is arranged at a position facing the channel region of the MOSFETs 13 to 15. MOSFET 15 (thin film S) in regions a and e (see FIG. 1)
The silicon oxide film 7 under the OI layer 10) has a thickness t.
It is 1. MOSFETs in regions b and d
The thickness of the silicon oxide film 7 under 14 (thin film SOI layer 9) is t2 (<t1). Further, the area c
The thickness of the silicon oxide film 7 under the MOSFET 13 (thin film SOI layer 8) is t3 (<t2). That is, the MOSFET far from the power supply wiring (main line) 2
As the thickness of the silicon oxide film 7 decreases, the threshold voltage decreases. Specifically, t1 is about 250
nm and t2 are about 150 nm, and t3 is about 50 nm.

On the surface of the silicon oxide film 7, a thin single crystal silicon layer (thin film SOI layer) 18 is formed. An impurity-doped polysilicon film 20 is disposed on the upper surface of the thin-film SOI layer 18 via an oxide film 19.

A silicon oxide film 21 as an interlayer insulating film is disposed on the silicon oxide film 7 including the thin SOI layers 8 to 10 and 18. Back gate electrode 16
Are aluminum 22, the thin SOI layer 18, the tunnel oxide film 1
9. Connected to a charge injection line (charge injection terminal) 23 made of aluminum via an impurity-doped polysilicon film 20. A predetermined amount of charge is injected into the back gate electrode (impurity-doped polysilicon layer for charge storage) 16 at the charge injection line 23.

Further, metal wirings 28 extend in the source / drain regions of the MOSFETs 13, 14, and 15, respectively. Then, M in the regions a, b, c, d, and e in FIG.
The sources (or drains) of the OSFETs 13, 14, and 15 are connected to a power supply wiring (branch line) 4. Note that M
Other terminals (drain (or source)) of the OSFETs 13, 14, 15 are grounded.

The SOI substrate 30 (silicon oxide film 2)
The surface of 1) is covered with a BPSG film 24 as a surface protection film. However, a part of the charge injection line 23 is exposed as a charge injection window.

Next, a method of manufacturing this device will be described with reference to FIGS.
4 will be described. First, as shown in FIG. 3, a high-resistance single-crystal silicon substrate 25 is prepared, and an oxide film 26 having a thickness of about 100 nm is formed on a portion to be an SOI layer later. Etching is performed to a depth of about 150 nm by a reactive ion etching method.

Then, after removing the oxide film 26 used as a mask, as shown in FIG. 4, the surface of the silicon substrate 25 is, for example, about 400 nm thick by a thermal oxidation method or a CVD method.
An oxide film (SiO ₂ ) 7 of m is formed. The thickness of the oxide film 7 at the thinnest place corresponds to t1 in FIG.

Before the oxide film 7 is formed, a process for removing damage to the silicon substrate 25 by the etching shown in FIG. 3 may be performed. Subsequently, as shown in FIG. 5, etching is performed, for example, by about 100 nm while leaving a desired region of the oxide film 7. The film thickness at the thinnest place where the oxide film 7 is etched corresponds to t2 in FIG.

Further, as shown in FIG. 6, the oxide film 7 is again etched, for example, by about 100 nm while leaving a desired region. The film thickness at the thinnest place where the oxide film 7 is etched corresponds to t3 in FIG.

Then, as shown in FIG. 7, a polysilicon film 16 is deposited on the oxide film 7 to a thickness of about 20 nm by, for example, a low pressure CVD method, and the polysilicon film 16 is further doped with n-type impurities by, for example, a thermal diffusion method. Impurity doped polysilicon film (back gate electrode) 1 by introducing certain phosphorus
6 is assumed.

Further, the impurity-doped polysilicon film 1
After etching a desired region of the polysilicon film 6, as shown in FIG.
An oxide film 17 having a thickness of, for example, about 200 nm is formed by the VD method.

Subsequently, as shown in FIG.
17, a first polysilicon film is formed, for example, under reduced pressure CVD.
A polysilicon film 6 is formed by depositing a film having a thickness of about 30 nm by a method, and further depositing a polysilicon film of a second layer on the polysilicon film by a CVD method, for example, to a thickness of about 5 μm.

Thereafter, as shown in FIG. 10, the surface of the polysilicon film 6 is flattened by mirror polishing. And FIG.
As shown in FIG. 1, a mirror-polished silicon substrate 5 is prepared, and the mirror surface and the flattened polysilicon mirror surface of the high-resistance silicon substrate 25 are bonded by a direct bonding method.
A substrate in which the two substrates are integrated is formed.

Further, the substrate 25 side is selectively polished to obtain a structure shown in FIG.
As shown in FIG. 7, the oxide film 7 in a region other than the portion to be the SOI layer is exposed on the surface. As a result, SOI layers 8, 9, 10, and 18 having a thickness of about 150 nm are formed, and a floating n ⁺ polysilicon layer 16 is formed in the substrate.

Thereafter, as shown in FIG. 13, oxide films 11 and 19 having a thickness of, for example, about 10 nm and impurity-doped polysilicon layer 12 are formed on SOI layers 8, 9, 10, and 18, respectively.
Then, as shown in FIG. 14, a through hole 27 reaching the polysilicon layer 16 is formed in a part of the SOI layer 18 by, for example, a reactive ion etching method.

Finally, as shown in FIG.
Source / drain regions, interlayer insulating film 21, metal wiring 2
2, 23, 28 and BPSG film 24 are replaced with a normal MOS-IC
It is formed at any time as in the process. Thus, the semiconductor device is completed.

As described above, according to the present manufacturing method, the number of manufacturing steps is increased only in the two steps of oxide film etching shown in FIGS. Next, the operation and effect of the semiconductor device shown in FIG. 2 will be described.

In general, in a thin-film SOI MOSFET, an impurity-doped polysilicon layer (back gate electrode) 16 is arranged at least in a region of the SOI layer facing a channel region via a silicon oxide film (insulating film) 7. The threshold voltage can be controlled by injecting charges into the impurity-doped polysilicon layer 16 (also by applying a voltage). In the thin-film SOI MOSFET provided with the back gate electrode 16 for controlling the threshold value, the electric charge injected into the back gate electrode 16 depends on the distance between the SOI layers 8, 9, 10 constituting the MOSFET and the back gate electrode 16. Have different effects on the MOSFET. By utilizing this, the thickness (distance) t1, t2, t3 of the silicon oxide film 7 is made different, so that the threshold voltage is made different for each region. That is, MO
By changing the distance between the SOI layer forming the SFET and the back gate for each region, the threshold voltage of each region is reduced by 0.2 V as the wiring distance becomes longer.

That is, as shown in FIG. 2, the silicon oxide film (insulating film) 7 has a step-like shape, so that the distances t1, t2, and t3 between the SOI layer and the back gate for each region.
Are changed to set the threshold voltages of the a, e, b, d, and c regions to arbitrary values.

For example, the power supply voltage V_DDAnd threshold voltage V_th
If you want to set the difference between
The pressure was 0.9V, 0.7V, 0.5V, 0.7V respectively.
V, 0.9V, the power supply voltage V in each region_DDWhen
Threshold voltage V_thDeviation from the set value of the
It can be as small as 0.1 V and equal
As a result, the operating speed decreases due to the effective power supply voltage drop.
It becomes possible to suppress. At this time, the number of areas divided is
The power supply voltage V in each area_DDAnd threshold voltage V _thof
The deviation from the set value of the difference is reduced, and the reduction in operating speed is suppressed.
The effect becomes larger.

As described above, even in a region where the effective power supply voltage V _DD is reduced by the voltage drop due to the resistance of the wiring, only an amount corresponding to the voltage drop in that region is used so as not to lower the operation speed of the entire circuit. The threshold voltage V _th is set low, and this method is simple.

As described above, this embodiment has the following features. (A) In a semiconductor device employing an SOI structure and having an impurity-doped polysilicon layer (back gate electrode) 16 disposed therein, each of the MOSFETs 13, 14, 15
Is divided into a plurality of areas a to e according to the length of the power supply wiring,
The threshold voltage of the MOSFET in the region where the wiring is long was lowered. That is, the thicknesses t1, t2, and t3 of the silicon oxide film (insulating film) 7 between the channel regions of the MOSFETs 13, 14, and 15 and the impurity-doped polysilicon layer (back gate electrode) 16 are made different for each region. By
The threshold voltages of the MOSFETs 13, 14, and 15 for each region are made different.

Therefore, in the region where the power supply wiring is long,
Although the ET causes a more effective drop in the power supply voltage, the threshold voltage is lowered, so that a decrease in the operation speed due to the drop in the power supply voltage is prevented. That is, even in a region where the effective power supply voltage is reduced due to the voltage drop due to the resistance of the wiring, the threshold voltage is set low by an amount corresponding to the voltage drop in the region, and the operation speed of the entire circuit is not reduced. As described above, it is possible to suppress the reduction in the operation speed due to the voltage drop due to the resistance component of the wiring without causing a great disadvantage in circuit layout. Further, the structure can be realized by a relatively simple method.

Note that the wiring (power supply wiring) 4 serving as a branch line may be formed in a mesh shape using two layers of metal wiring. At this time, the shape of the divided area is a square. Further, considering the driving rate and the gate usage rate of each gate in the circuit, the voltage drop amount of each MOSFET in the circuit is obtained from an accurate simulation or the like and divided into regions corresponding to the MOSFETs. Needless to say, the effect of suppressing the decrease is increased. (Second Embodiment) Next, a second embodiment of the present invention will be described, focusing on differences from the first embodiment.

FIG. 15 shows a cross-sectional view of the chip 1 instead of FIG. In this embodiment, the back gate electrode is an independent electrode 40, 41, 42 for each of the divided areas. At this time, charge injection (or voltage application) is performed for each back gate electrode, and a desired threshold voltage is obtained for each region by controlling the amount of injected charge (or applied voltage) for each region.

As described above, in the present embodiment, the back gate electrodes 40, 41, 42 are provided independently for each region, and the amount of charge injected or the voltage applied to the back gate electrodes 40, 41, 42 is made different for each region. MOS for each area
The threshold voltages of the FETs can be different.

Note that the second embodiment requires a terminal for voltage application or charge injection for each back gate electrode as compared with the first embodiment, but the distance between the back gate electrode and the SOI layer is small. Since it may be constant (t1 = t2 = t3 in FIG. 2), the manufacturing process is simplified. (Third Embodiment) Next, a third embodiment of the present invention will be described, focusing on differences from the first embodiment.

FIG. 16 is a cross-sectional view of the chip 1 replacing FIG. In this embodiment, the impurity concentration (or ion type) of the channel region that determines the threshold voltage for each divided region
, A desired threshold voltage is obtained for each region. That is, the single crystal silicon substrate 25 shown in FIG.
, The impurity concentration (or ion type) is changed for each region where the region becomes, and the impurity concentration (or ion type) of the channel region is made different. Specifically, the impurity concentration of the channel region is increased as the region of the wiring is longer.

As described above, in this embodiment, each MOSF
The ET is divided into a plurality of regions a to e according to the length of the power supply wiring, and the impurity concentration or the type of the impurity in the channel region in each of the MOSFETs 13, 14, 15 is made different for each region. The lower the threshold voltage, the lower the threshold voltage.

Here, when comparing the first embodiment with the third embodiment, when the third embodiment in which the ion implantation amount is divided for each region is used, four steps are performed. However, in the first embodiment, the number of steps is increased by two, and from this point of view, the first embodiment is a simpler method.

The method according to the third embodiment (a method of changing the impurity concentration or the type of the impurity in the channel region) is a useful technique even in a semiconductor device that does not use a thin-film SOI structure and has no back gate electrode.

In the above description, the case where the C-MOS structure is used has been described. However, the present invention can be applied to a semiconductor device having a single MOSFET formed in a substrate instead of the C-MOS structure.

In the above description, each MOS
When dividing the FET into a plurality of regions according to the length of the power supply wiring, one C-MOS is arranged in each region, but the number of MOSFETs in each region can be set to an appropriate number. .

[Brief description of the drawings]

FIG. 1 is a plan view of a wafer according to a first embodiment.

FIG. 2 is a vertical cross-sectional view of a portion A in FIG.

FIG. 3 is a cross-sectional view illustrating a manufacturing process of the semiconductor device.

FIG. 4 is a cross-sectional view illustrating a manufacturing process of the semiconductor device.

FIG. 5 is a cross-sectional view illustrating a manufacturing step of the semiconductor device.

FIG. 6 is a cross-sectional view illustrating a manufacturing step of the semiconductor device.

FIG. 7 is a cross-sectional view illustrating a manufacturing process of the semiconductor device.

FIG. 8 is a cross-sectional view illustrating a manufacturing process of the semiconductor device.

FIG. 9 is a cross-sectional view illustrating a manufacturing process of the semiconductor device.

FIG. 10 is a cross-sectional view illustrating a manufacturing step of the semiconductor device.

FIG. 11 is a cross-sectional view illustrating a manufacturing step of the semiconductor device.

FIG. 12 is a cross-sectional view illustrating a manufacturing step of the semiconductor device.

FIG. 13 is a cross-sectional view illustrating a manufacturing step of the semiconductor device.

FIG. 14 is a cross-sectional view illustrating a manufacturing step of the semiconductor device.

FIG. 15 is a sectional view of a semiconductor device according to a second embodiment;

FIG. 16 is a sectional view of a semiconductor device according to a third embodiment;

[Explanation of symbols]

4 ... power supply wiring, 7 ... silicon oxide film as insulator layer,
8, 9, 10 ... a thin-film SOI layer as a single-crystal semiconductor layer;
13, 14, 15 MOSFET, 16 back gate electrode, 30 SOI substrate as semiconductor substrate, 40, 4
1, 42: Back gate electrode.

Claims (3)

[Claims] 1. A plurality of MOSFETs are formed on an SOI substrate, a back gate electrode is arranged at least at a position facing a channel region of the MOSFET, and each of the MOSFETs is provided by a power supply wiring extending on the SOI substrate. In a semiconductor device in which a power supply voltage is supplied to a MOSFET, each of the MOSFETs is divided into a plurality of regions in accordance with a length of the power supply wiring, and a thickness of an insulating film between a channel region of the MOSFET and a back gate electrode. The semiconductor device is characterized in that the threshold voltage is lower for a MOSFET in a region having a longer wiring by varying the threshold voltage for each region. 2. A plurality of MOSFETs are formed on an SOI substrate, a back gate electrode is disposed at least at a position facing a channel region of the MOSFET, and each of the MOSFETs is provided by a power supply wiring extending on the SOI substrate. In a semiconductor device in which a power supply voltage is supplied to a MOSFET, each of the MOSFETs is divided into a plurality of regions according to the length of the power supply wiring, and the back gate electrode is independently provided for each region and applied to the back gate electrode. A semiconductor device characterized in that the voltage or the amount of injected charge is different for each region, and the threshold voltage is lower in a MOSFET in a region having a longer wiring. 3. A semiconductor device in which a plurality of MOSFETs are formed on a semiconductor substrate, and a power supply voltage is supplied to each of the MOSFETs by a power supply wiring extending on the semiconductor substrate. According to this, the region is divided into a plurality of regions, and the impurity concentration or the type of the impurity in the channel region in the MOSFET is changed for each region,
A semiconductor device in which a MOSFET in a region having a longer wiring has a lower threshold voltage.