JP3293349B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device.
The present invention relates to a semiconductor device in which a device such as a lateral MOSFET (for example, a switching element) is integrated using a substrate and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, a switched capacitor power conversion circuit (SC circuit) composed of a plurality of switching elements and a plurality of capacitance elements handles a plurality of high voltages. It is effective to use an SOI structure that has a high degree of freedom and facilitates high-breakdown-voltage separation.

FIG. 8 shows an SC circuit of a parallel charging and series discharging type, and the operation will be briefly described below.

[0004] First, ON OFF, the switching element S ₁ and switching element _{S 2, MOSFET (Q 11)} ~
The (Q ₄₁₎ ON, and turns off the _{MOSFET (Q 12) ~ (Q} 42), applies a DC source voltage E to the parallel circuit of the capacitors C ₁ -C _5. At this time, the MOSFETs (Q ₁₂ ) to (Q
₄₂ ) The drain voltages V _{21 to} V ₅₁ are MOSFETs
(Q ₁₁₎ ~ DC source voltage E becomes the ON resistance of the (Q ₄₁₎ is to be _{ignored, MOSFET (Q 12) ~ (} Q 42)
Source voltage V ₁₀ ~V ₄₀ of diode - becomes the voltage drop of the de D ₁ to D ₄ is substantially negligible as zero. Thus capacitor C ₁ -C ₅ is charged to a DC power supply voltage E.

Next, the switching element S₁Off, switch
Ching element S_TwoAnd turn on the MOSFET (Q₁₁) ~
(Q₄₁) Off, MOSFET (Q₁₂)-(Q₄₂)
Then, diode D₁~ D_FourIs reverse biased
Load Z → capacitor C_Five→ MOSFET (Q
₄₂) → Capacitor C_Four→ MOSFET (Q₃₂) → Capacity
Sita C_Three→ MOSFET (Q_{twenty two}) → Capacitor C_Two→ M
OSFET (Q₁₂) → Capacitor C₁→ Switching element
Child S_Two→ Load Z is DC power supply voltage in load Z loop
A pressure five times E (5E) is applied. At this time, the diode
D_FourCathode voltage V₅₀= 0, the MOSF
ET (Q₁₁) Drain voltage V₁₁= 5E, MOSFET
(Q_{twenty one}) Drain voltage V_{twenty one}= 4E, MOSFET (Q
₃₁) Drain voltage V₃₁= 3E, MOSFET (Q₄₁)
Drain voltage V₄₁= 2E, MOSFET (Q₄₂)
Rain voltage V₅₁= E, MOSFET (Q₁₂) Source power
Pressure V _Ten= 4E, MOSFET (Q_{twenty two}) Source voltage V₂₀
= 3E, MOSFET (Q₃₂) Source voltage V₃₀= 2
E, MOSFET (Q₄₂) Source voltage V₄₀= E, die
Mode D_FourCathode voltage V₅₀= 0.

A MOSFET that is part of this circuit
FIG. 9 shows a structure in which (Q ₁₂ ) to MOSFET (Q ₄₂ ) are realized in an SOI structure (first conventional example). This structure is an SOI structure having a one-side insulating oxide film layer (insulating film) 2 between a silicon substrate 1 and a silicon active layer (SOI layer) 3.
A trench 4 is dug from the surface of the I layer 3 to the insulating film 2 and filled with an insulating oxide film to form an individual device (here, M
OSFET (Q ₁₂ ) to MOSFET (Q ₄₂ )) regions, and each device region has a lateral DMOS
An FET is formed and each terminal is drawn out from the substrate surface.

Here, in the configuration shown in FIG. 9, when the circuit shown in FIG.
(Q ₁₂ ) -Drain Dniha of MOSFET (Q ₄₂ )
A voltage of the DC power supply voltage E is applied, and a zero voltage is applied to the source S. If the reference potential Vsub of the silicon substrate 1 is zero, the voltage applied to the insulating film 2 is at most the difference between the maximum voltage (here, the drain voltage) of each device and the reference potential Vsub, and the MOSFET (Q
₁₂ ) The voltage V _2S applied between the device region and the silicon substrate 1, that is, the voltage applied to the insulating film 2 is maximum, and V _2S = V ₂₁ −Vsub = E−0 = E ... (1) Similarly, MOSFET (Q ₂₂ ) to MOSFET
The voltages V _{3S to} V _5S applied between the device region of (Q ₄₂ ) and the silicon substrate 1, that is, the insulating film 2 are applied to the voltages V ₃₁ ,
Since V ₄₁ and V ₅₁ are the DC power supply voltage E, V _3S = V _4S = V _5S = E (2) Also, MOSFET (Q ₁₂ ) to MOSFET
The voltage applied to (Q ₄₂ ) is the DC power supply voltage E.

On the other hand, when performing series discharge, MOSFET
The voltage V _2S between the device region of (Q ₁₂ ) and the silicon substrate 1, that is, the voltage applied to the insulating film 2 is the maximum, and V _2S = V ₂₁ -Vsub = 4E-0 = 4E ... .. (3), and a voltage up to four times (4E) of the DC power supply voltage E is applied to the insulating film 2. Similarly, V _3S = 3E, V _4S = 2E, V _5S = E (4)

As described above, by fabricating devices on an SOI substrate and isolating and isolating each device,
The elements can be integrated on one substrate without being restricted by the voltage relationship between the devices.

In this conventional example, as is generally known, one surface of the silicon active layer 3 is oxidized to a desired thickness to form an insulating film 2 and is bonded to the silicon substrate 1 to form a silicon active layer. 3 may be polished to a desired thickness, a bonded SOI substrate or the like may be used.
It is shown an example of a lateral DMOSFET as _{OSFET (Q 12) ~MOSFET (Q} 42) , but laterally MOSF
An ET or a bipolar transistor may be used.

[0011]

However, MOSFETs
In (Q ₁₂ ) to MOSFET (Q ₄₂ ), although the device itself only needs to have the withstand voltage of the DC power supply voltage E,
Since a voltage of a maximum of 4E is applied to the insulating film 2, the insulating film 2 needs to have a thickness enough to withstand the voltage. Therefore, there is a problem that heat radiation through the substrate is deteriorated. In addition, since each device needs to charge and discharge the charge of the capacitance of the insulating film 2 having a large voltage difference at the time of ON / OFF, the switching speed of each device becomes slow, and the voltage difference between the substrates is different. However, there is a problem that the switching speed is different and the circuit operation becomes unstable.

In order to solve the above problem and further improve the breakdown voltage of the device itself by equalizing the equipotential lines in the device, the highest potential point (V ₂₁ ) of the device as shown by reference numeral 5 in FIG. There is a means (second conventional example) using a field plate for fixing the silicon substrate 1 to the highest potential by connecting to the silicon substrate 1. With this configuration,
The voltage V _2S between the device (MOSFET (Q ₁₂ )) at the highest potential and the silicon substrate 1, that is, the voltage applied to the insulating film 2
Is being reduced, the device (MOSFET (Q ₄₂ in this case)) in the lowest potential in the opposite and between the silicon substrate 1, that is a problem that the voltage V _5S according to the insulating film 2 becomes large as -3E~-4E Occurs.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems. It is an object of the present invention to enable a high-speed operation without affecting a high withstand voltage of an element and to obtain a buried oxide film of an SOI structure. A semiconductor device and a method of manufacturing the same, which can be set arbitrarily irrespective of the potential applied to the element, and can perform stable operation by fixing the potential of the device.

[0014]

In order to solve the above problems, according to the first aspect of the present invention, the first substrate serving as a support substrate is provided.
And a semiconductor substrate having a conductivity type opposite to that of the first semiconductor substrate.
Multiple devices are formed insulated from each other
A second semiconductor substrate, and the first and second semiconductor substrates
And a first insulating layer for electrically insulating each other from each other
A semiconductor device having an SOI structure,
A first semiconductor substrate formed in a first semiconductor substrate;
Having a conductivity type opposite to that of the conductive substrate and having a small number of the plurality of devices;
First conductive region electrically connected to at least two
Electrically connecting the device and the first conductive region
An opening formed in the first insulating layer for connection;
Wherein the first conductive region is the same as the device
Characterized by being electrically connected to the conductive type region.
It is. According to the invention described in claim 2, the support substrate
A first semiconductor substrate, and a first semiconductor substrate opposite to the first semiconductor substrate.
Multiple devices are formed insulated from each other
A second semiconductor substrate, and the first and second semiconductors.
A first insulating layer that electrically insulates the substrate from each other
Semiconductor device having an SOI structure
And forming the plurality of layers in the first insulating layer.
A first device electrically connected to at least two of the devices
Conductive region, the device and the first conductive region
Formed on the first insulating layer for electrically connecting
And the first conductive region has an opening formed therein.
Electrically connected to the same conductivity type area of the device.
It is a feature. According to the invention described in claim 3,
The semiconductor device according to claim 1 or 2, wherein
A plurality of first conductive regions are formed.
Things. According to the invention described in claim 4, claim 1 is
4. The semiconductor device according to claim 3, wherein
The surface of the second semiconductor substrate on which the first insulating layer is disposed
On the side different from the first half via the second insulating layer.
The conductive substrate has an opposite conductivity type to the plurality of devices.
Second conductive region electrically connected to at least two
Electrically connecting the device and the second conductive region
An opening formed in the second insulating layer for connection.
It has the second conductive region, the same of the device
Characterized by being electrically connected to the conductive type region.
It is. According to the invention described in claim 5, claims 1 to
The SOI structure according to claim 4,
The recess is formed by etching one surface of the semiconductor substrate.
Forming one of the second semiconductor substrates on which the concave portions are formed.
An oxide film to be the first insulating film is formed on the surface side,
Polish until exposed and the surface is flat.
The polished surface of the second semiconductor substrate is provided on the first semiconductor substrate.
After bonding the body substrate by the bonding process,
The second semiconductor substrate is located on two sides of the second semiconductor substrate.
To form by polishing to the desired thickness.
It is a feature.

[0015]

According to the first to fourth aspects of the present invention, S
It is not necessary to charge and discharge the parasitic capacitance formed by the insulating film 2 existing between the OI layer 3 and the silicon substrate 1, the silicon substrate 1 is connected to the ground potential zero, and the conductive region 61 is always at the positive potential. Therefore, the conductive region 61 is always in a reverse bias condition with respect to the silicon substrate 1 and PN
The conductive region 61 and the silicon substrate 1
And is electrically separated from.

According to the fifth aspect of the present invention, a predetermined region on one surface of the N-type silicon substrate 3 is subjected to silicon etching to form a concavo-convex portion on one surface of the N-type silicon substrate 3. An oxide film to be an insulating film is formed by performing thermal oxidation, and thereafter, polishing is performed until the convex portions are exposed and the surface is flattened. Here, the P-type silicon substrate 1 and the N-type silicon substrate 3 are bonded to each other to form a substrate having an SOI structure. Thereafter, by polishing the two surfaces of the N-type silicon substrate 3 to a desired thickness, a semiconductor device having an opening in an SOI structure insulating film while maintaining crystallinity can be formed.

[0017]

【Example】

(Embodiment 1) A first embodiment according to the present invention is shown in FIG. 1 and a manufacturing method thereof is shown in FIG.

The difference from the second conventional example shown in FIG.
A relatively high-resistance conductive region 61 facing the SOI layer 3 via the insulating film 2 is newly provided in the silicon substrate 1 so that the lateral MOSFET (Q ₁₂ ) is activated.
And an SOI in which a lateral MOSFET (Q ₄₂ ) is formed
This is a structure in which the layer 3 is electrically connected. The same reference numerals are given to the same components as those of the second conventional example, and the description is omitted.

Next, the manufacturing method will be described with reference to FIG.
After the diffusion window 7 is opened on the oxide film 2 on the surface of the P-type silicon substrate 1 as shown in FIG. 2A, N such as phosphorus is diffused from the diffusion window 7 opened as shown in FIG. An N-type impurity region 61 is formed by introducing a type impurity and performing thermal diffusion. On the other hand, FIG.
As shown in FIG. 2C, an appropriate region on the surface of the N-type silicon substrate 3 is subjected to silicon etching to form irregularities on the surface of the N-type silicon substrate 3, and then, as shown in FIG. 3. Thermal oxidation of the surface is performed. Subsequently, as shown in FIG. 2E, polishing is performed until the surface of the N-type silicon substrate 3 is flattened. Here, the wafer of the P-type silicon substrate 1 shown in FIG. 2B and the wafer of the N-type silicon substrate 3 shown in FIG. In this bonding step, the wafer is turned upside down on the N-type silicon substrate 3 shown in FIG. 2E, and the bonding step is performed to form a substrate having an SOI structure. Thereafter, the surface silicon layer of the SOI substrate is polished to a desired thickness to form a structure shown in FIG. Thereafter, as shown in FIG. 2G, silicon etching is performed on the surface silicon substrate of the SOI substrate, and then the insulating film 2 is deposited in the etched silicon grooves 8, thereby completing the SOI substrate. Then, by forming a lateral MOSFET on the SOI layer 3, the semiconductor device shown in FIG. 1 is completed.

Here, the drain voltage of each lateral MOSFET is determined by the lateral MOSFET (Q ₁₂ ) and the MOSFET (Q
₄₂ ) is electrically connected to the SOI layer 3 where the SOI layer 3 is formed. The conductivity type of the high-resistance conductive region 61 is the same conductivity type as that of the SOI layer 3, and is the opposite conductivity type to that of the silicon substrate 1. The silicon substrate 1 is electrically connected to the ground potential. The potentials at both ends of the conductive region 61 are equal to V ₂₁ and V ₅₁ , respectively, and the potential between the conductive regions 61 continuously changes from V ₂₁ to V ₅₁ . Therefore, FIG.
SOI layer 3 during parallel charging and series discharging in the circuit shown in FIG.
The voltage between the substrate and the silicon substrate 1 is almost always zero.

Therefore, it is not necessary to charge and discharge the parasitic capacitance formed by the insulating film 2 existing between the SOI layer 3 and the silicon substrate 1, and the switching element can operate at a high frequency. Further, since the silicon substrate 1 is connected to the ground potential zero and the conductive region 61 is always at the positive potential,
The conductive region 61 is always in a reverse bias condition with respect to the silicon substrate 1, and the conductive region 6
1 and the silicon substrate 1 are electrically separated. And
MOSFET (Q ₁₂₎ the drain potential of ~MOSFET (Q ₄₂₎ is for being coupled to the potential of the conductive region 61 in a volume of the insulating film 2, is reduced to the reference potential fluctuates due to noise, stable operation can also be a Become. Further, since the conductive region 61 also has a field plate effect, it is clear that it has no adverse effect on the breakdown voltage of the device.

(Embodiment 2) FIG. 3 shows a second embodiment according to the present invention, and FIG. 4 shows a manufacturing method thereof.

The difference from the first embodiment shown in FIG. 1 is that the conductive region 61 is embedded in the insulating films 21 and 22 between the SOI layer 3 of the SOI substrate and the silicon substrate 1. The conductive region 61 and the silicon substrate 1 are electrically separated from each other by the insulating films 21 and 22. The same components as those in the first embodiment are denoted by the same reference numerals and description thereof is omitted. .

Next, a manufacturing method will be briefly described with reference to FIG. As shown in FIG. 4A, an appropriate region of the surface of the N-type silicon substrate 3 is subjected to silicon etching to form irregularities on the surface of the N-type silicon substrate 3, and then, as shown in FIG. Thermal oxidation of the surface of the silicon substrate 3 is performed. And FIG.
Polishing is performed until the surface of the N-type silicon substrate 3 is flattened as shown in FIG. On the other hand, as shown in FIG. 4D, an oxide film 22 is formed in the P-type silicon substrate 1 and a silicon layer is formed on the surface of the P-type silicon substrate 1 by a SIMOX method in which oxygen ions are implanted into the P-type silicon substrate 1 with high acceleration energy. 61 is formed. Here, a wafer in which the oxide film 21 is embedded in the N-type silicon substrate 3 shown in FIG.
Are bonded together with the wafer of the P-type silicon substrate 1 shown in FIG. In this bonding step, the bonding step is performed by reversing the front and back of the wafer of the N-type silicon substrate 3 shown in FIG. 4C, and a substrate having an SOI structure is formed.
The SOI layer 3 of the I substrate is polished to a desired thickness, and FIG.
The structure shown in (e) is formed. After silicon etching of the SOI layer 3 of the SOI substrate is performed as shown in FIG. 4F, an insulating film 21 is deposited in the etched silicon groove 8 as shown in FIG. Is completed. By forming a lateral MOSFET on the SOI layer 3, the semiconductor device shown in FIG. 3 is completed.

Here, in order to obtain the SOI structure shown in FIG. 4G, in the step of FIG.
After the oxide film 22 is formed on the surface, a conductive film such as SIPOS may be formed.

In each of the manufacturing methods shown in the first and second embodiments, the two wafers are bonded together and the SO
When forming an I-wafer, the wafer surface of one silicon substrate is etched in advance to form an uneven portion, and then oxidized to flatten the surface so as to eliminate the uneven portion.
This oxide film functions as a buried oxide film of the SOI wafer. Further, the wafer of one silicon substrate on which the buried oxide film is formed is inverted at the time of bonding, is bonded to the wafer of the other silicon substrate, and is polished to a desired thickness. Regarding the crystallinity of the surface semiconductor layer, the same good crystallinity as that of the surface semiconductor layer obtained by the conventional bonding method is maintained.

(Embodiment 3) FIG. 5 shows a third embodiment according to the present invention.

The difference from the first embodiment shown in FIG. 1 is that the separately formed conductive regions 61 are formed with the insulating film 2 interposed therebetween.
That is, they are individually electrically connected to each of the lateral MOSFETs formed in the OI layer 3. The same components as those of the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

(Embodiment 4) FIG. 6 shows a fourth embodiment according to the present invention.

The difference from the third embodiment shown in FIG. 5 is that the separately formed conductive regions 61 are formed on the SOI layer 3 of the SOI substrate.
The structure is buried in the insulating film 21 and the insulating film 22 between the semiconductor substrate 1 and the silicon substrate 1. The same components as those in the third embodiment are denoted by the same reference numerals, and description thereof is omitted. .

The conductive region 61 in the third and fourth embodiments does not need to have a relatively high resistance.

(Embodiment 5) FIG. 7 shows a fifth embodiment according to the present invention.

The difference from the first embodiment shown in FIG. 1 is that a high-resistance conductive region 62 is newly formed on the surface of the SOI layer 3 via the insulating film 23, and the high-resistance conductive region 62 and the SOI layer 3
Are electrically connected to each other, and the same components as those of the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

The manufacturing method of the structure shown in the third embodiment to the fifth embodiment is the same as the manufacturing method shown in the first embodiment and the second embodiment. It is easily assumed that appropriate silicon etching is performed in order to form an electrical connection.

Further, any of the first to fifth embodiments may be combined. The conductive region 61 shown in the first to fifth embodiments may be formed inside the silicon substrate 1, 2 may be formed inside the conductive region 61.
May be set arbitrarily at a location where electrical connection is made between the silicon substrate 1.

[0036]

According to the first to fourth aspects of the present invention, high-speed operation can be performed without affecting the high breakdown voltage of the element, and the buried oxide film thickness of the SOI structure is applied to the element. It is possible to provide a semiconductor device which can be set arbitrarily irrespective of the potential, and which can perform stable operation by fixing the potential of the device.

According to the fifth aspect of the present invention, it is possible to provide a manufacturing method for easily obtaining the semiconductor device according to any one of the first to fourth aspects while maintaining the crystallinity.

[Brief description of the drawings]

FIG. 1 is a sectional view of a structure showing a first embodiment according to the present invention.

FIG. 2 is a sectional view showing a manufacturing process of a semiconductor substrate used in the above embodiment.

FIG. 3 is a sectional view of a structure showing a second embodiment according to the present invention.

FIG. 4 is a sectional view showing a manufacturing process of the semiconductor substrate used in the above embodiment.

FIG. 5 is a sectional view of a structure showing a third embodiment according to the present invention.

FIG. 6 is a sectional view of a structure showing a fourth embodiment according to the present invention.

FIG. 7 is a sectional view of a structure showing a fifth embodiment according to the present invention.

FIG. 8 is a circuit diagram of a parallel charging and series discharging SC circuit according to the present invention.

FIG. 9 is a sectional view of a structure showing a first conventional example according to the present invention.

FIG. 10 is a sectional view of a structure showing a second conventional example according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Oxide film 3 SOI layer 6 Conductive area

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Masato Onishi 1048 Kadoma Kadoma, Osaka Prefecture Matsushita Electric Works, Ltd. References JP-A-3-93265 (JP, A) JP-A-61-85853 (JP, A) JP-A-58-93282 (JP, A) JP-A-61-67253 (JP, A) 4-275450 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/8234 H01L 21/762 H01L 27/088 H01L 29/786

Claims (5)

(57) [Claims] A first semiconductor substrate serving as a support substrate; a second semiconductor substrate having a conductivity type opposite to the first semiconductor substrate and having a plurality of devices formed insulated from each other; A semiconductor device having an SOI structure, comprising: a first insulating layer that electrically insulates the first and second semiconductor substrates from each other; wherein the semiconductor device is formed in the first semiconductor substrate; A first conductive region having a conductivity type opposite to that of the first semiconductor substrate and electrically connected to at least two of the plurality of devices; and electrically connecting the device and the first conductive region. An opening formed in the first insulating layer for connection, wherein the first conductive region is electrically connected to a region of the same conductivity type of the device. Semiconductor device. 2. A first semiconductor substrate serving as a support substrate, a second semiconductor substrate having a conductivity type opposite to that of the first semiconductor substrate and having a plurality of devices formed insulated from each other; A first insulating layer for electrically insulating the first and second semiconductor substrates from each other; a semiconductor device having an SOI structure, wherein the semiconductor device is formed in the first insulating layer, A first conductive region electrically connected to at least two of the plurality of devices; and a device for electrically connecting the device and the first conductive region.
A semiconductor device having an opening formed in the first insulating layer, wherein the first conductive region is electrically connected to a region of the same conductivity type of the device. 3. The semiconductor device according to claim 1, wherein a plurality of said first conductive regions are formed. 4. On the surface of the second semiconductor substrate, which is different from the surface on which the first insulating layer is arranged, a conductive type opposite to that of the first semiconductor substrate is provided via a second insulating layer. A second conductive region electrically connected to at least two of the plurality of devices; and a second insulating region for electrically connecting the device and the second conductive region. 4. The device according to claim 1, further comprising an opening formed in a layer, wherein the second conductive region is electrically connected to a region of the same conductivity type of the device. 13. A semiconductor device according to claim 1. 5. The SOI structure according to claim 1, wherein an uneven portion is formed by etching one surface side of the second semiconductor substrate, and wherein the uneven portion is formed. Forming an oxide film serving as the first insulating film on one surface side of the second semiconductor substrate, and polishing the surface until the projections are exposed and the surface becomes flat; After bonding the first semiconductor substrate to the surface on which the second semiconductor substrate has been subjected to the bonding step, the two surfaces of the second semiconductor substrate are polished until the second semiconductor substrate has a desired thickness. A method for manufacturing a semiconductor device, comprising: