JP2013149811A - Semiconductor device, manufacturing device and method, and image pickup element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable local control of electric charge in the vicinity of an insulating layer.SOLUTION: A semiconductor device comprises: an insulating layer, such as a silicon oxide film, formed on a silicon substrate; and a silicon layer formed on the insulating layer and comprising, e.g., circuit elements of an integrated circuit formed therein. In the insulating layer, a charge storage layer for storing electric charge, such as a silicon nitride film, is locally formed. This disclosure is applicable not only to the semiconductor device also to a manufacturing device and method and to an image pickup element.

Description

  The present disclosure relates to a semiconductor device, a manufacturing apparatus and method, and an imaging element, and more particularly, to a semiconductor device, a manufacturing apparatus and method, and an imaging element that enable local control of the amount of charge in the vicinity of an insulating layer.

  In recent years, with the miniaturization of semiconductor integrated circuits, reduction of device variation has become a major issue in advanced CMOS (Complementary Metal Oxide Semiconductor). As a solution for variation, a structure in which no dopant is applied to the channel has been proposed. In this case, since there is no channel II, the threshold voltage Vth is determined by the work function of the gate electrode material. However, particularly in the case of a PMOSFET (P Metal-Oxide-Semiconductor Field-Effect Transistor) (hereinafter also simply referred to as PMOS), it is difficult to reduce the threshold voltage Vth.

  In contrast, a buried oxide layer (Box (Buried Oxide) layer) with an UTB (Ultra Thin Body) structure, which is an insulating layer, includes a silicon nitride film (SiN) in a silicon oxide film (SiO2). A technique for controlling the threshold voltage Vth by using an ONO structure has been reported (see, for example, Non-Patent Document 1).

P. Nguyen *, F. Andrieu, X. Garros, J. Widiez, G. Molas, R. Tisseur, O. Weber, A. Toffoli, F. Allain, D. Lafond, H. Dansas, C. Tabone, L Brevard, J. Dechamp, E. Guiot #, O. Faynot, "Ultra-Thin Buried Nitride Integration for Multi-VT, low-Variability and Power Management in Planar FDSOI CMOSFETs", CEA-LETI, Minatec campus, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France, email: francois.andrieu@cea.fr * now with # SOITEC, Parc Technologiques des Fontaines F-38926 Bernin

  However, since the back bias is applied to the bulk substrate, only a positive or negative polarity can be applied. For this reason, if the threshold voltage Vth of the PMOSFET is to be lowered, the threshold voltage Vth of the NMOSFET may be increased.

  The present disclosure has been made in view of such a situation, and an object thereof is to enable local control of the amount of charge in the vicinity of an insulating layer.

  One aspect of the present disclosure includes an insulating layer formed on a silicon substrate and a silicon layer formed on the insulating layer, and the insulating layer has a charge storage layer that locally stores charges. It is a semiconductor device.

  The insulating layer may have the charge storage layer only below a predetermined circuit element.

  The circuit element may be a P-type MOSFET.

  The P-type MOSFET may have a gate electrode made of the same material as the N-type MOSFET.

  The circuit element may be a photodiode.

  The insulating layer may have the charge storage layer only in a predetermined region.

  The insulating layer may be formed of silicon oxide, locally made of silicon nitride, and include the charge storage layer in which charges are stored by a back bias applied to the silicon substrate.

  The insulating layer may be formed of silicon oxide, and may have the charge storage layer made of a high-k film using a high dielectric constant material locally at the interface with the silicon layer.

  The insulating layer may be formed of silicon oxide and locally include the charge storage layer made of a high-k film using a high dielectric constant material.

  The insulating layer may be formed of silicon oxide, and may have a plurality of types of charge storage layers locally at different portions.

  The insulating layer is formed of silicon oxide, is locally made of silicon nitride, includes a first charge storage layer in which charges are stored by a back bias applied to the silicon substrate, and includes the first charge. A second charge storage layer made of a high-k film using a high dielectric constant material can be locally provided in a portion different from the storage layer.

  Another aspect of the present disclosure is a manufacturing apparatus for manufacturing a semiconductor device, which includes a first oxide film forming unit that forms a silicon oxide film on a silicon substrate, and the first oxide film forming unit. A nitride film forming part for forming a silicon nitride film on the silicon oxide film thus formed, and the silicon nitride film formed by the nitride film forming part are patterned so that only a desired portion is localized. And a second oxide film forming unit for forming a silicon oxide film on the silicon nitride film patterned by the nitride film processing unit. .

  The nitride film processing unit applies a resist to the surface of the silicon nitride film, forms a resist opening region at a desired position using a mask and a lithography technique, and performs reactive ion etching on the silicon nitride in the resist opening region. The resist can be removed by etching the film and ashing.

  Each of the nitride film forming unit and the second oxide film forming unit can be formed by a CVD (Chemical Vapor Deposition) method.

  A planarization processing unit for planarizing the surface of the silicon oxide film formed by the second oxide film deposition unit, and a silicon substrate superimposed on the silicon oxide film planarized by the planarization processing unit And a superimposing unit to be further provided.

  The planarization unit polishes the silicon oxide film by CMP (Chemical and Mechanical Polishing) to planarize the surface of the silicon oxide film so that the silicon nitride film is exposed, and the overlapping unit has a flat surface. A silicon substrate having a silicon oxide film formed on the surface can be bonded onto the silicon oxide film thus formed.

  Another aspect of the present disclosure is also a manufacturing method of a manufacturing apparatus for manufacturing a semiconductor device, wherein the first oxide film forming unit forms a silicon oxide film on a silicon substrate, and a nitride film forming unit However, a silicon nitride film is formed on the formed silicon oxide film, and the nitride film processing unit patterns the formed silicon nitride film to leave only a desired portion locally. In the manufacturing method, the second oxide film forming section is processed and forms a silicon oxide film on the patterned silicon nitride film.

  Still another aspect of the present disclosure includes an insulating layer formed on a silicon substrate, a silicon layer formed on the insulating layer, and a photoelectric conversion element that photoelectrically converts incident light formed on the silicon layer. The insulating layer is an image pickup device having a charge storage layer for storing charges under the photoelectric conversion device.

  The insulating layer is formed of silicon oxide, and includes the charge storage layer formed of silicon nitride below the photoelectric conversion element, in which charges are stored by a back bias applied to the silicon substrate. Can do.

  The insulating layer may be formed of silicon oxide, and may have the charge storage layer made of a high-k film using a high dielectric constant material below the photoelectric conversion element.

  In one aspect of the present disclosure, an insulating layer is formed on a silicon substrate, a silicon layer is formed on the insulating layer, and a charge storage layer that accumulates charges locally is formed on the insulating layer. Is done.

  In another aspect of the present disclosure, a silicon oxide film is formed on a silicon substrate, a silicon nitride film is formed on the formed silicon oxide film, and the nitrided silicon nitride film is patterned. Then, a silicon oxide film is formed on the silicon nitride film that has been processed and patterned to leave only a desired portion locally.

  In yet another aspect of the present disclosure, an insulating layer is formed on a silicon substrate, a silicon layer is formed on the insulating layer, a photoelectric conversion element that photoelectrically converts incident light is formed on the silicon layer, and insulation is performed. A charge storage layer for storing charges is formed below the photoelectric conversion element of the layer.

  According to the present disclosure, the amount of charge can be controlled. In particular, the amount of charge in the vicinity of the insulating layer can be locally controlled.

It is sectional drawing explaining the mode of charge amount control by the conventional ONO structure. It is a figure explaining the mode of charge amount control by the conventional ONO structure. It is sectional drawing explaining the structural example of the semiconductor element to which this technique is applied. It is a block diagram which shows the main structural examples of a manufacturing apparatus. It is a figure explaining the example of the mode of a manufacturing process. It is a figure explaining the example of the mode of a manufacturing process. It is a top view explaining the example of arrangement | positioning of an insulating layer. It is a flowchart explaining the example of the flow of a manufacturing process. It is sectional drawing explaining the other structural example of an insulating layer. It is sectional drawing explaining the other structural example of a semiconductor element. It is sectional drawing explaining the structural example of the image pick-up element to which this technique is applied. It is sectional drawing explaining the other structural example of an image pick-up element.

Hereinafter, modes for carrying out the present technology (hereinafter referred to as embodiments) will be described. The description will be given in the following order.
1. First embodiment (semiconductor element)
2. Second embodiment (manufacturing apparatus / manufacturing method)
3. Third embodiment (another example of a semiconductor element)
4). Fourth embodiment (imaging device)

<1. First Embodiment>
[ONO structure]
In order to realize a low threshold voltage (Vth) with a PMOSFET (P Metal-Oxide-Semiconductor Field-Effect Transistor) (hereinafter also simply referred to as a PMOS), for example, in Non-Patent Document 1, UTB (Ultra The threshold voltage Vth is obtained by making the buried oxide layer (Box (Buried Oxide) layer) of the Thin Body structure into an ONO structure that includes (includes) a silicon nitride film (SiN) in a silicon oxide film (SiO2). The technology to control is reported.

  FIG. 1 is a cross-sectional view for explaining a charge amount control by a conventional ONO structure.

As shown in FIG. 1, a silicon nitride film (SiN) sandwiched between two oxide film layers (Top oxide and Bottom oxide) by applying a back bias (V _B (V _{B &#62}; 0)), etc. Since the charge trap is performed on the nitride film layer (Nitride), the threshold voltage Vth can be controlled.

  However, in the conventional case, such an ONO structure is uniformly formed over the entire semiconductor element. Therefore, when both PMOSFET and NMOSFET exist in the semiconductor element, the influence of the back bias applied to both of them.

  However, as shown in the graphs of FIGS. 2A and 2B, by applying a back bias, the threshold voltage Vth becomes PMOSFET and NMOSFET (N Metal-Oxide-Semiconductor Field-Effect Transistor) (hereinafter also simply referred to as NMOS). Thus, they change in opposite directions. That is, for example, if the threshold voltage Vth of the PMOSFET is to be lowered, the threshold voltage Vth of the NMOSFET may be increased.

[Semiconductor element]
Therefore, in the present disclosure, only an insulating layer at a desired portion has an ONO structure so that the amount of charge in the vicinity of the insulating layer can be locally controlled.

  FIG. 3 is a cross-sectional view illustrating a configuration example of a semiconductor element to which the present technology is applied. A semiconductor element 100 shown in FIG. 3 is a semiconductor device in which an integrated circuit is formed on a semiconductor substrate. FIG. 3 shows a configuration example of PMOSFET and NMOSFET as a part of the integrated circuit.

  As shown in FIG. 3, in the semiconductor device 100, an insulating layer 112 and a thin silicon (Si) substrate 113 are stacked on a silicon (Si) substrate 111, and a PMOSFET 130 and an NMOSFET 140 are formed on the silicon substrate 113. Yes.

  A source 131, a gate 132, a drain 133, and a channel 134 are formed on the silicon substrate 113 as a configuration of the PMOSFET 130. Further, as a configuration of the NMOSFET 140, a source 141, a gate 142, a drain 143, and a channel 144 are also formed.

  An oxide film 151 (SiO 2) is formed on the insulating layer 112. Further, a nitride film 152A (SiN) is formed under the PMOSFET 130 of the insulating layer 112. A similar nitride film 152B is also formed in a portion of the insulating layer 112 that is not under the NMOSFET 140. The nitride film 152A and the nitride film 152B are simply referred to as the nitride film 152 when there is no need to distinguish between them.

  As described above, the nitride film 152 is formed only in a portion other than the NMOSFET, and the insulating layer 112 has an ONO structure, so that the influence of bias application does not reach the NMOSFET. Therefore, the semiconductor device 100 can control only the threshold voltage Vth of the PMOSFET without changing the threshold voltage Vth of the NMOSFET.

  Note that the nitride film 152 may be formed only on the insulating layer 112 below the PMOSFET. That is, it is only necessary to form the nitride film 152 only in a desired portion where the influence of bias application is desired, and its position and range are arbitrary.

<2. Second Embodiment>
[manufacturing device]
FIG. 4 is a block diagram showing a main configuration example of a manufacturing apparatus for manufacturing such a semiconductor element 100. A manufacturing apparatus 200 shown in FIG. 4 is an apparatus for manufacturing an imaging device to which the present technology is applied. When forming the nitride film 152, patterning is performed, and the local nitride film 152 is formed as described above. Do. The manufacturing apparatus 200 includes a control unit 211 and a manufacturing unit 241.

  The control unit 211 includes, for example, a CPU (Central Processing Unit), a ROM (Read Only Memory), a RAM (Random Access Memory), and the like, and controls each unit of the manufacturing unit 241 to control processing related to manufacturing of the semiconductor element 100. I do. For example, the CPU of the control unit 211 executes various processes according to programs stored in the ROM. Further, the CPU executes various processes in accordance with programs loaded from the storage unit 223 into the RAM. The RAM also appropriately stores data necessary for the CPU to execute various processes.

  The manufacturing apparatus 200 includes an input unit 221, an output unit 222, a storage unit 223, a communication unit 224, and a drive 225.

  The input unit 221 includes a keyboard, a mouse, a touch panel, an external input terminal, and the like. The input unit 221 receives user instructions and external information input and supplies the information to the control unit 211. The output unit 222 includes a display such as a CRT (Cathode Ray Tube) display and an LCD (Liquid Crystal Display), a speaker, and an external output terminal. The output unit 222 displays various information supplied from the control unit 211 as an image, sound, or analog. Output as a signal or digital data.

  The storage unit 223 includes a solid state drive (SSD) such as a flash memory, a hard disk, and the like, stores information supplied from the control unit 211, and reads and supplies stored information according to a request from the control unit 211. To do.

  The communication unit 224 includes, for example, a wired LAN (Local Area Network), a wireless LAN interface, a modem, and the like, and performs communication processing with an external device via a network including the Internet. For example, the communication unit 224 transmits information supplied from the control unit 211 to the communication partner, or supplies information received from the communication partner to the control unit 211.

  The drive 225 is connected to the control unit 211 as necessary. Then, a removable medium 231 such as a magnetic disk, an optical disk, a magneto-optical disk, or a semiconductor memory is appropriately attached to the drive 225. Then, the computer program read from the removable medium 231 via the drive 225 is installed in the storage unit 223 as necessary.

  The manufacturing unit 241 is controlled by the control unit 211 to perform processing related to manufacturing of the semiconductor element 100 to which the present technology is applied. The manufacturing unit 241 includes an oxide film forming unit 251, a nitride film forming unit 252, a nitride film processing unit 253, an oxide film forming unit 254, a planarization processing unit 255, an oxide film / Si substrate superimposing unit 256, and an element forming unit. Part 257.

  The silicon substrate 111 is supplied to the manufacturing unit 241. As shown in FIG. 5A, the oxide film forming unit 251 forms an oxide film 151A such as SiO 2 on the silicon substrate 111 by, for example, thermal oxidation or CVD (Chemical Vapor Deposition). The oxide film forming unit 251 supplies the silicon substrate 111 on which the oxide film 151 </ b> A is formed to the nitride film forming unit 252.

  As shown in FIG. 5B, the nitride film forming unit 252 forms a nitride film 152 such as SiN on the supplied oxide film 151A of the silicon substrate 111 by, for example, a CVD method. The nitride film forming unit 252 supplies the silicon substrate 111 on which the nitride film 152 is formed to the nitride film processing unit 253.

  The nitride film processing unit 253 performs patterning of the nitride film 152 on the silicon substrate 111 as shown in FIG. 5C.

  More specifically, the nitride film processing unit 253 applies a resist to the surface of the nitride film 152, and forms a resist opening region at a desired position using a mask and a lithography technique. This desired position is, for example, a portion where a circuit element not affected by back bias application is formed, or a portion where a circuit element affected by back bias application is not formed. A circuit element that does not affect the application of the back bias is, for example, an NMOSFET. A circuit element that affects the application of the back bias is, for example, a PMOSFET.

  The nitride film processing unit 253 etches the nitride film 152 by RIE (Reactive Ion Etching) (reactive ion etching). By doing so, the nitride film 152 in a portion where the resist is not formed is removed. When the etching is completed, the nitride film processing unit 253 removes the resist by ashing.

  As described above, nitride film 152 (nitride film 152A and nitride film 152B) is left only in a desired portion where the resist has been formed (locally). That is, the nitride film 152 is patterned.

  The nitride film processing unit 253 supplies the silicon substrate 111 processed with the nitride film 152 in this way to the oxide film forming unit 254.

  As shown in FIG. 5D, the oxide film forming unit 254 forms an oxide film 151B such as SiO 2 from the patterned nitride film 152 by, eg, CVD. The oxide film forming unit 254 supplies the silicon substrate 111 on which the oxide film 151 </ b> B is formed to the planarization processing unit 255.

  As shown in FIG. 6A, the planarization processing unit 255 planarizes the surface of the oxide film 151B so that the nitride film 152 is exposed by polishing the oxide film 151B by CMP (Chemical and Mechanical Polishing), for example. To do. In other words, oxide film 151B-1, nitride film 152A, oxide film 151B-2, and nitride film 152B are exposed on the surface of silicon substrate 111. The planarization processing unit 255 supplies the silicon substrate 111 with the oxide film 151 </ b> B planarized to the oxide film / Si substrate overlapping unit 256.

  As shown in FIG. 6B, the oxide film / Si substrate overlapping portion 256 bonds the silicon substrate 113 on which the oxide film 151C such as SiO 2 is formed on the silicon substrate 111 on which the oxide film 151B is planarized. . Thereby, a silicon substrate including an insulating layer, that is, an SOI (Silicon on Insulator) substrate is manufactured. In addition, the insulating layer 112 (Box layer) in which only a desired portion has the ONO structure of the oxide film 151 and the nitride film 152 and the other portion is formed by the oxide film 151 is completed. Note that the oxide films 151A to 151C are all made of the same material and form the oxide film 151.

  That is, an SOI substrate that includes the insulating layer 112 having an ONO structure locally is manufactured. In this insulating layer 112 (Box layer), for example, the NMOSFET portion is formed of SiO2, and the PMOSFET portion has an ONO (SiO2 / SiN / SiO2) structure. The oxide film / Si substrate superimposing unit 256 supplies the silicon substrate 111 with the SOI (Silicon on Insulator) substrate manufactured in this way to the element forming unit 257.

  The element formation unit 257 forms a circuit element on the supplied SOI substrate, as shown in FIG. 6C. The element forming unit 257 forms the PMOSFET 130 by forming the source 131, the gate 132, the drain 133, and the channel 134 on the silicon substrate 113, or forms the source 141, the gate 142, the drain 143, and the channel 144, for example. As a result, the NMOSFET 140 is formed.

  Further, as in the example shown in FIG. 6C, the element forming portion 257 can form an STI (Shallow Trench Isolation) 271 to separate the PMOSFET 130 and the NMOSFET 140. For example, the element forming unit 257 forms an STI 271 by digging a groove in a portion between the PMOSFET 130 and the NMOSFET 140 of the silicon substrate 113 and filling SiO 2 as an insulator.

  In addition, as in the example illustrated in FIG. 6C, the element formation unit 257 includes, for example, an electrode 272 that applies a back bias to the silicon substrate 111.

  The element forming unit 257 outputs the semiconductor element 100 manufactured as described above to the outside of the manufacturing apparatus 200.

  The semiconductor device 100 manufactured as described above can control the threshold voltage Vth by applying a back bias to the electrode 272 to trap charges in the ONO portion and controlling the channel portion. When this back bias is applied, it is necessary to apply the voltage between the substrate and the source, or between the substrate and the drain. Therefore, in order to realize more stable voltage application, the nitride film 152 has a channel portion It is desirable to form not only under the source and drain.

  For example, as shown in FIG. 7, it is desirable that the nitride film 152 be formed up to the periphery of the active region where the PMOSFET is formed (that is, the insulating layer 112 has an ONO structure).

  Note that the nitride film 152 is desirably separated under the STI 271 or formed by processing the nitride film with the STI 271.

  In addition, since it is necessary to trap electrons in the nitride film 152, the insulating layer 112 (Box layer) is desirably thin. As an approximate numerical value, the ONO of the insulating layer 112 is desirably set so that each film thickness is about 10 nm or less. Further, since the back bias needs to trap charges in the nitride film 152, a voltage that does not cause dielectric breakdown is required. Specifically, an absolute value of about 5V (10V is the maximum) is desirable.

  The target device is a UTB structure, and the silicon base of the actual device is very thin, about several nanometers to several tens of nanometers. Since the silicon substrate transmits visible light of 3 μm or more, sufficient visibility of the pattern of the nitride film 152 can be obtained. As a result, accurate alignment is possible, so that the insulating layer 112 (Box layer) can be made into an ONO structure only at a desired portion (for example, a portion of the PMOSFET 130).

[Flow of manufacturing process]
FIG. 8 is a flowchart for explaining an example of the flow of the manufacturing process.

  When the manufacturing process is started, the oxide film forming unit 251 controls the control unit 211 to form the oxide film 151A on the silicon substrate 111 which is a bulk silicon substrate in step S201.

  In step S202, the nitride film forming unit 252 is controlled by the control unit 211 to form the nitride film 152 on the oxide film 151A.

  In step S203, the nitride film processing unit 253 is controlled by the control unit 211 to pattern the nitride film 152 as described above, leaving only a desired portion.

  In step S <b> 204, the oxide film forming unit 254 is controlled by the control unit 211 to form the oxide film 151 </ b> B on the nitride film 152.

  In step S205, the planarization processing unit 255 is controlled by the control unit 211 to planarize the surface of the oxide film 151B.

  In step S206, the oxide film / Si substrate superimposing unit 256 is controlled by the control unit 211 to bond the planarized oxide film 151B and the oxide film 151C formed on the silicon substrate 113 to bond the SOI substrate. To manufacture.

  In step S207, the element forming unit 257 is controlled by the control unit 211 to form circuit elements such as PMOSFETs and NMOSFETs on the SOI substrate.

  When the semiconductor element 100 is manufactured as described above, the manufacturing unit 241 ends the manufacturing process.

  By performing each process as described above, the manufacturing apparatus 200 can easily manufacture the semiconductor element 100 that locally controls the amount of charge in the vicinity of the insulating layer.

<3. Third Embodiment>
[High-k film]
The present technology locally controls the amount of charge in the vicinity of the insulating layer by providing a charge storage layer that stores charges at a desired position of the insulating layer. The structure for accumulating the charge is arbitrary and may be other than the above-described ONO structure. For example, as shown in FIG. 9, instead of the ONO structure, high dielectric constants such as hafnium oxide (HfO2), titanium oxide (TiO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), lanthanum oxide (La2O3), etc. The high-k film 301 using the above material may be formed in the vicinity of the interface between the PMOSFET insulating layer (Box layer) 112 and the silicon substrate 113.

  FIG. 9A shows an example in which the High-k film 301 is formed at the interface between the insulating layer (Box layer) 112 and the silicon substrate 113. FIG. 9B shows an example in which the high-k film 301 is formed inside the insulating layer (Box layer) 112. In this case, since the high-k film 301 itself has a charge (generates a negative fixed charge), there is a possibility that the back bias is unnecessary.

  In addition, since it is desirable to accumulate charges near the interface between the insulating layer (Box layer) 112 and the silicon substrate 113, the High-k film 301 is formed in a shallower portion of the insulating layer (Box layer) 112. Desirable (closer to the interface).

  Such a high-k film 301 is formed only in a desired portion (for example, a PMOSFET portion) by patterning (or not to be formed in an unnecessary portion), similarly to the above-described ONO structure. As a result, the amount of charge in the vicinity of the insulating layer can be locally controlled.

[Gate common material]
FIG. 10 is a cross-sectional view illustrating another configuration example of the semiconductor element. In the semiconductor element 100 to which the present technology is applied, the threshold voltage Vth of the PMOSFET can be controlled by the back bias. In addition, the control does not affect the threshold voltage Vth of the NMOSFET. Therefore, the material of the gate 132 of the PMOSFET 130 may be any material as long as it functions as a gate, and can be determined independently of the material of the gate 142 of the NMOSFET 140.

  For example, as in the example shown in FIG. 10, the gate 132 of the PMOSFET 130 may be formed of the same material as the gate 142 of the NMOSFET 140. By doing so, the structure of the semiconductor element is further simplified. In addition, the gate 132 and the gate 142 can be formed in a single process, and the manufacturing of the semiconductor element 100 becomes easier. Therefore, cost reduction can be realized.

<4. Fourth Embodiment>
[Image sensor 1]
The present technology described above can be applied to circuit elements other than MOSFETs. For example, the insulating layer below the photodiode of the image sensor may have an ONO structure.

  FIG. 11 is a cross-sectional view illustrating a configuration example of an image sensor to which the present technology is applied. As in the case of the semiconductor element 100, the imaging element 400 illustrated in FIG. 11 includes a peripheral circuit 410, an image sensor 420, and the like on an SOI substrate in which an insulating layer 112 is formed between the silicon substrate 111 and the silicon substrate 113. A circuit element is formed, and is an element that outputs an image of a subject captured by the image sensor 420 as an electric signal (data).

  On the silicon substrate 113, circuit elements such as PMOSFETs and NMOSFETs are formed as the peripheral circuits 410. Further, a MOSFET and a photodiode 430 are formed on the silicon substrate 113 as the image sensor 420.

  The photodiode 430 photoelectrically converts incident light. When imaging of the subject is started, the photodiode 430 converts the image of the subject into an electrical signal (image data). The image sensor 420 reads the image data from the photodiode and outputs the image data to the outside of the image sensor 400 via the peripheral circuit 410.

  A nitride film 152 is provided as a charge storage layer inside the oxide film 151 below the photodiode 430, and an ONO structure is formed in the insulating layer 112. Since the film thickness of the silicon substrate 113 is determined by the light absorption of the image sensor, about 3 μm is required, and the region for charge control is not the vicinity of the surface but a deep region. By applying a back bias to the silicon substrate 111, charges are accumulated in the nitride film 152, so that this ONO structure can be used for potential formation at a deep portion of the photodiode 430.

  The charge storage layer may be a high-k film as described above. In this case, similarly to the case of the first embodiment, the nitride film 152 is patterned, and this nitride film 152 is formed only under the photodiode 430, so that, for example, the NMOSFET of the peripheral circuit 410 is formed. For example, the influence of the application of the back bias to the circuit element that is not desired can be suppressed.

  As in the case of the third embodiment, a high-k film is formed in the vicinity of the interface between the insulating layer (Box layer) 112 of the PMOSFET and the silicon substrate 113 instead of making the insulating layer 112 have an ONO structure. You may do it.

  Further, such patterning of the nitride film 152 is not necessarily performed for each circuit element, and may be performed for each arbitrary region. For example, patterning may be performed for each area for each application, such as the area of the image sensor 420 and the area of the peripheral circuit 410.

[Image sensor 2]
Further, a plurality of types of charge storage layers may be locally provided in different portions of the insulating layer 112. For example, as in the example shown in FIG. 12, both the nitride film 152 and the high-k film 301 may be provided locally (at different positions) on the insulating layer 112.

  The image sensor 500 shown in FIG. 12 basically has the same configuration as the image sensor 400 shown in FIG. 11, but the lower part of the PMOSFET 411 formed as the peripheral circuit 410 of the insulating layer 112 is an oxide film 151 and a nitride film. An ONO structure 152 is formed, and only the oxide film 151 is formed below the NMOSFET 412 formed as the peripheral circuit 410, and the high-k film 301 is formed in the entire region of the image sensor 420.

  In this case, the threshold voltage Vth of the PMOSFET 411 is controlled by the back bias Vb without affecting the threshold voltage Vth of the NMOSFET 412. In addition, circuit elements such as the photodiode 430 formed in the image sensor 420 are affected by charges accumulated in the high-k film 301 regardless of whether or not a back bias is applied.

  This makes it possible to control the amount of charge near the insulating layer more diversely. Of course, the position (region) where the nitride film 152 and the high-k film 301 are formed is arbitrary as long as they are different from each other.

  In this technology, the amount of charge in the vicinity of the insulating layer is locally controlled by accumulating charges locally in the insulating layer, and its specific structure allows local charge amount control. As long as it is. That is, the structure for accumulating the charge is not limited to the above-described ONO structure using a back bias or a high-k film.

  Note that the imaging device to which the present technology is applied is not limited to the above-described configuration, and any information processing having an imaging function, such as a digital still camera, a video camera, a mobile phone, a smartphone, a tablet device, or a personal computer. It can be applied to the device. The present invention can also be applied to a camera module that is used by being mounted on another information processing apparatus (or mounted as an embedded device).

  Furthermore, the present technology can be applied to any semiconductor device.

  The series of processes described above can be executed by hardware or can be executed by software. When the above-described series of processing is executed by software, a program constituting the software is installed from a network or a recording medium.

  For example, as shown in FIG. 4, the recording medium includes a removable medium 231 on which a program is recorded, which is distributed to distribute the program to the user, separately from the apparatus main body. The removable medium 231 includes a magnetic disk (including a flexible disk) and an optical disk (including a CD-ROM and a DVD). Furthermore, a magneto-optical disk (including MD (Mini Disc)), a semiconductor memory, and the like are also included. The above-described recording medium is not only such a removable medium 231 but also a ROM in which a program is recorded and a hard disk included in the storage unit 223 that is distributed to the user in a state of being incorporated in the apparatus main body in advance. It may be configured by.

  The program executed by the computer may be a program that is processed in time series in the order described in this specification, or in parallel or at a necessary timing such as when a call is made. It may be a program for processing.

  Further, in the present specification, the step of describing the program recorded on the recording medium is not limited to the processing performed in chronological order according to the described order, but may be performed in parallel or It also includes processes that are executed individually.

  Further, in this specification, the system represents the entire apparatus composed of a plurality of devices (apparatuses).

  In addition, in the above description, the configuration described as one device (or processing unit) may be divided and configured as a plurality of devices (or processing units). Conversely, the configurations described above as a plurality of devices (or processing units) may be combined into a single device (or processing unit). Of course, a configuration other than that described above may be added to the configuration of each device (or each processing unit). Furthermore, if the configuration and operation of the entire system are substantially the same, a part of the configuration of a certain device (or processing unit) may be included in the configuration of another device (or other processing unit). . That is, the present technology is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present technology.

In addition, this technique can also take the following structures.
(1) an insulating layer formed on a silicon substrate;
A silicon layer formed on the insulating layer,
The said insulating layer has a charge storage layer which accumulate | stores an electric charge locally. Semiconductor device.
(2) The semiconductor device according to (1), wherein the insulating layer includes the charge storage layer only below a predetermined circuit element.
(3) The semiconductor device according to (2), wherein the circuit element is a P-type MOSFET.
(4) The semiconductor device according to (3), wherein the P-type MOSFET has a gate electrode made of the same material as the N-type MOSFET.
(5) The semiconductor device according to (2), wherein the circuit element is a photodiode.
(6) The semiconductor device according to (1), wherein the insulating layer includes the charge storage layer only in a predetermined region.
(7) The insulating layer is formed of silicon oxide, is locally made of silicon nitride, and includes the charge storage layer in which charges are stored by a back bias applied to the silicon substrate. The semiconductor device according to any one of (6).
(8) The insulating layer is formed of silicon oxide, and has the charge storage layer made of a high-k film using a high dielectric constant material locally at the interface with the silicon layer. (1) The semiconductor device in any one of thru | or (6).
(9) The insulating layer is formed of silicon oxide and locally includes the charge storage layer made of a high-k film using a high dielectric constant material. Any one of (1) to (6) A semiconductor device according to 1.
(10) The semiconductor device according to any one of (1) to (9), wherein the insulating layer is formed of silicon oxide and has a plurality of types of charge storage layers locally at different portions.
(11) The insulating layer is formed of silicon oxide, is locally made of silicon nitride, and includes a first charge storage layer in which charges are stored by a back bias applied to the silicon substrate, The device according to any one of (1) to (10), wherein a second charge storage layer made of a high-k film using a high dielectric constant material is locally provided in a portion different from the one charge storage layer. Semiconductor device.
(12) A manufacturing apparatus for manufacturing a semiconductor device,
A first oxide film forming section for forming a silicon oxide film on a silicon substrate;
A nitride film forming unit for forming a silicon nitride film on the silicon oxide film formed by the first oxide film forming unit;
A nitride film processing unit that processes the silicon nitride film formed by the nitride film forming unit so as to leave only a desired portion locally by patterning;
A manufacturing apparatus comprising: a second oxide film forming unit that forms a silicon oxide film on the silicon nitride film patterned by the nitride film processing unit.
(13) The nitride film processing unit applies a resist to the surface of the silicon nitride film, forms a resist opening region at a desired position using a mask and a lithography technique, and performs reactive ion etching on the resist opening region. The manufacturing apparatus according to (12), wherein the silicon nitride film is etched and the resist is removed by ashing.
(14) The manufacturing apparatus according to (12) or (13), wherein each of the nitride film forming unit and the second oxide film forming unit performs film formation by a CVD (Chemical Vapor Deposition) method.
(15) a planarization processing unit that planarizes the surface of the silicon oxide film formed by the second oxide film forming unit;
The manufacturing apparatus according to any one of (12) to (14), further including: a superimposing unit that superimposes a silicon substrate on the silicon oxide film planarized by the planarizing unit.
(16) The planarization processing unit planarizes the silicon oxide film surface so as to polish the silicon oxide film by CMP (Chemical and Mechanical Polishing) and expose the silicon nitride film,
The manufacturing apparatus according to (15), wherein the superimposing unit bonds a silicon substrate on which a silicon oxide film is formed on the silicon oxide film having a planarized surface.
(17) A manufacturing method of a manufacturing apparatus for manufacturing a semiconductor device,
The first oxide film forming unit forms a silicon oxide film on the silicon substrate,
The nitride film forming unit forms a silicon nitride film on the formed silicon oxide film,
A nitride film processing unit processes the formed silicon nitride film so that only a desired portion is left locally by patterning,
A manufacturing method in which a second oxide film forming unit forms a silicon oxide film on the patterned silicon nitride film.
(18) an insulating layer formed on the silicon substrate;
A silicon layer formed on the insulating layer;
A photoelectric conversion element that photoelectrically converts incident light formed in the silicon layer,
The said insulating layer has a charge storage layer which accumulate | stores an electric charge in the lower part of the said photoelectric conversion element.
(19) The insulating layer is formed of silicon oxide, and is formed of silicon nitride below the photoelectric conversion element, and includes the charge storage layer in which charges are stored by a back bias applied to the silicon substrate. The imaging device according to (18).
(20) The imaging according to (18), wherein the insulating layer is formed of silicon oxide, and has the charge storage layer made of a high-k film using a high dielectric constant material below the photoelectric conversion element. element.

  100 semiconductor device, 111 silicon substrate, 112 insulating layer, 113 silicon substrate, 130 PMOSFET, 131 source, 132 gate, 133 drain, 134 channel, 140 NMOSFET, 141 source, 142 gate, 143 drain, 144 channel, 151 oxide film, 152 nitride film, 200 manufacturing apparatus, 211 control unit, 241 manufacturing unit, 252 nitride film forming unit, 253 nitride film processing unit, 271 STI, 300 semiconductor element, 301 high-k film, 400 imaging element, 410 peripheral circuit, 411 PMOSFET, 412, NMOSFET, 420 Image sensor, 430 Photodiode

Claims (20)

An insulating layer formed on the silicon substrate;
A silicon layer formed on the insulating layer,
The said insulating layer has a charge storage layer which accumulate | stores an electric charge locally. Semiconductor device. The semiconductor device according to claim 1, wherein the insulating layer has the charge storage layer only under a predetermined circuit element. The semiconductor device according to claim 2, wherein the circuit element is a P-type MOSFET. The semiconductor device according to claim 3, wherein the P-type MOSFET has a gate electrode made of the same material as that of the N-type MOSFET. The semiconductor device according to claim 2, wherein the circuit element is a photodiode. The semiconductor device according to claim 1, wherein the insulating layer has the charge storage layer only in a predetermined region. 2. The semiconductor device according to claim 1, wherein the insulating layer is formed of silicon oxide, is locally formed of silicon nitride, and includes the charge storage layer in which charges are stored by a back bias applied to the silicon substrate. . 2. The semiconductor according to claim 1, wherein the insulating layer is formed of silicon oxide and has the charge storage layer made of a high-k film using a high dielectric constant material locally at an interface with the silicon layer. apparatus. The semiconductor device according to claim 1, wherein the insulating layer is formed of silicon oxide and locally includes the charge storage layer made of a high-k film using a high dielectric constant material. The semiconductor device according to claim 1, wherein the insulating layer is formed of silicon oxide and has a plurality of types of charge storage layers locally at different portions. The insulating layer is formed of silicon oxide, is locally made of silicon nitride, includes a first charge storage layer in which charges are stored by a back bias applied to the silicon substrate, and includes the first charge. The semiconductor device according to claim 1, further comprising a second charge accumulation layer made of a high-k film using a material having a high dielectric constant locally at a portion different from the accumulation layer. A manufacturing apparatus for manufacturing a semiconductor device,
A first oxide film forming section for forming a silicon oxide film on a silicon substrate;
A nitride film forming unit for forming a silicon nitride film on the silicon oxide film formed by the first oxide film forming unit;
A nitride film processing unit that processes the silicon nitride film formed by the nitride film forming unit so as to leave only a desired portion locally by patterning;
A manufacturing apparatus comprising: a second oxide film forming unit that forms a silicon oxide film on the silicon nitride film patterned by the nitride film processing unit. The nitride film processing unit applies a resist to the surface of the silicon nitride film, forms a resist opening region at a desired position using a mask and a lithography technique, and performs reactive ion etching on the silicon nitride in the resist opening region. The manufacturing apparatus according to claim 12, wherein the film is etched and the resist is removed by ashing. The manufacturing apparatus according to claim 12, wherein the nitride film forming unit and the second oxide film forming unit each form a film by a CVD (Chemical Vapor Deposition) method. A planarization processing unit for planarizing the surface of the silicon oxide film formed by the second oxide film forming unit;
The manufacturing apparatus according to claim 12, further comprising: an overlapping portion that overlaps a silicon substrate on the silicon oxide film flattened by the flattening processing portion. The planarization unit polishes the silicon oxide film by CMP (Chemical and Mechanical Polishing), planarizes the silicon oxide film surface so as to expose the silicon nitride film,
The manufacturing apparatus according to claim 15, wherein the overlapping unit is configured to bond a silicon substrate having a silicon oxide film formed on a surface of the silicon oxide film having a planarized surface. A manufacturing method of a manufacturing apparatus for manufacturing a semiconductor device,
The first oxide film forming unit forms a silicon oxide film on the silicon substrate,
The nitride film forming unit forms a silicon nitride film on the formed silicon oxide film,
The nitride film processing unit processes the formed silicon nitride film so as to leave only a desired portion locally by patterning,
A manufacturing method in which a second oxide film forming unit forms a silicon oxide film on the patterned silicon nitride film. An insulating layer formed on the silicon substrate;
A silicon layer formed on the insulating layer;
A photoelectric conversion element that photoelectrically converts incident light formed in the silicon layer,
The said insulating layer has a charge storage layer which accumulate | stores an electric charge in the lower part of the said photoelectric conversion element. The insulating layer is formed of silicon oxide, and is formed of silicon nitride below the photoelectric conversion element, and includes the charge storage layer in which charges are stored by a back bias applied to the silicon substrate. The imaging device described. The imaging device according to claim 18, wherein the insulating layer is formed of silicon oxide, and has the charge storage layer made of a high-k film using a high dielectric constant material below the photoelectric conversion device.

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