SG153631A1 - Pmos transistor strain optimization with raised junction regions - Google Patents

Pmos transistor strain optimization with raised junction regions

Info

Publication number
SG153631A1
SG153631A1 SG200402952-6A SG2004029526A SG153631A1 SG 153631 A1 SG153631 A1 SG 153631A1 SG 2004029526 A SG2004029526 A SG 2004029526A SG 153631 A1 SG153631 A1 SG 153631A1
Authority
SG
Singapore
Prior art keywords
silicon alloy
alloy material
substrate
pmos transistor
junction regions
Prior art date
Application number
SG200402952-6A
Other languages
English (en)
Inventor
Mark T Bohr
Tahir Ghani
Stephen Cea
Kaizad Mistry
Christopher P Auth
Mark Armstrong
Keith E Zawadzki
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of SG153631A1 publication Critical patent/SG153631A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
SG200402952-6A 2003-06-27 2004-05-21 Pmos transistor strain optimization with raised junction regions SG153631A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/608,870 US20040262683A1 (en) 2003-06-27 2003-06-27 PMOS transistor strain optimization with raised junction regions

Publications (1)

Publication Number Publication Date
SG153631A1 true SG153631A1 (en) 2009-07-29

Family

ID=33540701

Family Applications (1)

Application Number Title Priority Date Filing Date
SG200402952-6A SG153631A1 (en) 2003-06-27 2004-05-21 Pmos transistor strain optimization with raised junction regions

Country Status (8)

Country Link
US (2) US20040262683A1 (fr)
EP (2) EP3392905B1 (fr)
KR (1) KR100741238B1 (fr)
CN (1) CN100449780C (fr)
AU (1) AU2003297139A1 (fr)
SG (1) SG153631A1 (fr)
TW (1) TWI298948B (fr)
WO (1) WO2005010982A1 (fr)

Families Citing this family (128)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6830976B2 (en) * 2001-03-02 2004-12-14 Amberwave Systems Corproation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6982474B2 (en) 2002-06-25 2006-01-03 Amberwave Systems Corporation Reacted conductive gate electrodes
US7358121B2 (en) 2002-08-23 2008-04-15 Intel Corporation Tri-gate devices and methods of fabrication
US6921913B2 (en) * 2003-03-04 2005-07-26 Taiwan Semiconductor Manufacturing Co., Ltd. Strained-channel transistor structure with lattice-mismatched zone
US7531828B2 (en) * 2003-06-26 2009-05-12 Mears Technologies, Inc. Semiconductor device including a strained superlattice between at least one pair of spaced apart stress regions
US20070015344A1 (en) * 2003-06-26 2007-01-18 Rj Mears, Llc Method for Making a Semiconductor Device Including a Strained Superlattice Between at Least One Pair of Spaced Apart Stress Regions
US7456476B2 (en) 2003-06-27 2008-11-25 Intel Corporation Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
US6909151B2 (en) * 2003-06-27 2005-06-21 Intel Corporation Nonplanar device with stress incorporation layer and method of fabrication
US7078742B2 (en) 2003-07-25 2006-07-18 Taiwan Semiconductor Manufacturing Co., Ltd. Strained-channel semiconductor structure and method of fabricating the same
US6936881B2 (en) 2003-07-25 2005-08-30 Taiwan Semiconductor Manufacturing Company, Ltd. Capacitor that includes high permittivity capacitor dielectric
US6891192B2 (en) * 2003-08-04 2005-05-10 International Business Machines Corporation Structure and method of making strained semiconductor CMOS transistors having lattice-mismatched semiconductor regions underlying source and drain regions
US20050035410A1 (en) * 2003-08-15 2005-02-17 Yee-Chia Yeo Semiconductor diode with reduced leakage
US7112495B2 (en) 2003-08-15 2006-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit
US20050035369A1 (en) * 2003-08-15 2005-02-17 Chun-Chieh Lin Structure and method of forming integrated circuits utilizing strained channel transistors
US7071052B2 (en) * 2003-08-18 2006-07-04 Taiwan Semiconductor Manufacturing Company, Ltd. Resistor with reduced leakage
US6906360B2 (en) * 2003-09-10 2005-06-14 International Business Machines Corporation Structure and method of making strained channel CMOS transistors having lattice-mismatched epitaxial extension and source and drain regions
US7303949B2 (en) 2003-10-20 2007-12-04 International Business Machines Corporation High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture
US7888201B2 (en) 2003-11-04 2011-02-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors
US7247534B2 (en) 2003-11-19 2007-07-24 International Business Machines Corporation Silicon device on Si:C-OI and SGOI and method of manufacture
US7545001B2 (en) * 2003-11-25 2009-06-09 Taiwan Semiconductor Manufacturing Company Semiconductor device having high drive current and method of manufacture therefor
US6989322B2 (en) * 2003-11-25 2006-01-24 International Business Machines Corporation Method of forming ultra-thin silicidation-stop extensions in mosfet devices
US7105390B2 (en) * 2003-12-30 2006-09-12 Intel Corporation Nonplanar transistors with metal gate electrodes
US7268058B2 (en) 2004-01-16 2007-09-11 Intel Corporation Tri-gate transistors and methods to fabricate same
US6921691B1 (en) * 2004-03-18 2005-07-26 Infineon Technologies Ag Transistor with dopant-bearing metal in source and drain
CN1684246B (zh) * 2004-03-30 2010-05-12 三星电子株式会社 低噪声和高性能电路以及制造方法
US7154118B2 (en) * 2004-03-31 2006-12-26 Intel Corporation Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
US7023018B2 (en) * 2004-04-06 2006-04-04 Texas Instruments Incorporated SiGe transistor with strained layers
US7119404B2 (en) * 2004-05-19 2006-10-10 Taiwan Semiconductor Manufacturing Co. Ltd. High performance strained channel MOSFETs by coupled stress effects
US7592678B2 (en) * 2004-06-17 2009-09-22 Infineon Technologies Ag CMOS transistors with dual high-k gate dielectric and methods of manufacture thereof
US8178902B2 (en) * 2004-06-17 2012-05-15 Infineon Technologies Ag CMOS transistor with dual high-k gate dielectric and method of manufacture thereof
US8399934B2 (en) 2004-12-20 2013-03-19 Infineon Technologies Ag Transistor device
US7042009B2 (en) 2004-06-30 2006-05-09 Intel Corporation High mobility tri-gate devices and methods of fabrication
US7122435B2 (en) * 2004-08-02 2006-10-17 Texas Instruments Incorporated Methods, systems and structures for forming improved transistors
US7348284B2 (en) 2004-08-10 2008-03-25 Intel Corporation Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow
US7179696B2 (en) * 2004-09-17 2007-02-20 Texas Instruments Incorporated Phosphorus activated NMOS using SiC process
US7071064B2 (en) * 2004-09-23 2006-07-04 Intel Corporation U-gate transistors and methods of fabrication
US7422946B2 (en) 2004-09-29 2008-09-09 Intel Corporation Independently accessed double-gate and tri-gate transistors in same process flow
US7332439B2 (en) 2004-09-29 2008-02-19 Intel Corporation Metal gate transistors with epitaxial source and drain regions
US7361958B2 (en) * 2004-09-30 2008-04-22 Intel Corporation Nonplanar transistors with metal gate electrodes
US20060086977A1 (en) 2004-10-25 2006-04-27 Uday Shah Nonplanar device with thinned lower body portion and method of fabrication
US7402872B2 (en) * 2004-11-18 2008-07-22 Intel Corporation Method for forming an integrated circuit
US7344934B2 (en) 2004-12-06 2008-03-18 Infineon Technologies Ag CMOS transistor and method of manufacture thereof
KR100678314B1 (ko) 2004-12-15 2007-02-02 동부일렉트로닉스 주식회사 저접촉저항을 갖는 반도체 소자의 제조방법
US7195985B2 (en) * 2005-01-04 2007-03-27 Intel Corporation CMOS transistor junction regions formed by a CVD etching and deposition sequence
US7335959B2 (en) * 2005-01-06 2008-02-26 Intel Corporation Device with stepped source/drain region profile
US7193279B2 (en) * 2005-01-18 2007-03-20 Intel Corporation Non-planar MOS structure with a strained channel region
JP4369379B2 (ja) * 2005-02-18 2009-11-18 富士通マイクロエレクトロニクス株式会社 半導体装置
US7518196B2 (en) 2005-02-23 2009-04-14 Intel Corporation Field effect transistor with narrow bandgap source and drain regions and method of fabrication
KR100703967B1 (ko) 2005-02-28 2007-04-05 삼성전자주식회사 씨모스 트랜지스터 및 그 제조 방법
JP4426988B2 (ja) * 2005-03-09 2010-03-03 富士通マイクロエレクトロニクス株式会社 ｐチャネルＭＯＳトランジスタの製造方法
US7470972B2 (en) * 2005-03-11 2008-12-30 Intel Corporation Complementary metal oxide semiconductor integrated circuit using uniaxial compressive stress and biaxial compressive stress
US20060202266A1 (en) 2005-03-14 2006-09-14 Marko Radosavljevic Field effect transistor with metal source/drain regions
US7160781B2 (en) * 2005-03-21 2007-01-09 Infineon Technologies Ag Transistor device and methods of manufacture thereof
US7361538B2 (en) * 2005-04-14 2008-04-22 Infineon Technologies Ag Transistors and methods of manufacture thereof
WO2006111888A1 (fr) * 2005-04-20 2006-10-26 Koninklijke Philips Electronics N.V. Circuit integre contraint et procede de production de ce dernier
US7858481B2 (en) 2005-06-15 2010-12-28 Intel Corporation Method for fabricating transistor with thinned channel
US7547637B2 (en) 2005-06-21 2009-06-16 Intel Corporation Methods for patterning a semiconductor film
US7579617B2 (en) * 2005-06-22 2009-08-25 Fujitsu Microelectronics Limited Semiconductor device and production method thereof
JP4984665B2 (ja) * 2005-06-22 2012-07-25 富士通セミコンダクター株式会社 半導体装置およびその製造方法
US8105908B2 (en) * 2005-06-23 2012-01-31 Applied Materials, Inc. Methods for forming a transistor and modulating channel stress
US7279375B2 (en) * 2005-06-30 2007-10-09 Intel Corporation Block contact architectures for nanoscale channel transistors
DE102005030583B4 (de) * 2005-06-30 2010-09-30 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung von Kontaktisolationsschichten und Silizidgebieten mit unterschiedlichen Eigenschaften eines Halbleiterbauelements und Halbleiterbauelement
CN100463143C (zh) * 2005-07-07 2009-02-18 中芯国际集成电路制造(上海)有限公司 具有氧化物间隔层的应变源漏cmos的集成方法
WO2007011789A1 (fr) * 2005-07-15 2007-01-25 Mears Technologies, Inc. Dispositif a semi-conducteur comprenant une couche a heterostructure contrainte entre au moins une paire de zones de contrainte espacees et procedes associes
US7902008B2 (en) * 2005-08-03 2011-03-08 Globalfoundries Inc. Methods for fabricating a stressed MOS device
US7642607B2 (en) * 2005-08-10 2010-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. MOS devices with reduced recess on substrate surface
US7402875B2 (en) * 2005-08-17 2008-07-22 Intel Corporation Lateral undercut of metal gate in SOI device
US7470943B2 (en) * 2005-08-22 2008-12-30 International Business Machines Corporation High performance MOSFET comprising a stressed gate metal silicide layer and method of fabricating the same
DE102005041225B3 (de) 2005-08-31 2007-04-26 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung vertiefter verformter Drain/Source-Gebiete in NMOS- und PMOS-Transistoren
US8188551B2 (en) * 2005-09-30 2012-05-29 Infineon Technologies Ag Semiconductor devices and methods of manufacture thereof
US20070052036A1 (en) * 2005-09-02 2007-03-08 Hongfa Luan Transistors and methods of manufacture thereof
US20070052037A1 (en) * 2005-09-02 2007-03-08 Hongfa Luan Semiconductor devices and methods of manufacture thereof
US8003470B2 (en) * 2005-09-13 2011-08-23 Infineon Technologies Ag Strained semiconductor device and method of making the same
US7479421B2 (en) 2005-09-28 2009-01-20 Intel Corporation Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby
US20070090416A1 (en) 2005-09-28 2007-04-26 Doyle Brian S CMOS devices with a single work function gate electrode and method of fabrication
US7947546B2 (en) * 2005-10-31 2011-05-24 Chartered Semiconductor Manufacturing, Ltd. Implant damage control by in-situ C doping during SiGe epitaxy for device applications
US7462538B2 (en) * 2005-11-15 2008-12-09 Infineon Technologies Ag Methods of manufacturing multiple gate CMOS transistors having different gate dielectric materials
US7485503B2 (en) 2005-11-30 2009-02-03 Intel Corporation Dielectric interface for group III-V semiconductor device
US7495290B2 (en) 2005-12-14 2009-02-24 Infineon Technologies Ag Semiconductor devices and methods of manufacture thereof
US7510943B2 (en) * 2005-12-16 2009-03-31 Infineon Technologies Ag Semiconductor devices and methods of manufacture thereof
US7718500B2 (en) * 2005-12-16 2010-05-18 Chartered Semiconductor Manufacturing, Ltd Formation of raised source/drain structures in NFET with embedded SiGe in PFET
US8101485B2 (en) 2005-12-16 2012-01-24 Intel Corporation Replacement gates to enhance transistor strain
WO2007091316A1 (fr) * 2006-02-08 2007-08-16 Fujitsu Limited Transistor mos a canal p et dispositif a circuit integre a semiconducteur
US20070238236A1 (en) * 2006-03-28 2007-10-11 Cook Ted Jr Structure and fabrication method of a selectively deposited capping layer on an epitaxially grown source drain
US20070246776A1 (en) * 2006-04-20 2007-10-25 Synopsys, Inc. Stress engineering for cap layer induced stress
US7541239B2 (en) * 2006-06-30 2009-06-02 Intel Corporation Selective spacer formation on transistors of different classes on the same device
DE102006035666B3 (de) * 2006-07-31 2008-04-17 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Ausbilden einer Halbleiterstruktur
US8143646B2 (en) 2006-08-02 2012-03-27 Intel Corporation Stacking fault and twin blocking barrier for integrating III-V on Si
US20080050898A1 (en) * 2006-08-23 2008-02-28 Hongfa Luan Semiconductor devices and methods of manufacture thereof
DE102006046375B4 (de) * 2006-09-29 2011-02-17 Advanced Micro Devices, Inc., Sunnyvale Feldeffekttransistor mit einer verspannten dielektrischen Schicht auf der Grundlage einer(-) Bauteiltopographie sowie Halbleiterbauelement bzw. Verfahren zur Herstellung eines Feldeffekttransistors
US8008157B2 (en) * 2006-10-27 2011-08-30 Taiwan Semiconductor Manufacturing Company, Ltd. CMOS device with raised source and drain regions
US20080124874A1 (en) * 2006-11-03 2008-05-29 Samsung Electronics Co., Ltd. Methods of Forming Field Effect Transistors Having Silicon-Germanium Source and Drain Regions
KR100773359B1 (ko) * 2006-11-20 2007-11-05 삼성전자주식회사 높은 이동도를 갖는 트랜지스터들의 제조방법 및 그에 의해제조된 트랜지스터들
US8558278B2 (en) 2007-01-16 2013-10-15 Taiwan Semiconductor Manufacturing Company, Ltd. Strained transistor with optimized drive current and method of forming
JP5100137B2 (ja) * 2007-01-26 2012-12-19 株式会社東芝 半導体装置の製造方法および半導体装置
US8536619B2 (en) * 2007-02-05 2013-09-17 Taiwan Semiconductor Manufacturing Company, Ltd. Strained MOS device and methods for forming the same
US7572706B2 (en) * 2007-02-28 2009-08-11 Freescale Semiconductor, Inc. Source/drain stressor and method therefor
US8569837B2 (en) * 2007-05-07 2013-10-29 Taiwan Semiconductor Manufacturing Company, Ltd. MOS devices having elevated source/drain regions
US7553717B2 (en) * 2007-05-11 2009-06-30 Texas Instruments Incorporated Recess etch for epitaxial SiGe
US8450165B2 (en) 2007-05-14 2013-05-28 Intel Corporation Semiconductor device having tipless epitaxial source/drain regions
US20080293192A1 (en) * 2007-05-22 2008-11-27 Stefan Zollner Semiconductor device with stressors and methods thereof
KR101264113B1 (ko) * 2007-07-16 2013-05-13 삼성전자주식회사 변형된 채널을 갖는 ｃｍｏｓ 소자 및 이의 제조방법
JP2009043760A (ja) * 2007-08-06 2009-02-26 Toshiba Corp 半導体装置
US20090115060A1 (en) * 2007-11-01 2009-05-07 Infineon Technologies Ag Integrated circuit device and method
JP5104373B2 (ja) * 2008-02-14 2012-12-19 日本ゼオン株式会社 位相差板の製造方法
US7943961B2 (en) 2008-03-13 2011-05-17 Taiwan Semiconductor Manufacturing Company, Ltd. Strain bars in stressed layers of MOS devices
US8362566B2 (en) 2008-06-23 2013-01-29 Intel Corporation Stress in trigate devices using complimentary gate fill materials
US7808051B2 (en) 2008-09-29 2010-10-05 Taiwan Semiconductor Manufacturing Company, Ltd. Standard cell without OD space effect in Y-direction
US9445967B2 (en) 2008-10-29 2016-09-20 Koninklijke Philips N.V. Automated CPR device
KR101561059B1 (ko) * 2008-11-20 2015-10-16 삼성전자주식회사 반도체 소자 및 그 제조 방법
US8093665B2 (en) * 2009-05-18 2012-01-10 Macronix International Co., Ltd. Semiconductor device and method for fabricating the same
US8487354B2 (en) * 2009-08-21 2013-07-16 Taiwan Semiconductor Manufacturing Company, Ltd. Method for improving selectivity of epi process
US8405160B2 (en) * 2010-05-26 2013-03-26 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-strained source/drain structures
US8558279B2 (en) * 2010-09-23 2013-10-15 Intel Corporation Non-planar device having uniaxially strained semiconductor body and method of making same
US8236637B2 (en) * 2010-09-29 2012-08-07 International Business Machines Corporation Planar silicide semiconductor structure
US8552503B2 (en) * 2010-11-30 2013-10-08 United Microelectronics Corp. Strained silicon structure
US8482079B2 (en) * 2011-06-15 2013-07-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacturing the same
US8847319B2 (en) 2012-03-09 2014-09-30 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy structure for multiple gate dielectric interface and methods
US8889501B2 (en) * 2012-06-01 2014-11-18 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for forming MOS devices with raised source/drain regions
CN103779276A (zh) * 2012-10-17 2014-05-07 中国科学院微电子研究所 Cmos制造方法
US9087716B2 (en) * 2013-07-15 2015-07-21 Globalfoundries Inc. Channel semiconductor alloy layer growth adjusted by impurity ion implantation
US9231102B2 (en) * 2013-08-29 2016-01-05 Taiwan Semiconductor Manufacturing Company Limited Asymmetric semiconductor device
US20150270134A1 (en) * 2014-03-19 2015-09-24 Qualcomm Incorporated Methods of forming a metal-insulator-semiconductor (mis) structure and a dual contact device
KR102316220B1 (ko) * 2014-11-14 2021-10-26 삼성전자주식회사 반도체 장치 및 그 제조 방법
US10998270B2 (en) 2016-10-28 2021-05-04 Intel Corporation Local interconnect for group IV source/drain regions
CN108231766B (zh) * 2016-12-14 2020-11-27 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法
TWI836152B (zh) * 2020-10-16 2024-03-21 鈺創科技股份有限公司 電晶體結構
CN115377181A (zh) 2021-05-21 2022-11-22 联华电子股份有限公司 半导体装置以及其制作方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6165826A (en) * 1994-12-23 2000-12-26 Intel Corporation Transistor with low resistance tip and method of fabrication in a CMOS process
US6214679B1 (en) * 1999-12-30 2001-04-10 Intel Corporation Cobalt salicidation method on a silicon germanium film
EP1231643A2 (fr) * 2001-02-09 2002-08-14 President of Tohoku University Transistor MOS à effet de champ comprenant des couches Si et SiGe ou des couches Si et SiGeC comme régions de canal
US6492216B1 (en) * 2002-02-07 2002-12-10 Taiwan Semiconductor Manufacturing Company Method of forming a transistor with a strained channel

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5155571A (en) * 1990-08-06 1992-10-13 The Regents Of The University Of California Complementary field effect transistors having strained superlattice structure
JPH10270685A (ja) * 1997-03-27 1998-10-09 Sony Corp 電界効果トランジスタとその製造方法、半導体装置とその製造方法、その半導体装置を含む論理回路および半導体基板
US6121100A (en) * 1997-12-31 2000-09-19 Intel Corporation Method of fabricating a MOS transistor with a raised source/drain extension
JP4511092B2 (ja) * 2000-12-11 2010-07-28 セイコーエプソン株式会社 半導体素子の製造方法
US6952040B2 (en) * 2001-06-29 2005-10-04 Intel Corporation Transistor structure and method of fabrication
US7002223B2 (en) * 2001-07-27 2006-02-21 Samsung Electronics Co., Ltd. Semiconductor device having elevated source/drain
US6621131B2 (en) * 2001-11-01 2003-09-16 Intel Corporation Semiconductor transistor having a stressed channel
US6756633B2 (en) * 2001-12-27 2004-06-29 Silicon Storage Technology, Inc. Semiconductor memory array of floating gate memory cells with horizontally oriented floating gate edges
KR100423904B1 (ko) * 2002-03-26 2004-03-22 삼성전자주식회사 모스 트랜지스터에 접속되는 콘택을 가진 반도체 장치의제조방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6165826A (en) * 1994-12-23 2000-12-26 Intel Corporation Transistor with low resistance tip and method of fabrication in a CMOS process
US6214679B1 (en) * 1999-12-30 2001-04-10 Intel Corporation Cobalt salicidation method on a silicon germanium film
EP1231643A2 (fr) * 2001-02-09 2002-08-14 President of Tohoku University Transistor MOS à effet de champ comprenant des couches Si et SiGe ou des couches Si et SiGeC comme régions de canal
US6492216B1 (en) * 2002-02-07 2002-12-10 Taiwan Semiconductor Manufacturing Company Method of forming a transistor with a strained channel

Also Published As

Publication number Publication date
TW200501412A (en) 2005-01-01
CN100449780C (zh) 2009-01-07
KR20060026447A (ko) 2006-03-23
EP3392905B1 (fr) 2020-03-11
AU2003297139A1 (en) 2005-02-14
EP1639636B1 (fr) 2019-03-27
EP3392905A1 (fr) 2018-10-24
TWI298948B (en) 2008-07-11
US20070034945A1 (en) 2007-02-15
KR100741238B1 (ko) 2007-07-19
EP1639636A1 (fr) 2006-03-29
US20040262683A1 (en) 2004-12-30
CN1577890A (zh) 2005-02-09
WO2005010982A1 (fr) 2005-02-03

Similar Documents

Publication Publication Date Title
SG153631A1 (en) Pmos transistor strain optimization with raised junction regions
JP2007528593A5 (fr)
WO2011162977A3 (fr) Épitaxies à dopants monocouche delta pour siliciure de source/drain incorporé
WO2008063543A3 (fr) Transistor mos amélioré en caractéristique de contrainte, et procédés pour sa fabrication
TW200515474A (en) Semiconductor device and fabrication method thereof
SG139632A1 (en) Structure and method to implement dual stressor layers with improved silicide control
WO2011037743A3 (fr) Procédé et structure destinés à former des transistors à effet de champ hautes performances à éléments de contraintes intégrés
SG143124A1 (en) Semiconductor devices having pfet with sige gate electrode and embedded sige source/drain regions and methods of making the same
WO2008127643A3 (fr) Dispositifs à semi-conducteurs à déformation améliorée et leurs procédés de fabrication
WO2008156516A3 (fr) Procédés de fabrication de dispositifs de puissance en carbure de silicium par retrait au moins partiel d'un substrat du carbure de silicium de type n et dispositifs de puissance en carbure de silicium ainsi fabriqués
TW200603294A (en) Method of making transistor with strained source/drain
GB2497060A (en) Method and structure for pFET junction profile with SiGe channel
WO2006127093A3 (fr) Procedes de fabrication de dispositifs en carbure de silicium comportant des canaux lisses
WO2009019837A1 (fr) Dispositif à semi-conducteur de carbure de silicium et son procédé de production
TW200620489A (en) Strained fully depleted silicon on insulator semiconductor device and manufacturing method therefor
JP2007520891A5 (fr)
TW200642080A (en) A novel semiconductor device with improved channel strain effect
TW200731412A (en) Semiconductor device having a trench gate the fabricating method of the same
TW200625450A (en) Substrate having silicon germanium material and stressed silicon nitride layer
TW200618068A (en) Strained semiconductor devices and method for forming at least a portion thereof
TW200607094A (en) Semiconductor device and method of manufacturing thereof
TW200746430A (en) Method of manufacturing semiconductor device, and semiconductor device
TW200729343A (en) Method for fabricating controlled stress silicon nitride films
WO2011133339A3 (fr) Stresseur intégré dopant monocouche pour cmos avancés
TW200731414A (en) Methodology for deposition of doped SEG for raised source/drain regions