WO2006111888A1 - Circuit integre contraint et procede de production de ce dernier - Google Patents

Circuit integre contraint et procede de production de ce dernier Download PDF

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Publication number
WO2006111888A1
WO2006111888A1 PCT/IB2006/051123 IB2006051123W WO2006111888A1 WO 2006111888 A1 WO2006111888 A1 WO 2006111888A1 IB 2006051123 W IB2006051123 W IB 2006051123W WO 2006111888 A1 WO2006111888 A1 WO 2006111888A1
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Prior art keywords
substrate
semiconductor element
main electrode
drain
disposed
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PCT/IB2006/051123
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English (en)
Inventor
Markus Muller
Arnaud Pouydebasque
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Koninklijke Philips Electronics N.V.
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Publication of WO2006111888A1 publication Critical patent/WO2006111888A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures

Definitions

  • a strained integrated circuit and a method of manufacturing the same.
  • An aspect of the invention relates to a strained integrated circuit and a method of manufacturing such a strained integrated circuit.
  • Another aspect of the invention relates to a strained semiconductor-on- insulator (SOI) device and a method of manufacturing such a strained semiconductor-on-insulator (SOI) device.
  • SOI semiconductor-on-insulator
  • a field effect transistor comprises a gate, a source, a drain, where a current flows from the drain to the source through a channel under the control of the gate.
  • a transistor performance may be improved by increasing the carrier mobility in the channel.
  • strain engineering has been developed in order to increase the carrier mobility.
  • ultra thin body semiconductor devices in particular semiconductor-on-insulator (SOI) devices have been developed.
  • SOI semiconductor-on-insulator
  • the semiconductor-on-insulator technology is particularly well adapted for future complementary metal-oxide semiconductor (CMOS) volume production.
  • CMOS complementary metal-oxide semiconductor
  • the patent publication US 6,787,852 describes a SOI device.
  • the SOI device includes a substrate having a buried oxide layer disposed thereon and an active layer disposed on the buried oxide layer.
  • the active layer has an active region defined by isolation regions, the active region having a source and a drain with a body disposed therebetween.
  • the source and the drain have a selectively grown silicon-germanium region disposed under an upper layer of selectively grown silicon.
  • the silicon-geranium regions form heterojunction portions respectively along the source/body junction and the drain/body junction.
  • the invention relates to an integrated circuit (for example a PMOS semiconductor element) comprising: - a first main electrode (for example a drain that is P-doped); a second main electrode (for example a source that is P-doped); a semiconductor body extending from the first main electrode to the second main electrode and supported by a substrate; a control electrode (for example a gate) disposed onto the semiconductor body; - the semiconductor body comprising a channel for letting flow current carriers from the first main electrode (the drain) to the second main electrode (the source) under the control of the control electrode (the gate); wherein each main electrode is supported by the substrate and made of a semiconductor material having a lattice structure that is different from the substrate so that a force in direction of the other main electrode is applied for laterally compressing the channel.
  • a first main electrode for example a drain that is P-doped
  • a second main electrode for example a source that is P-doped
  • a semiconductor body extending from the first main electrode to the second
  • the semiconductor body may further comprise an insulator layer supporting the semiconductor layer, the insulator layer being supported by the substrate. More precisely, the semiconductor body may comprise a semiconductor layer disposed on a buried oxide layer, the buried oxide layer being disposed on the substrate.
  • the semiconductor layer can be made of silicon and the main electrodes can be made of Silicon-Germanium.
  • the invention relates to a SOI device comprising at least one integrated circuit of the N-doped type (a N-MOS semiconductor element) and at least one integrated circuit of the P-doped type (a P-MOS semiconductor element).
  • the other integrated circuit of the N-doped type comprising a semiconductor layer disposed on a buried oxide layer, the buried oxide layer being disposed on the substrate, the semiconductor layer comprising a source and a drain that are N-doped with a channel disposed therebetween, and a gate disposed on the channel.
  • the P-MOS semiconductor element is separated from the N- MOS semiconductor element by an isolation area.
  • the invention relates to a method of manufacturing an integrated circuit (for example a PMOS semiconductor element) comprising the steps of: providing a structure comprising a substrate, a semiconductor layer disposed on the substrate and a control electrode disposed on the semiconductor layer, the semiconductor layer comprising a channel underneath the control electrode; etching the structure that is not protected by the control electrode (for example a gate) so as to expose the substrate and to define a semiconductor body underneath the electrode; and growing a first main electrode (for example a drain) and a second main electrode (for example a source) each electrode extending from the exposed substrate on both sides of the semiconductor body, the semiconductor body extending from the first main electrode to the second main electrode, each main electrode being made of a semiconductor material having a lattice structure that is different from the substrate so that a force in direction of the other main electrode is applied for laterally compressing the channel.
  • a first main electrode for example a drain
  • a second main electrode for example a source
  • the structure may be a SOI structure comprising an insulator layer supporting the semiconductor layer, the insulator layer being supported by the substrate.
  • the semiconductor layer can be made of silicon.
  • the insulator layer can be a buried oxide layer.
  • the main electrodes can be made of Silicon-Germanium.
  • the method of manufacturing a SOI device further comprises the steps of: providing a SOI structure comprising a substrate, a buried oxide layer disposed on the substrate, a semiconductor layer disposed on the buried oxide layer, the semiconductor layer being P-doped and comprising a source area and a drain area with a channel disposed therebetween, and a gate disposed on the channel; - etching the semiconductor layer of the source area and the drain area down to the buried oxide layer, and etching the buried oxide layer under the source are and the drain are down to the substrate so as to define a first substrate exposing recess and a second substrate exposing recess in place of and under the source and the drain area; and growing a material for applying a determined stress laterally compressing the channel into the recesses so as to build a strained drain and a strained source.
  • the method of manufacturing a SOI device further comprises the steps of: providing a SOI structure comprising a substrate, a buried oxide layer disposed on the substrate, a semiconductor layer disposed on the buried oxide layer, the SOI structure having a P-MOS semiconductor element and a N-MOS semiconductor element separated by an isolation area, each semiconductor element comprising a drain, a source and a gate; depositing a dielectric stack onto the N-MOS semiconductor element before the etching step; and removing the dielectric stack onto the N-active area after the growing step.
  • the method may further comprise the steps of: implanting and annealing the source and the drain of the P-MOS semiconductor element and the N-MOS semiconductor element; performing a silicidation of the source, the drain and the gate of the P-MOS semiconductor element and the N-MOS semiconductor element; and providing a plurality of contacts to the SOI structure.
  • the step of depositing the dielectric stack onto the N-MOS semiconductor element may comprise the steps of: depositing a dielectric stack onto the SOI structure; and - removing the dielectric stack from the P-MOS semiconductor element.
  • the dielectric stack can be made of a nitride layer deposited on an oxide layer.
  • the step of removing the dielectric stack onto the N-MOS semiconductor element may comprise the steps of: depositing a hard-mask onto the P-MOS semiconductor element; - etching the dielectric stack onto the N-MOS semiconductor element; and etching the hard-mask onto the P-MOS semiconductor element.
  • the step of growing the material into the recesses may be combined with a P-type in situ doping step of the drain and source of the P-MOS semiconductor element.
  • the invention allows the engineering of stress in the channel by selective epitaxy growth of Silicon-Germanium SiGe after the complete removal of the Silicon layer and the underlying buried oxide layer of the P-MOS semiconductor element.
  • Silicon-Germanium SiGe has a larger lattice parameter than Silicon
  • Silicon-Germanium SiGe grown on the exposed Si substrate will transfer a compressive stress to the channel.
  • a SOI device according to the invention is suitable for high speed performance applications.
  • the manufacturing method of the invention is easy to implement in the current CMOS transistor manufacturing process, and does not imply a substantial manufacturing cost increase.
  • FIG. 1 is a cross-section view schematically illustrating a SOI device at an intermediate manufacturing stage obtained after a known manufacturing process
  • FIG. 2A, FIG. 2B, FIG. 2C, FIG. 2D, FIG. 2E and FIG. 2F are cross-section views schematically illustrating the SOI device depicted in FIG. 1 in successive intermediate stages according to the manufacturing method of the invention.
  • FIG. 3 is a cross-section view schematically illustrating a SOI device after a final stage of the manufacturing method of the invention.
  • FIG. 1 shows in a highly diagrammatic manner a cross-section of a SOI device Ia.
  • the first intermediate SOI device Ia shown in FIG. 1 may be obtained through a conventional CMOS transistor manufacturing process.
  • the SOI device Ia comprises a P-MOS semiconductor element 20 and
  • N-MOS semiconductor element 22 The P-MOS and N-MOS semiconductor elements operate according to an enhancement-mode.
  • the P-MOS semiconductor element 20 comprises a substrate 10, a buried oxide layer 12a, a semiconductor layer 14a and isolation areas 16a, 16b, 16c.
  • the substrate is made of silicon Si.
  • the buried oxide layer 12a made of silicon oxide
  • the semiconductor layer 14a made of N-doped silicon Si, is disposed on the buried oxide layer 12a.
  • the P-MOS semiconductor element 20 is separated from the N-MOS semiconductor element 22 by the isolation area 16b.
  • the P-MOS semiconductor element 20 comprises a source area 30 and a drain area
  • the source area is a source accommodating area corresponding to an area where a future implantation of a source will be performed.
  • the drain area is a drain accommodating area corresponding to an area where a future implantation of a drain will be performed.
  • a channel 34 in the semiconductor layer 14a extends between the source area 30 and the drain area 32.
  • a gate 40 is disposed onto the channel 34.
  • the gate comprises a gate oxide layer 42 disposed onto the semiconductor layer 14a and a gate electrode 44 disposed onto the gate oxide layer.
  • the gate may further comprise a dielectric hard-mask 46 disposed onto the gate electrode 44. Additionally, wall spacers 48 are formed adjacent to the gate 40.
  • the N-MOS semiconductor element 22 is similarly constructed and will, therefore, not be further described. A main difference is that the semiconductor layer 15 within the N- MOS semiconductor element is P-doped instead of N-doped.
  • the hereinbefore described SOI device Ia may be manufactured according to the following CMOS transistor manufacturing process.
  • a SOI substrate is manufactured. Then, the SOI substrate is patterned through the formation of shallow trench isolations. Subsequently, the various channels are implanted and the gates are formed through gate oxide and gate electrode deposition.
  • a further suitable hard- mask may be deposited onto the gate electrode.
  • this will avoid a deep etching and re-growth of the gate that could affect the gate integrity.
  • the gates are etched and the gate oxide is removed from the active areas. Subsequently, the source and the drain extensions, and halos are implanted.
  • side wall spacers are formed by the deposition of a dielectric material adjacent to the gate and subsequent anisotropic etching.
  • FIGS. 2 are cross-section views schematically illustrating the successive intermediate stages of the manufacturing method of the invention. The manufacturing method of the invention is applied to the first intermediate SOI device depicted in FIG. 1.
  • FIG. 2A depicts a second intermediate SOI device Ib.
  • the second intermediate SOI device Ib is obtained by applying a stack depositing step to the first intermediate SOI device Ia depicted in FIG. 1. This step aims at depositing a dielectric stack 50 onto the N-MOS semiconductor element 22 of the SOI device Ib.
  • the dielectric stack 50 is deposited DPOl onto the P-MOS 20 and N-MOS 22 semiconductor elements of the SOI device.
  • the dielectric stack 50 may be made of a nitride layer deposited on a thin oxide layer.
  • the dielectric stack is selectively removed from the P-MOS semiconductor element 20 by using a photolithography process with an inverse N-active mask and subsequent dry etching. According to an alternative not shown in the Figures, a photolithography process with a negative resist and a conventional N-active mask can be used. Subsequently, the dielectric stack is selectively removed by dry etching from the P-MOS semiconductor element 20.
  • FIG. 2B depicts a third intermediate SOI device Ic.
  • the third intermediate SOI device Ic.
  • Ic is obtained by a source and drain etching step of the second intermediate SOI device Ib depicted in FIG. 2A.
  • the semiconductor layer 14a of the source area 30 and the drain area 32 of the P-MOS semiconductor element 20 is etched SEPl down to the buried oxide layer 12a.
  • the etching process stopped at the interface between the buried oxide layer 12a and former prior semiconductor layer 14a.
  • a former drain recess 60a and former source recess 62a are obtained in place of the former source area 30 and drain area 32.
  • a shortened semiconductor layer 14b is maintained under the gate and spacers. The shortened semiconductor layer 14b comprises the channel 34.
  • the N-MOS semiconductor element 22 is untouched.
  • FIG. 2C depicts a fourth intermediate SOI device Id.
  • the fourth intermediate SOI device Id is obtained by a buried oxide layer etching step of the third intermediate SOI device Ic depicted in FIG. 2B.
  • the buried oxide layer 12a under the former drain recess 60a and former source recess 62a is etched SEP2 down to the substrate 10.
  • the etching process stopped at the interface between the substrate 10 and the former buried oxide layer 12a.
  • the buried oxide layer 12a may be removed by a selective wet or dry etching process.
  • the buried oxide layer 12a is only removed where it is exposed to the etching process.
  • a first substrate exposing recess 60b and a second substrate exposing recess 62b are obtained in place of the former source area 30 and drain area 32 and under the former source area 30 and drain area 32.
  • a shortened buried oxide layer 12b is maintained under the shortened semiconductor layer 14b.
  • the N-MOS semiconductor element 22 is untouched.
  • the selective etching steps SEPl and SEP2 of the semiconductor layer 14a and the buried oxide layer 12a, respectively, define the substrate exposing recesses 60b and 62b in place of and under the former source area 30 and the drain area 32 of the P-MOS semiconductor element 20.
  • the selective and local removal of these layers will enable performing a subsequent selective epitaxy directly on the substrate 10. Subsequently, the exposed substrate 10 is cleaned.
  • FIG. 2D depicts a fifth intermediate SOI device Ie.
  • the fifth intermediate SOI device Ie is obtained by a material growing step into the substrate exposing recesses of the fourth intermediate SOI device Id depicted in FIG. 2C.
  • a material is grown DPO2 into the substrate exposing recesses 60b and 62b, respectively through a selective epitaxial growth.
  • the selective epitaxial growth consists in growing the material only on the substrate 10 which is exposed and not on the dielectric stack 50.
  • the material may be, for example, Silicon-Germanium SiGe.
  • the selective material growth DPO2 enables to build a strained source 130 and a strained drain 132 into the P-MOS semiconductor element 20.
  • the lattice parameter of the material is chosen larger than the one of the shortened semiconductor layer 14b.
  • a determined axial stress SF (shown by the arrows) will build up, laterally compressing the shortened semiconductor layer 14b portion, i.e. the channel 34.
  • the hole mobility into the channel 34 will be enhanced.
  • the lattice parameter of Silicon-Germanium SiGe increases linearly with the Ge content.
  • the stress is generated because of the epitaxial growth of SiGe on the Silicon substrate.
  • the lattice parameter of the Silicon substrate is maintained up to a determined critical thickness. Above the critical thickness, the elastic energy due to the crystal deformation is too high, relaxation phenomena like dislocations occur and stress is removed.
  • the Germanium Ge fraction and Silicon-Germanium SiGe thickness over the substrate may be adjusted to get a maximal strain enhancement.
  • the epitaxial growth may be combined with a P-type in- situ doping. This will enables to skip a future source and drain implantation on P-active areas 20.
  • the dielectric stack 50 protecting the N-active area 22 is removed. This may be performed in the following way.
  • FIG. 2E depicts a sixth intermediate SOI device If.
  • the sixth intermediate SOI device 1 f is obtained by a hard-mask depositing step onto the P-MOS semiconductor element and a subsequent etching step on the fifth intermediate SOI device Ie depicted in FIG. 2D.
  • a protective hard-mask 70 is deposited DPO3 onto the P-MOS semiconductor element 20 by using a photolithography technique.
  • the dielectric stack 50 onto the N-MOS semiconductor element 22 is etched SEP3. This step may be performed by using a dry etching process.
  • FIG. 2F depicts a seventh intermediate SOI device Ig.
  • the seventh intermediate SOI device Ig is obtained by a hard-mask etching step of the sixth intermediate SOI device If depicted in FIG. 2E.
  • the protective hard-mask 70 protecting the P-active areas is removed.
  • the gate hard mask 46 may be removed shortly afterwards.
  • FIG. 3 is a cross-section view schematically illustrating a final SOI device 1 according to the invention.
  • the SOI device 1 comprises the P-MOS semiconductor element 20 and the N-MOS semiconductor element 22 separated by the isolation area 16b.
  • the N-MOS semiconductor element 22 is a conventional N-MOS semiconductor element.
  • the P-MOS semiconductor element 20 comprises the strained source 130, the strained drain 132 with the channel 34 disposed therebetween, and the gate 40.
  • the channel 34 extends underneath the gate 40 from the strained source 130 to the strained drain 132.
  • the gate comprises a gate oxide layer 42 and a gate electrode 44 disposed onto the gate oxide layer.
  • the gate may further comprise a dielectric hard-mask 46 disposed onto the gate electrode 44.
  • Side wall spacers 48 are disposed adjacent to the gate 40.
  • the shortened semiconductor layer 14b disposed on the shortened buried oxide layer 12b supports the gate 40.
  • the shortened semiconductor layer 14b comprises the channel 40.
  • the shortened buried oxide layer 12b is disposed on the substrate 10.
  • the strained source 130 is made of a material filling the first substrate exposing recess
  • the material constituting the strained source 130 extends to the substrate 10 and has a lattice structure that is different from the substrate 10 so that a lateral force in direction of the strained drain 132 is applied onto the channel 34.
  • the strained drain 132 is made of a material filling the second substrate exposing recess 62b.
  • the material constituting the strained drain 132 extends to the substrate 10 and has a lattice structure that is different from the substrate 10 so that a lateral force in direction of the strained source 130 is applied onto the channel 34.
  • the semiconductor layer 14b is made of silicon.
  • the material constituting the strained source 130 and the strained drain 132 and for compressing the channel is Silicon- Germanium.
  • the substrate may have a thickness of several millimeters
  • the buried oxide layer may have a thickness ranging from 40 nm to 200 nm
  • the semiconductor layer may have a thickness ranging from 10 nm (fully depleted SOI) to 100 nm (partially depleted SOI).
  • the gate may have a height ranging from 70 nm to 120 nm and a minimum length ranging from 10 nm to 50 nm.
  • the Silicon-Germanium material may have a Germanium Ge concentration ranging from 20 % to 30%.
  • the thickness of the grown material may be less than 70 nm in order to avoid dislocations.
  • junction leakage may increase power consumption when the SOI device is in a standby mode.
  • smart implantations optimization of the junction dopant profile
  • the junction leakage is acceptable in applications where speed performance is more important than a relatively high standby power.
  • the isolation between N-MOS semiconductor element and P-MOS semiconductor element is guaranteed by the buried oxide layer under the N-MOS semiconductor element and the shallow trench isolation areas.
  • the gate which is underneath the gate electrode, is a well-defined channel like in conventional SOI devices. Consequently, the gate can precisely be controlled by means of a voltage applied to the gate electrode. That is, the device in accordance with the invention has many advantages similar to those of conventional SOI devices.
  • a further advantage of the invention is the improved heat dissipation compared to conventional SOI devices.
  • the Silicon-Germanium material enables enhanced heat dissipation towards the substrate because the Silicon-Germanium/Silicon interface has a higher thermal conductivity with respect to silicon oxide.
  • the final SOI device 1 depicted in FIG. 3 may be further processed in a conventional manner (CMOS transistor manufacturing process).
  • CMOS transistor manufacturing process For example, the source and the drain of the P-active area and the N-active area implanting and annealing steps are performed.
  • the source and the drain of the N-active area implanting step is performed when the material epitaxial growth is combined with a P-type in- situ doping.
  • the source, the drain and the gate of the P-active area and the N-active area silicidation step is performed.
  • a plurality of contacts is provided to the SOI structure.
  • the conventional back-end process is performed.
  • Aluminum Al or Copper Cu back- end may be used for various metal layers.
  • the semiconductor layer is made of silicon.
  • the material for applying a determined stress laterally compressing the channel is Silicon-Germanium.
  • the lattice parameter of the material is larger than the one of material constituting the semiconductor layer and that the material can be grown epitaxially onto the semiconductor layer.
  • SOI device comprising one P-MOS semiconductor element and one N-MOS semiconductor element

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

Un circuit intégré comprend: une première électrode principale (130), une deuxième électrode principale (132), un corps semiconducteur (12b, 14b) qui s'étend entre la première électrode principale (130) et la deuxième électrode principale (132) et qui est supporté par un substrat (10). Une électrode de commande (40) est située sur le corps semiconducteur, ledit corps semiconducteur comprenant un passage (34) qui laisse s'écouler les porteurs de charge entre la première électrode principale (130) et la deuxième électrode principale (132) sous la commande de l'électrode de commande (40), chaque électrode principale (130) et (132) étant supportée par le substrat (10) et formée d'un matériau semiconducteur présentant une structure maillée qui est différente de celle du substrat, de sorte que, une force SF dirigée vers l'autre électrode principale (132) et (130) s'applique pour comprimer latéralement le passage (34).
PCT/IB2006/051123 2005-04-20 2006-04-12 Circuit integre contraint et procede de production de ce dernier WO2006111888A1 (fr)

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EP1989729A4 (fr) * 2006-02-24 2011-04-20 Freescale Semiconductor Inc Procédé de fabrication semi-conducteur intégrant des éléments de contrainte et éléments de contrainte de couches diélectriques interniveaux
FR3036530A1 (fr) * 2015-05-19 2016-11-25 St Microelectronics Sa Procede de realisation de cellules memoires du type a programmation unique comportant des condensateurs mos et circuit integre correspondant
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US9881928B2 (en) 2015-05-19 2018-01-30 Stmicroelectronics Sa Method for producing one-time-programmable memory cells and corresponding integrated circuit

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