SG137807A1 - Process for improving copper line cap formation - Google Patents
Process for improving copper line cap formationInfo
- Publication number
- SG137807A1 SG137807A1 SG200703632-0A SG2007036320A SG137807A1 SG 137807 A1 SG137807 A1 SG 137807A1 SG 2007036320 A SG2007036320 A SG 2007036320A SG 137807 A1 SG137807 A1 SG 137807A1
- Authority
- SG
- Singapore
- Prior art keywords
- low
- conductive line
- opening
- dielectric layer
- diffusion barrier
- Prior art date
Links
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title 1
- 230000015572 biosynthetic process Effects 0.000 title 1
- 229910052802 copper Inorganic materials 0.000 title 1
- 239000010949 copper Substances 0.000 title 1
- 230000004888 barrier function Effects 0.000 abstract 3
- 238000009792 diffusion process Methods 0.000 abstract 3
- 239000004065 semiconductor Substances 0.000 abstract 2
- 239000000758 substrate Substances 0.000 abstract 2
- 239000002184 metal Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
- H01L21/02074—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a planarization of conductive layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76865—Selective removal of parts of the layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Chemically Coating (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US80148906P | 2006-05-18 | 2006-05-18 | |
US11/605,893 US8193087B2 (en) | 2006-05-18 | 2006-11-28 | Process for improving copper line cap formation |
Publications (1)
Publication Number | Publication Date |
---|---|
SG137807A1 true SG137807A1 (en) | 2007-12-28 |
Family
ID=38651042
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG200703632-0A SG137807A1 (en) | 2006-05-18 | 2007-05-18 | Process for improving copper line cap formation |
Country Status (6)
Country | Link |
---|---|
US (2) | US8193087B2 (ja) |
JP (1) | JP4436384B2 (ja) |
KR (1) | KR100895865B1 (ja) |
CN (1) | CN101075578B (ja) |
FR (1) | FR2901406B1 (ja) |
SG (1) | SG137807A1 (ja) |
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JP4836092B2 (ja) * | 2008-03-19 | 2011-12-14 | 国立大学法人東北大学 | 半導体装置の形成方法 |
US7846841B2 (en) * | 2008-09-30 | 2010-12-07 | Tokyo Electron Limited | Method for forming cobalt nitride cap layers |
JP2010177393A (ja) * | 2009-01-29 | 2010-08-12 | Sony Corp | 半導体記憶装置およびその製造方法 |
CN102044475A (zh) * | 2009-10-13 | 2011-05-04 | 中芯国际集成电路制造(上海)有限公司 | 互连结构及其形成方法 |
CN102064098B (zh) * | 2009-11-17 | 2012-10-24 | 台湾积体电路制造股份有限公司 | 从填充有中间层的沟槽生长ⅲ-ⅴ化合物半导体 |
US8304906B2 (en) * | 2010-05-28 | 2012-11-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Partial air gap formation for providing interconnect isolation in integrated circuits |
US8461683B2 (en) * | 2011-04-01 | 2013-06-11 | Intel Corporation | Self-forming, self-aligned barriers for back-end interconnects and methods of making same |
JP5857615B2 (ja) * | 2011-10-17 | 2016-02-10 | 富士通株式会社 | 電子装置およびその製造方法 |
JP6054049B2 (ja) * | 2012-03-27 | 2016-12-27 | 東京エレクトロン株式会社 | めっき処理方法、めっき処理システムおよび記憶媒体 |
US8669176B1 (en) * | 2012-08-28 | 2014-03-11 | Globalfoundries Inc. | BEOL integration scheme for copper CMP to prevent dendrite formation |
US8896090B2 (en) * | 2013-02-22 | 2014-11-25 | International Business Machines Corporation | Electrical fuses and methods of making electrical fuses |
US9209073B2 (en) | 2013-03-12 | 2015-12-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal cap apparatus and method |
US10032712B2 (en) * | 2013-03-15 | 2018-07-24 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor structure |
US8860229B1 (en) | 2013-07-16 | 2014-10-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Hybrid bonding with through substrate via (TSV) |
US9087821B2 (en) | 2013-07-16 | 2015-07-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Hybrid bonding with through substrate via (TSV) |
US9299640B2 (en) | 2013-07-16 | 2016-03-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Front-to-back bonding with through-substrate via (TSV) |
US9929050B2 (en) * | 2013-07-16 | 2018-03-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms for forming three-dimensional integrated circuit (3DIC) stacking structure |
US9349636B2 (en) * | 2013-09-26 | 2016-05-24 | Intel Corporation | Interconnect wires including relatively low resistivity cores |
US20150206798A1 (en) * | 2014-01-17 | 2015-07-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect Structure And Method of Forming |
CN103904025A (zh) * | 2014-03-24 | 2014-07-02 | 上海华力微电子有限公司 | 提高金属连线电迁移可靠性的方法 |
US9324650B2 (en) * | 2014-08-15 | 2016-04-26 | International Business Machines Corporation | Interconnect structures with fully aligned vias |
CN107004633B (zh) * | 2014-12-22 | 2020-10-30 | 英特尔公司 | 使用交替硬掩模和密闭性蚀刻停止衬垫方案使紧密间距导电层与引导通孔接触的方法和结构 |
CN109216267A (zh) * | 2014-12-23 | 2019-01-15 | 英特尔公司 | 解耦过孔填充 |
US9633941B2 (en) | 2015-08-21 | 2017-04-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device structure and method for forming the same |
US9893120B2 (en) * | 2016-04-15 | 2018-02-13 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure and method of forming the same |
KR102662612B1 (ko) | 2016-10-02 | 2024-05-03 | 어플라이드 머티어리얼스, 인코포레이티드 | 루테늄 라이너로 구리 전자 이동을 개선하기 위한 도핑된 선택적 금속 캡 |
US10109524B2 (en) * | 2017-01-24 | 2018-10-23 | Globalfoundries Inc. | Recessing of liner and conductor for via formation |
US10832946B1 (en) | 2019-04-24 | 2020-11-10 | International Business Machines Corporation | Recessed interconnet line having a low-oxygen cap for facilitating a robust planarization process and protecting the interconnect line from downstream etch operations |
US11227833B2 (en) * | 2019-09-16 | 2022-01-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interconnect structure and method for forming the same |
US11222843B2 (en) * | 2019-09-16 | 2022-01-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interconnect structure and method for forming the same |
CN112582336A (zh) * | 2019-09-29 | 2021-03-30 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件的形成方法 |
US20220084948A1 (en) * | 2020-09-17 | 2022-03-17 | Nanya Technology Corporation | Semiconductor structure and manufacturing method thereof |
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US7332422B2 (en) * | 2005-01-05 | 2008-02-19 | Chartered Semiconductor Manufacturing, Ltd. | Method for CuO reduction by using two step nitrogen oxygen and reducing plasma treatment |
US20060205204A1 (en) * | 2005-03-14 | 2006-09-14 | Michael Beck | Method of making a semiconductor interconnect with a metal cap |
KR100729126B1 (ko) * | 2005-11-15 | 2007-06-14 | 동부일렉트로닉스 주식회사 | 반도체 소자의 금속 배선 및 그 형성 방법 |
US20070228571A1 (en) * | 2006-04-04 | 2007-10-04 | Chen-Hua Yu | Interconnect structure having a silicide/germanide cap layer |
US20070249156A1 (en) * | 2006-04-20 | 2007-10-25 | Griselda Bonilla | Method for enabling hard mask free integration of ultra low-k materials and structures produced thereby |
-
2006
- 2006-11-28 US US11/605,893 patent/US8193087B2/en active Active
-
2007
- 2007-05-16 JP JP2007131029A patent/JP4436384B2/ja active Active
- 2007-05-17 KR KR1020070048307A patent/KR100895865B1/ko active IP Right Grant
- 2007-05-17 CN CN2007101039545A patent/CN101075578B/zh active Active
- 2007-05-18 FR FR0703572A patent/FR2901406B1/fr active Active
- 2007-05-18 SG SG200703632-0A patent/SG137807A1/en unknown
-
2012
- 2012-04-05 US US13/440,704 patent/US8623760B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
KR100895865B1 (ko) | 2009-05-06 |
FR2901406B1 (fr) | 2013-12-20 |
KR20070112035A (ko) | 2007-11-22 |
US20120190191A1 (en) | 2012-07-26 |
US8623760B2 (en) | 2014-01-07 |
CN101075578A (zh) | 2007-11-21 |
JP4436384B2 (ja) | 2010-03-24 |
JP2007311799A (ja) | 2007-11-29 |
CN101075578B (zh) | 2010-09-15 |
US20070269978A1 (en) | 2007-11-22 |
FR2901406A1 (fr) | 2007-11-23 |
US8193087B2 (en) | 2012-06-05 |
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