SG136030A1 - Method for manufacturing compound material wafers and method for recycling a used donor substrate - Google Patents
Method for manufacturing compound material wafers and method for recycling a used donor substrateInfo
- Publication number
- SG136030A1 SG136030A1 SG200700657-0A SG2007006570A SG136030A1 SG 136030 A1 SG136030 A1 SG 136030A1 SG 2007006570 A SG2007006570 A SG 2007006570A SG 136030 A1 SG136030 A1 SG 136030A1
- Authority
- SG
- Singapore
- Prior art keywords
- recycling
- compound material
- manufacturing compound
- material wafers
- donor substrate
- Prior art date
Links
- 238000000034 method Methods 0.000 title abstract 5
- 150000001875 compounds Chemical class 0.000 title abstract 3
- 238000004519 manufacturing process Methods 0.000 title abstract 3
- 239000000463 material Substances 0.000 title abstract 3
- 238000004064 recycling Methods 0.000 title abstract 3
- 239000000758 substrate Substances 0.000 title abstract 3
- 235000012431 wafers Nutrition 0.000 title abstract 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract 1
- 229910052760 oxygen Inorganic materials 0.000 abstract 1
- 239000001301 oxygen Substances 0.000 abstract 1
- 239000002244 precipitate Substances 0.000 abstract 1
- 238000007669 thermal treatment Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02032—Preparing bulk and homogeneous wafers by reclaiming or re-processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Element Separation (AREA)
- Recrystallisation Techniques (AREA)
- Formation Of Insulating Films (AREA)
- Separation, Recovery Or Treatment Of Waste Materials Containing Plastics (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP06290421.4A EP1835533B1 (en) | 2006-03-14 | 2006-03-14 | Method for manufacturing compound material wafers and method for recycling a used donor substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| SG136030A1 true SG136030A1 (en) | 2007-10-29 |
Family
ID=36940653
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| SG200700657-0A SG136030A1 (en) | 2006-03-14 | 2007-01-29 | Method for manufacturing compound material wafers and method for recycling a used donor substrate |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US7405136B2 (ko) |
| EP (1) | EP1835533B1 (ko) |
| JP (1) | JP4928932B2 (ko) |
| KR (1) | KR100886620B1 (ko) |
| CN (1) | CN100541759C (ko) |
| SG (1) | SG136030A1 (ko) |
| TW (1) | TWI334165B (ko) |
Families Citing this family (29)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4715470B2 (ja) * | 2005-11-28 | 2011-07-06 | 株式会社Ｓｕｍｃｏ | 剥離ウェーハの再生加工方法及びこの方法により再生加工された剥離ウェーハ |
| JP5314838B2 (ja) * | 2006-07-14 | 2013-10-16 | 信越半導体株式会社 | 剥離ウェーハを再利用する方法 |
| JP5289805B2 (ja) * | 2007-05-10 | 2013-09-11 | 株式会社半導体エネルギー研究所 | 半導体装置製造用基板の作製方法 |
| US7781308B2 (en) * | 2007-12-03 | 2010-08-24 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing SOI substrate |
| CN101504930B (zh) * | 2008-02-06 | 2013-10-16 | 株式会社半导体能源研究所 | Soi衬底的制造方法 |
| DE102008027521B4 (de) * | 2008-06-10 | 2017-07-27 | Infineon Technologies Austria Ag | Verfahren zum Herstellen einer Halbleiterschicht |
| US8871610B2 (en) * | 2008-10-02 | 2014-10-28 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing SOI substrate |
| JP5410769B2 (ja) * | 2009-01-30 | 2014-02-05 | グローバルウェーハズ・ジャパン株式会社 | シリコンウェーハの熱処理方法 |
| US8198172B2 (en) * | 2009-02-25 | 2012-06-12 | Micron Technology, Inc. | Methods of forming integrated circuits using donor and acceptor substrates |
| US8048773B2 (en) * | 2009-03-24 | 2011-11-01 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing SOI substrate |
| SG166060A1 (en) * | 2009-04-22 | 2010-11-29 | Semiconductor Energy Lab | Method of manufacturing soi substrate |
| US8318588B2 (en) * | 2009-08-25 | 2012-11-27 | Semiconductor Energy Laboratory Co., Ltd. | Method for reprocessing semiconductor substrate, method for manufacturing reprocessed semiconductor substrate, and method for manufacturing SOI substrate |
| KR101731809B1 (ko) * | 2009-10-09 | 2017-05-02 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 기판의 재생 방법, 재생된 반도체 기판의 제조 방법, 및 ｓｏｉ 기판의 제조 방법 |
| US8367517B2 (en) * | 2010-01-26 | 2013-02-05 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing SOI substrate |
| EP2614518A4 (en) * | 2010-09-10 | 2016-02-10 | VerLASE TECHNOLOGIES LLC | METHODS OF MANUFACTURING OPTOELECTRONIC DEVICES USING SEMICONDUCTOR DONOR DETACHED LAYERS AND DEVICES MANUFACTURED THEREBY |
| US9123529B2 (en) | 2011-06-21 | 2015-09-01 | Semiconductor Energy Laboratory Co., Ltd. | Method for reprocessing semiconductor substrate, method for manufacturing reprocessed semiconductor substrate, and method for manufacturing SOI substrate |
| FR2987166B1 (fr) * | 2012-02-16 | 2017-05-12 | Soitec Silicon On Insulator | Procede de transfert d'une couche |
| FR2987682B1 (fr) | 2012-03-05 | 2014-11-21 | Soitec Silicon On Insulator | Procede de test d'une structure semi-conducteur sur isolant et application dudit test pour la fabrication d'une telle structure |
| US8747598B2 (en) * | 2012-04-25 | 2014-06-10 | Gtat Corporation | Method of forming a permanently supported lamina |
| FR2999801B1 (fr) | 2012-12-14 | 2014-12-26 | Soitec Silicon On Insulator | Procede de fabrication d'une structure |
| US9082692B2 (en) | 2013-01-02 | 2015-07-14 | Micron Technology, Inc. | Engineered substrate assemblies with epitaxial templates and related systems, methods, and devices |
| TW201444118A (zh) * | 2013-05-03 | 2014-11-16 | Univ Dayeh | 具有氮化鎵磊晶層的藍寶石基板的回收方法 |
| JP6100200B2 (ja) * | 2014-04-24 | 2017-03-22 | 信越半導体株式会社 | 貼り合わせｓｏｉウェーハの製造方法 |
| FR3051968B1 (fr) * | 2016-05-25 | 2018-06-01 | Soitec | Procede de fabrication d'un substrat semi-conducteur a haute resistivite |
| FI128442B (en) * | 2017-06-21 | 2020-05-15 | Turun Yliopisto | Silicon structure with crystalline silica |
| FR3076069B1 (fr) * | 2017-12-22 | 2021-11-26 | Commissariat Energie Atomique | Procede de transfert d'une couche utile |
| FR3076070B1 (fr) * | 2017-12-22 | 2019-12-27 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Procede de transfert d'une couche utile |
| DE102018122979B4 (de) * | 2018-06-13 | 2023-11-02 | Infineon Technologies Ag | Verfahren zum bilden einer silicium-isolator-schicht und halbleitervorrichtung mit derselben |
| CN110223995B (zh) * | 2019-06-14 | 2021-11-02 | 芯盟科技有限公司 | 一种图像传感器的形成方法、图像传感器及电子设备 |
Family Cites Families (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3932369B2 (ja) | 1998-04-09 | 2007-06-20 | 信越半導体株式会社 | 剥離ウエーハを再利用する方法および再利用に供されるシリコンウエーハ |
| JPH11307747A (ja) * | 1998-04-17 | 1999-11-05 | Nec Corp | Ｓｏｉ基板およびその製造方法 |
| JP3500063B2 (ja) * | 1998-04-23 | 2004-02-23 | 信越半導体株式会社 | 剥離ウエーハを再利用する方法および再利用に供されるシリコンウエーハ |
| JP3697106B2 (ja) * | 1998-05-15 | 2005-09-21 | キヤノン株式会社 | 半導体基板の作製方法及び半導体薄膜の作製方法 |
| US6436846B1 (en) * | 1998-09-03 | 2002-08-20 | Siemens Aktiengesellscharft | Combined preanneal/oxidation step using rapid thermal processing |
| JP3750526B2 (ja) * | 1999-03-16 | 2006-03-01 | 信越半導体株式会社 | シリコンウエーハの製造方法及びシリコンウエーハ |
| JP2001144275A (ja) * | 1999-08-27 | 2001-05-25 | Shin Etsu Handotai Co Ltd | 貼り合わせｓｏｉウエーハの製造方法および貼り合わせｓｏｉウエーハ |
| JP3943782B2 (ja) * | 1999-11-29 | 2007-07-11 | 信越半導体株式会社 | 剥離ウエーハの再生処理方法及び再生処理された剥離ウエーハ |
| KR100549258B1 (ko) * | 2000-06-02 | 2006-02-03 | 주식회사 실트론 | 에스오아이 웨이퍼 제조 방법 |
| FR2838865B1 (fr) * | 2002-04-23 | 2005-10-14 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat avec couche utile sur support de resistivite elevee |
| US7074623B2 (en) * | 2002-06-07 | 2006-07-11 | Amberwave Systems Corporation | Methods of forming strained-semiconductor-on-insulator finFET device structures |
| JP2004193515A (ja) * | 2002-12-13 | 2004-07-08 | Shin Etsu Handotai Co Ltd | Ｓｏｉウエーハの製造方法 |
| US20040187769A1 (en) * | 2003-03-27 | 2004-09-30 | Yoshirou Aoki | Method of producing SOI wafer |
| JP4869544B2 (ja) * | 2003-04-14 | 2012-02-08 | 株式会社Ｓｕｍｃｏ | Ｓｏｉ基板の製造方法 |
| FR2857982B1 (fr) | 2003-07-24 | 2007-05-18 | Soitec Silicon On Insulator | Procede de fabrication d'une couche epitaxiee |
| KR20050013398A (ko) * | 2003-07-28 | 2005-02-04 | 주식회사 실트론 | 실리콘 단결정 웨이퍼 및 ｓｏｉ 웨이퍼의 제조방법 |
| DE10336271B4 (de) * | 2003-08-07 | 2008-02-07 | Siltronic Ag | Siliciumscheibe und Verfahren zu deren Herstellung |
| FR2867310B1 (fr) | 2004-03-05 | 2006-05-26 | Soitec Silicon On Insulator | Technique d'amelioration de la qualite d'une couche mince prelevee |
| FR2867607B1 (fr) * | 2004-03-10 | 2006-07-14 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat pour la microelectronique, l'opto-electronique et l'optique avec limitaton des lignes de glissement et substrat correspondant |
| JP4715470B2 (ja) * | 2005-11-28 | 2011-07-06 | 株式会社Ｓｕｍｃｏ | 剥離ウェーハの再生加工方法及びこの方法により再生加工された剥離ウェーハ |
-
2006
- 2006-03-14 EP EP06290421.4A patent/EP1835533B1/en active Active
- 2006-06-21 US US11/472,693 patent/US7405136B2/en active Active
- 2006-12-22 TW TW095148607A patent/TWI334165B/zh active
- 2006-12-25 JP JP2006348136A patent/JP4928932B2/ja active Active
-
2007
- 2007-01-03 KR KR1020070000569A patent/KR100886620B1/ko active IP Right Grant
- 2007-01-17 CN CNB2007100019671A patent/CN100541759C/zh active Active
- 2007-01-29 SG SG200700657-0A patent/SG136030A1/en unknown
Also Published As
| Publication number | Publication date |
|---|---|
| KR20070093798A (ko) | 2007-09-19 |
| JP4928932B2 (ja) | 2012-05-09 |
| US20070216042A1 (en) | 2007-09-20 |
| TW200741821A (en) | 2007-11-01 |
| EP1835533A1 (en) | 2007-09-19 |
| KR100886620B1 (ko) | 2009-03-05 |
| TWI334165B (en) | 2010-12-01 |
| CN101038890A (zh) | 2007-09-19 |
| EP1835533B1 (en) | 2020-06-03 |
| US7405136B2 (en) | 2008-07-29 |
| CN100541759C (zh) | 2009-09-16 |
| JP2007251129A (ja) | 2007-09-27 |
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