SG11201907968XA - Process for fabricating a donor substrate for forming optoelectronic devices, collection of substrates issued from this process - Google Patents

Process for fabricating a donor substrate for forming optoelectronic devices, collection of substrates issued from this process

Info

Publication number
SG11201907968XA
SG11201907968XA SG11201907968XA SG11201907968XA SG11201907968XA SG 11201907968X A SG11201907968X A SG 11201907968XA SG 11201907968X A SG11201907968X A SG 11201907968XA SG 11201907968X A SG11201907968X A SG 11201907968XA SG 11201907968X A SG11201907968X A SG 11201907968XA
Authority
SG
Singapore
Prior art keywords
donor substrate
issued
substrates
collection
fabricating
Prior art date
Application number
SG11201907968XA
Other languages
English (en)
Inventor
David Sotta
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Publication of SG11201907968XA publication Critical patent/SG11201907968XA/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02387—Group 13/15 materials
    • H01L21/02389—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H01L21/3245—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering of AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Led Devices (AREA)
  • Recrystallisation Techniques (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
SG11201907968XA 2017-03-01 2018-02-26 Process for fabricating a donor substrate for forming optoelectronic devices, collection of substrates issued from this process SG11201907968XA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1751666A FR3063571B1 (fr) 2017-03-01 2017-03-01 Procede de fabrication d'un substrat donneur pour la formation de dispositifs optoelectroniques, collection de substrats issus de ce procede
PCT/FR2018/050446 WO2018158529A1 (fr) 2017-03-01 2018-02-26 Procede de fabrication d'un substrat donneur pour la formation de dispositifs optoelectroniques

Publications (1)

Publication Number Publication Date
SG11201907968XA true SG11201907968XA (en) 2019-09-27

Family

ID=59579670

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201907968XA SG11201907968XA (en) 2017-03-01 2018-02-26 Process for fabricating a donor substrate for forming optoelectronic devices, collection of substrates issued from this process

Country Status (9)

Country Link
US (2) US11245050B2 (fr)
EP (1) EP3590129B1 (fr)
JP (1) JP6980964B2 (fr)
KR (1) KR102431046B1 (fr)
CN (1) CN110383421B (fr)
FR (1) FR3063571B1 (fr)
SG (1) SG11201907968XA (fr)
TW (1) TWI752176B (fr)
WO (1) WO2018158529A1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3091005B1 (fr) 2018-12-21 2021-01-29 Soitec Silicon On Insulator Substrat de croissance et procede de fabrication d’un tel substrat
GB2586862B (en) * 2019-09-06 2021-12-15 Plessey Semiconductors Ltd LED precursor incorporating strain relaxing structure
FR3103627B1 (fr) * 2019-11-25 2023-03-24 Soitec Silicon On Insulator Procede de production d'un substrat comprenant une etape de traitement thermique de relaxation

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6774015B1 (en) * 2002-12-19 2004-08-10 International Business Machines Corporation Strained silicon-on-insulator (SSOI) and method to form the same
JP5190923B2 (ja) * 2007-07-24 2013-04-24 独立行政法人産業技術総合研究所 ＧａＮをチャネル層とする窒化物半導体トランジスタ及びその作製方法
EP2151852B1 (fr) * 2008-08-06 2020-01-15 Soitec Relâchement et transfert de couches tendues
KR20110063773A (ko) * 2008-09-24 2011-06-14 에스.오.아이. 테크 실리콘 온 인슐레이터 테크놀로지스 릴랙싱된 반도체 재료층들을 형성하는 방법들, 반도체 구조들, 디바이스들 및 그를 포함하는 엔지니어링된 기판들
US9117944B2 (en) 2008-09-24 2015-08-25 Koninklijke Philips N.V. Semiconductor light emitting devices grown on composite substrates
FR2936903B1 (fr) * 2008-10-07 2011-01-14 Soitec Silicon On Insulator Relaxation d'une couche de materiau contraint avec application d'un raidisseur
EP2502266B1 (fr) * 2009-11-18 2020-03-04 Soitec Procédés de fabrication de structures semi-conductrices et dispositifs à semi-conducteurs au moyen de couches de liaison de verre, et structures semi-conductrices et dispositifs à semi-conducteurs formés par de tels procédés
CN102136536A (zh) * 2010-01-25 2011-07-27 亚威朗(美国) 应变平衡发光器件
FR2973157B1 (fr) * 2011-03-25 2014-03-14 Soitec Silicon On Insulator Procédé de réalisation d'ilots de matériau contraint au moins partiellement relaxe
US9343303B2 (en) * 2014-03-20 2016-05-17 Samsung Electronics Co., Ltd. Methods of forming low-defect strain-relaxed layers on lattice-mismatched substrates and related semiconductor structures and devices
US11015186B2 (en) 2016-09-27 2021-05-25 Abbott Molecular Inc. Maximizing DNA yield of blood specimens collected in rapid clot tubes

Also Published As

Publication number Publication date
JP6980964B2 (ja) 2021-12-15
US11735685B2 (en) 2023-08-22
EP3590129A1 (fr) 2020-01-08
TWI752176B (zh) 2022-01-11
KR102431046B1 (ko) 2022-08-11
TW201842540A (zh) 2018-12-01
JP2020511779A (ja) 2020-04-16
FR3063571A1 (fr) 2018-09-07
US20200013921A1 (en) 2020-01-09
KR20190117746A (ko) 2019-10-16
CN110383421A (zh) 2019-10-25
FR3063571B1 (fr) 2021-04-30
WO2018158529A1 (fr) 2018-09-07
US20210351318A1 (en) 2021-11-11
US11245050B2 (en) 2022-02-08
EP3590129B1 (fr) 2020-11-04
CN110383421B (zh) 2023-02-28

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