FR3103627B1 - Procede de production d'un substrat comprenant une etape de traitement thermique de relaxation - Google Patents

Procede de production d'un substrat comprenant une etape de traitement thermique de relaxation Download PDF

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Publication number
FR3103627B1
FR3103627B1 FR1913159A FR1913159A FR3103627B1 FR 3103627 B1 FR3103627 B1 FR 3103627B1 FR 1913159 A FR1913159 A FR 1913159A FR 1913159 A FR1913159 A FR 1913159A FR 3103627 B1 FR3103627 B1 FR 3103627B1
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France
Prior art keywords
layer
producing
substrate
indium
heat treatment
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Active
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FR1913159A
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English (en)
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FR3103627A1 (fr
Inventor
Mariia Rozhavskaia
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Soitec SA
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Soitec SA
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Priority to FR1913159A priority Critical patent/FR3103627B1/fr
Publication of FR3103627A1 publication Critical patent/FR3103627A1/fr
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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer

Abstract

L'invention concerne un procédé de production d'un substrat de croissance comprenant la préparation d'un substrat donneur (2) en formant une couche de surface cristalline semi-conductrice (1) sur une couche germe (2a) d'un support (2b). La préparation de la couche de surface (1) comprend la formation d'une couche primaire (1a) comprenant de l'indium, du gallium et de l'azote directement sur la couche germe (2a), puis la formation d'une couche secondaire (1b) comprenant de l'indium, du gallium et de l'azote directement sur la couche primaire (1a), la couche secondaire (1b) présentant un paramètre naturel de maille supérieur à une couche d'InGaN contenant 8% d'indium et la couche primaire (1a) présentant un paramètre naturel de maille inférieur à celui du maille naturel de la couche secondaire (1b). Figure à publier avec l'abrégé : Fig. 1
FR1913159A 2019-11-25 2019-11-25 Procede de production d'un substrat comprenant une etape de traitement thermique de relaxation Active FR3103627B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR1913159A FR3103627B1 (fr) 2019-11-25 2019-11-25 Procede de production d'un substrat comprenant une etape de traitement thermique de relaxation

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1913159A FR3103627B1 (fr) 2019-11-25 2019-11-25 Procede de production d'un substrat comprenant une etape de traitement thermique de relaxation
FR1913159 2019-11-25

Publications (2)

Publication Number Publication Date
FR3103627A1 FR3103627A1 (fr) 2021-05-28
FR3103627B1 true FR3103627B1 (fr) 2023-03-24

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Family Applications (1)

Application Number Title Priority Date Filing Date
FR1913159A Active FR3103627B1 (fr) 2019-11-25 2019-11-25 Procede de production d'un substrat comprenant une etape de traitement thermique de relaxation

Country Status (1)

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FR (1) FR3103627B1 (fr)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2151852B1 (fr) 2008-08-06 2020-01-15 Soitec Relâchement et transfert de couches tendues
EP2151856A1 (fr) 2008-08-06 2010-02-10 S.O.I. TEC Silicon Relâchement de couches tendues
FR3063571B1 (fr) * 2017-03-01 2021-04-30 Soitec Silicon On Insulator Procede de fabrication d'un substrat donneur pour la formation de dispositifs optoelectroniques, collection de substrats issus de ce procede
FR3079070B1 (fr) * 2018-03-13 2020-02-28 Soitec Procede de fabrication d'une pluralite d'ilots semi-conducteurs cristallins presentant une variete de parametres de maille
EP4033531B1 (fr) * 2017-03-17 2023-08-02 Soitec Procédé de fabrication d'une pluralité d'îlots semiconducteurs cristallins

Also Published As

Publication number Publication date
FR3103627A1 (fr) 2021-05-28

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