SG11201806451VA - Method and system for forming memory fin patterns - Google Patents
Method and system for forming memory fin patternsInfo
- Publication number
- SG11201806451VA SG11201806451VA SG11201806451VA SG11201806451VA SG11201806451VA SG 11201806451V A SG11201806451V A SG 11201806451VA SG 11201806451V A SG11201806451V A SG 11201806451VA SG 11201806451V A SG11201806451V A SG 11201806451VA SG 11201806451V A SG11201806451V A SG 11201806451VA
- Authority
- SG
- Singapore
- Prior art keywords
- international
- etch
- ho1l
- pct
- cuts
- Prior art date
Links
- 238000000034 method Methods 0.000 title abstract 5
- 239000000463 material Substances 0.000 abstract 3
- UTFVTJYLPLJXBI-UHFFFAOYSA-N Austin Natural products CC1OC(=O)C2C3C(C)(OC(=O)C13O)C(OC(=O)C)C4=C(C)C5(CCC24C)C=CC(=O)OC5(C)C UTFVTJYLPLJXBI-UHFFFAOYSA-N 0.000 abstract 1
- 244000000188 Vaccinium ovalifolium Species 0.000 abstract 1
- DEMDOYQPCDXCEB-WLEVADLXSA-N [(1S,2R,5S,8R,9R,12S,13S)-12-hydroxy-2,2',2',6,9,13-hexamethyl-16-methylidene-6',11,15-trioxospiro[10,14-dioxatetracyclo[7.6.1.01,12.02,7]hexadec-6-ene-5,3'-pyran]-8-yl] acetate Chemical compound C1([C@@H](OC(C)=O)[C@@]2(C)C(=C)[C@]3([C@@]1(CC1)C)C(=O)O[C@H]([C@@]3(C(=O)O2)O)C)=C(C)[C@]21C=CC(=O)OC2(C)C DEMDOYQPCDXCEB-WLEVADLXSA-N 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 230000008520 organization Effects 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
- H10B12/056—Making the transistor the transistor being a FinFET
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/0002—Lithographic processes using patterning methods other than those involving the exposure to radiation, e.g. by stamping
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3088—Process specially adapted to improve the resolution of the mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Drying Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Preparing Plates And Mask In Photomechanical Process (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201662288846P | 2016-01-29 | 2016-01-29 | |
| PCT/US2017/015136 WO2017132381A1 (en) | 2016-01-29 | 2017-01-26 | Method and system for forming memory fin patterns |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| SG11201806451VA true SG11201806451VA (en) | 2018-08-30 |
Family
ID=59387112
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| SG11201806451VA SG11201806451VA (en) | 2016-01-29 | 2017-01-26 | Method and system for forming memory fin patterns |
Country Status (7)
| Country | Link |
|---|---|
| US (2) | US10115726B2 (ja) |
| JP (1) | JP6715415B2 (ja) |
| KR (1) | KR102207120B1 (ja) |
| CN (1) | CN108701588B (ja) |
| SG (1) | SG11201806451VA (ja) |
| TW (1) | TWI633583B (ja) |
| WO (1) | WO2017132381A1 (ja) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9991156B2 (en) * | 2016-06-03 | 2018-06-05 | International Business Machines Corporation | Self-aligned quadruple patterning (SAQP) for routing layouts including multi-track jogs |
| US10388644B2 (en) | 2016-11-29 | 2019-08-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of manufacturing conductors and semiconductor device which includes conductors |
| CN109411337A (zh) * | 2017-08-16 | 2019-03-01 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件及其形成方法 |
| US10734238B2 (en) * | 2017-11-21 | 2020-08-04 | Lam Research Corporation | Atomic layer deposition and etch in a single plasma chamber for critical dimension control |
| US10566207B2 (en) * | 2017-12-27 | 2020-02-18 | Samsung Electronics Co., Ltd. | Semiconductor manufacturing methods for patterning line patterns to have reduced length variation |
| US10439047B2 (en) * | 2018-02-14 | 2019-10-08 | Applied Materials, Inc. | Methods for etch mask and fin structure formation |
| EP3618103A1 (en) * | 2018-08-30 | 2020-03-04 | IMEC vzw | A patterning method |
| US20200090980A1 (en) * | 2018-09-13 | 2020-03-19 | Nanya Technology Corporation | Method for preparing semiconductor structures |
| US10903082B2 (en) | 2018-09-21 | 2021-01-26 | Varian Semiconductor Equipment Associates, Inc. | Spacer sculpting for forming semiconductor devices |
| US11024511B1 (en) | 2020-04-21 | 2021-06-01 | Winbond Electronics Corp. | Patterning method |
| JP2022032500A (ja) | 2020-08-12 | 2022-02-25 | キオクシア株式会社 | パターン形成方法およびテンプレートの製造方法 |
Family Cites Families (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100674970B1 (ko) * | 2005-04-21 | 2007-01-26 | 삼성전자주식회사 | 이중 스페이서들을 이용한 미세 피치의 패턴 형성 방법 |
| US7429536B2 (en) * | 2005-05-23 | 2008-09-30 | Micron Technology, Inc. | Methods for forming arrays of small, closely spaced features |
| US7914971B2 (en) * | 2005-08-12 | 2011-03-29 | Semiconductor Energy Laboratory Co., Ltd. | Light exposure mask and method for manufacturing semiconductor device using the same |
| JP4566862B2 (ja) * | 2005-08-25 | 2010-10-20 | 富士通株式会社 | レジストパターン厚肉化材料、レジストパターンの形成方法、半導体装置及びその製造方法 |
| US7759197B2 (en) * | 2005-09-01 | 2010-07-20 | Micron Technology, Inc. | Method of forming isolated features using pitch multiplication |
| US7323374B2 (en) * | 2005-09-19 | 2008-01-29 | International Business Machines Corporation | Dense chevron finFET and method of manufacturing same |
| KR100932333B1 (ko) * | 2007-11-29 | 2009-12-16 | 주식회사 하이닉스반도체 | 반도체 소자의 하드 마스크 패턴 및 그 형성 방법 |
| KR101532012B1 (ko) | 2008-12-24 | 2015-06-30 | 삼성전자주식회사 | 반도체 소자 및 반도체 소자의 패턴 형성 방법 |
| US7871873B2 (en) * | 2009-03-27 | 2011-01-18 | Global Foundries Inc. | Method of forming fin structures using a sacrificial etch stop layer on bulk semiconductor material |
| US9028123B2 (en) * | 2010-04-16 | 2015-05-12 | Flex Lighting Ii, Llc | Display illumination device with a film-based lightguide having stacked incident surfaces |
| US8575032B2 (en) * | 2011-05-05 | 2013-11-05 | Micron Technology, Inc. | Methods of forming a pattern on a substrate |
| KR20130042352A (ko) * | 2011-10-18 | 2013-04-26 | 에스케이하이닉스 주식회사 | 비휘발성 메모리 장치의 제조 방법 |
| US8647981B1 (en) * | 2012-08-31 | 2014-02-11 | Micron Technology, Inc. | Methods of forming patterns, and methods of forming integrated circuitry |
| US9287131B2 (en) * | 2014-02-21 | 2016-03-15 | Globalfoundries Inc. | Methods of patterning line-type features using a multiple patterning process that enables the use of tighter contact enclosure spacing rules |
| KR101860249B1 (ko) * | 2014-02-23 | 2018-05-21 | 도쿄엘렉트론가부시키가이샤 | 다수의 패터닝된 층을 교차시켜 패턴 밀도를 증가시키는 방법 |
| US9728406B2 (en) * | 2014-08-08 | 2017-08-08 | Applied Materials, Inc. | Multi materials and selective removal enabled reverse tone process |
| US9818611B2 (en) * | 2015-09-24 | 2017-11-14 | Tokyo Electron Limited | Methods of forming etch masks for sub-resolution substrate patterning |
| US9991156B2 (en) * | 2016-06-03 | 2018-06-05 | International Business Machines Corporation | Self-aligned quadruple patterning (SAQP) for routing layouts including multi-track jogs |
-
2017
- 2017-01-26 JP JP2018539435A patent/JP6715415B2/ja active Active
- 2017-01-26 CN CN201780014213.1A patent/CN108701588B/zh active Active
- 2017-01-26 WO PCT/US2017/015136 patent/WO2017132381A1/en active Application Filing
- 2017-01-26 SG SG11201806451VA patent/SG11201806451VA/en unknown
- 2017-01-26 US US15/416,916 patent/US10115726B2/en active Active
- 2017-01-26 KR KR1020187024383A patent/KR102207120B1/ko active IP Right Grant
- 2017-02-02 TW TW106103442A patent/TWI633583B/zh active
-
2018
- 2018-09-20 US US16/137,111 patent/US20190027481A1/en not_active Abandoned
Also Published As
| Publication number | Publication date |
|---|---|
| JP6715415B2 (ja) | 2020-07-01 |
| US10115726B2 (en) | 2018-10-30 |
| US20170221902A1 (en) | 2017-08-03 |
| CN108701588B (zh) | 2023-03-14 |
| TWI633583B (zh) | 2018-08-21 |
| JP2019508889A (ja) | 2019-03-28 |
| CN108701588A (zh) | 2018-10-23 |
| KR102207120B1 (ko) | 2021-01-22 |
| US20190027481A1 (en) | 2019-01-24 |
| TW201737309A (zh) | 2017-10-16 |
| KR20180100699A (ko) | 2018-09-11 |
| WO2017132381A1 (en) | 2017-08-03 |
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