SG11201807698SA - Bottom-up method for forming wire structures upon a substrate - Google Patents

Bottom-up method for forming wire structures upon a substrate

Info

Publication number
SG11201807698SA
SG11201807698SA SG11201807698SA SG11201807698SA SG11201807698SA SG 11201807698S A SG11201807698S A SG 11201807698SA SG 11201807698S A SG11201807698S A SG 11201807698SA SG 11201807698S A SG11201807698S A SG 11201807698SA SG 11201807698S A SG11201807698S A SG 11201807698SA
Authority
SG
Singapore
Prior art keywords
international
substrate
electrode
fluid
pct
Prior art date
Application number
SG11201807698SA
Inventor
Filip Granek
Zbigniew Rozynek
Original Assignee
Xtpl S A
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xtpl S A filed Critical Xtpl S A
Publication of SG11201807698SA publication Critical patent/SG11201807698SA/en

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Classifications

    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D13/00—Electrophoretic coating characterised by the process
    • C25D13/12—Electrophoretic coating characterised by the process characterised by the article coated
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82B—NANOSTRUCTURES FORMED BY MANIPULATION OF INDIVIDUAL ATOMS, MOLECULES, OR LIMITED COLLECTIONS OF ATOMS OR MOLECULES AS DISCRETE UNITS; MANUFACTURE OR TREATMENT THEREOF
    • B82B3/00—Manufacture or treatment of nanostructures by manipulation of individual atoms or molecules, or limited collections of atoms or molecules as discrete units
    • B82B3/0004—Apparatus specially adapted for the manufacture or treatment of nanostructural devices or systems or methods for manufacturing the same
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82B—NANOSTRUCTURES FORMED BY MANIPULATION OF INDIVIDUAL ATOMS, MOLECULES, OR LIMITED COLLECTIONS OF ATOMS OR MOLECULES AS DISCRETE UNITS; MANUFACTURE OR TREATMENT THEREOF
    • B82B3/00—Manufacture or treatment of nanostructures by manipulation of individual atoms or molecules, or limited collections of atoms or molecules as discrete units
    • B82B3/0042—Assembling discrete nanostructures into nanostructural devices
    • B82B3/0052—Aligning two or more elements
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D13/00—Electrophoretic coating characterised by the process
    • C25D13/22—Servicing or operating apparatus or multistep processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02307—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a liquid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02422—Non-crystalline insulating materials, e.g. glass, polymers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02601—Nanoparticles
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02603—Nanowires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02623—Liquid deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/326—Application of electric currents or fields, e.g. for electroforming
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67098—Apparatus for thermal treatment
    • H01L21/67115—Apparatus for thermal treatment mainly by radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H01L22/26—Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/413—Nanosized electrodes, e.g. nanowire electrodes comprising one or a plurality of nanowires
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/12—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns
    • H05K3/1283—After-treatment of the printed patterns, e.g. sintering or curing methods
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • G—PHYSICS
    • G02—OPTICS
    • G02C—SPECTACLES; SUNGLASSES OR GOGGLES INSOFAR AS THEY HAVE THE SAME FEATURES AS SPECTACLES; CONTACT LENSES
    • G02C7/00—Optical parts
    • G02C7/02—Lenses; Lens systems ; Methods of designing lenses
    • G02C7/04—Contact lenses for the eyes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1131—Sintering, i.e. fusing of metal particles to achieve or improve electrical conductivity
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/16—Inspection; Monitoring; Aligning
    • H05K2203/163—Monitoring a manufacturing process

Abstract

INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property -, Organization M1111101110101011111 HO 11111 0111011111010111110111011 MEV III 11 International Bureau .... .51 jd (10) International Publication Number ........./ (43) International Publication Date WO 2017/162696 Al 28 September 2017 (28.09.2017) WIP0 I PCT (51) International Patent Classification: (81) Designated States (unless otherwise indicated, for every H01L 29/06 (2006.01) B82B 3/00 (2006.01) kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, (21) International Application Number: BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, PCT/EP2017/056739 DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, (22) International Filing Date: HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, 21 March 2017 (21.03.2017) KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, (25) Filing Language: English NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, (26) Publication Language: English RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, (30) Priority Data: ZA, ZM, ZW. 1604818.3 22 March 2016 (22.03.2016) GB (84) Designated States (unless otherwise indicated, for every (71) Applicant: XTPL S.A. [PL/PL]; Stablowicka 147, 54-066 kind of regional protection available): ARIPO (BW, GH, Wroclaw (PL). GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, (72) Inventors: GRANEK, Filip; Tanskiego 7/9, 54-129 Wro- TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, claw (PL). ROZYNEK, Zbigniew; Prof. Sylwestra Kaliskiego 24/10, 85-796 Bydgoszcz (PL). DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, (74) Agent: GILL JENNINGS & EVERY LLP; The SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, Broadgate Tower, 20 Primrose Street, London EC2A 2ES GW, KM, ML, MR, NE, SN, TD, TG). (GB). [Continued on next page] = Title: BOTTOM-UP METHOD FOR FORMING WIRE STRUCTURES UPON A SUBSTRATE (54) (57) : A method is provided for forming = I 7 structures upon a substrate. The method com- prises: depositing fluid onto a substrate so as to define a wetted region, the fluid containing elec- trically polahzable nanoparticles; applying an al- —= 22 -----______L 18 ------ 5 5 1 ternating electric field to the fluid on the region, using a first electrode and a second electrode, so that a plurality of the nanoparticles are assembled to form an elongate structure extending from the first electrode towards the second electrode; and removing the fluid such that the elongate struc- tune remains upon the substrate. 26 = = . = = 4 20 1-1 .4 15 10 11 3 01 ei 5 ,-, IN ,-, © ei Fig. 16 O WO 2017/162696 Al MIDEDIMOMOIDERDEEMOMOHIONIECIOIRMOVOIMIE Published: — before the expiration of the time limit for amending the — with international search report (Art. 21(3)) claims and to be republished in amendments (Rule 48.2(h)) the event of receipt of
SG11201807698SA 2016-03-22 2017-03-21 Bottom-up method for forming wire structures upon a substrate SG11201807698SA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GBGB1604818.3A GB201604818D0 (en) 2016-03-22 2016-03-22 Method for forming structures upon a substrate
PCT/EP2017/056739 WO2017162696A1 (en) 2016-03-22 2017-03-21 Bottom-up method for forming wire structures upon a substrate

Publications (1)

Publication Number Publication Date
SG11201807698SA true SG11201807698SA (en) 2018-10-30

Family

ID=55968668

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201807698SA SG11201807698SA (en) 2016-03-22 2017-03-21 Bottom-up method for forming wire structures upon a substrate

Country Status (14)

Country Link
US (1) US10731268B2 (en)
EP (1) EP3433879B1 (en)
JP (1) JP7012020B2 (en)
KR (1) KR102038244B1 (en)
CN (1) CN109478558B (en)
AU (1) AU2017238313B2 (en)
CA (1) CA3018117A1 (en)
GB (1) GB201604818D0 (en)
IL (1) IL261919B2 (en)
MY (1) MY192442A (en)
PL (1) PL3433879T3 (en)
SG (1) SG11201807698SA (en)
TW (1) TW201802024A (en)
WO (1) WO2017162696A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11001687B2 (en) * 2016-08-31 2021-05-11 Konica Minolta, Inc. Substrate with functional fine line and method for forming functional fine line
GB2576293B (en) * 2018-06-06 2022-10-12 Xtpl S A Method for removing bottlenecks
GB201812691D0 (en) 2018-08-03 2018-09-19 Xtpl S A Method of forming a structure upon a substrate

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10146838A1 (en) 2001-09-24 2003-04-10 Ptr Praez Stechnik Gmbh Workpiece feeding device for an electron beam machining device
JP4281342B2 (en) 2001-12-05 2009-06-17 セイコーエプソン株式会社 Pattern forming method and wiring forming method
AU2003290531A1 (en) * 2002-10-21 2004-05-13 Nanoink, Inc. Nanometer-scale engineered structures, methods and apparatus for fabrication thereof, and applications to mask repair, enhancement, and fabrication
JP4853607B2 (en) 2004-07-09 2012-01-11 セイコーエプソン株式会社 Thin film transistor manufacturing method
US7892610B2 (en) * 2007-05-07 2011-02-22 Nanosys, Inc. Method and system for printing aligned nanowires and other electrical devices
FI122644B (en) * 2007-06-08 2012-04-30 Teknologian Tutkimuskeskus Vtt Process for forming electrically conductive or semiconducting paths on a substrate and using the method for producing transistors and producing sensors
US9061494B2 (en) * 2007-07-19 2015-06-23 The Board Of Trustees Of The University Of Illinois High resolution electrohydrodynamic jet printing for manufacturing systems
WO2010028712A1 (en) 2008-09-11 2010-03-18 ETH Zürich Capillarity-assisted, mask-less, nano-/micro-scale spray deposition of particle based functional 0d to 3d micro- and nanostructures on flat or curved substrates with or without added electrocapillarity effect
US8937293B2 (en) * 2009-10-01 2015-01-20 Northeastern University Nanoscale interconnects fabricated by electrical field directed assembly of nanoelements
US9305766B2 (en) * 2009-12-22 2016-04-05 Qunano Ab Method for manufacturing a nanowire structure
WO2011135924A1 (en) * 2010-04-27 2011-11-03 独立行政法人物質・材料研究機構 Metal nanoparticle array structure, device for producing same, and method for producing same

Also Published As

Publication number Publication date
PL3433879T3 (en) 2019-12-31
MY192442A (en) 2022-08-21
IL261919B1 (en) 2023-01-01
AU2017238313B2 (en) 2020-04-09
TW201802024A (en) 2018-01-16
JP7012020B2 (en) 2022-01-27
JP2019519089A (en) 2019-07-04
WO2017162696A1 (en) 2017-09-28
CA3018117A1 (en) 2017-09-28
US10731268B2 (en) 2020-08-04
IL261919B2 (en) 2023-05-01
CN109478558A (en) 2019-03-15
GB201604818D0 (en) 2016-05-04
US20190106804A1 (en) 2019-04-11
EP3433879A1 (en) 2019-01-30
IL261919A (en) 2018-10-31
EP3433879B1 (en) 2019-08-21
CN109478558B (en) 2020-05-05
KR102038244B1 (en) 2019-10-29
AU2017238313A1 (en) 2018-10-11
KR20180124097A (en) 2018-11-20

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