SG110691G - Data processing apparatus with selective instruction prefetching - Google Patents

Data processing apparatus with selective instruction prefetching

Info

Publication number
SG110691G
SG110691G SG1106/91A SG110691A SG110691G SG 110691 G SG110691 G SG 110691G SG 1106/91 A SG1106/91 A SG 1106/91A SG 110691 A SG110691 A SG 110691A SG 110691 G SG110691 G SG 110691G
Authority
SG
Singapore
Prior art keywords
processing apparatus
data processing
instruction prefetching
selective instruction
selective
Prior art date
Application number
SG1106/91A
Other languages
English (en)
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of SG110691G publication Critical patent/SG110691G/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0888—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Bus Control (AREA)
  • Microcomputers (AREA)
  • Debugging And Monitoring (AREA)
SG1106/91A 1988-05-26 1991-12-31 Data processing apparatus with selective instruction prefetching SG110691G (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/198,894 US5125084A (en) 1988-05-26 1988-05-26 Control of pipelined operation in a microcomputer system employing dynamic bus sizing with 80386 processor and 82385 cache controller

Publications (1)

Publication Number Publication Date
SG110691G true SG110691G (en) 1992-02-14

Family

ID=22735315

Family Applications (1)

Application Number Title Priority Date Filing Date
SG1106/91A SG110691G (en) 1988-05-26 1991-12-31 Data processing apparatus with selective instruction prefetching

Country Status (25)

Country Link
US (1) US5125084A (nl)
EP (1) EP0343988B1 (nl)
JP (1) JPH0623960B2 (nl)
KR (1) KR930002321B1 (nl)
CN (1) CN1009589B (nl)
AR (1) AR242671A1 (nl)
AT (1) ATE112869T1 (nl)
AU (1) AU615055B2 (nl)
BE (1) BE1002768A4 (nl)
BR (1) BR8902393A (nl)
CA (1) CA1313274C (nl)
DE (2) DE3914265A1 (nl)
DK (1) DK169492B1 (nl)
ES (1) ES2063818T3 (nl)
FI (1) FI95175C (nl)
FR (1) FR2632090A1 (nl)
GB (2) GB8904921D0 (nl)
HK (1) HK11492A (nl)
IT (1) IT1230207B (nl)
MX (1) MX173139B (nl)
MY (1) MY104738A (nl)
NL (1) NL8901326A (nl)
NO (1) NO174788B (nl)
SE (1) SE8901307L (nl)
SG (1) SG110691G (nl)

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GB2256296B (en) * 1991-05-31 1995-01-18 Integrated Device Tech Multiplexed status and diagnostic pins in a microprocessor with on-chip caches
US5228134A (en) * 1991-06-04 1993-07-13 Intel Corporation Cache memory integrated circuit for use with a synchronous central processor bus and an asynchronous memory bus
US5293603A (en) * 1991-06-04 1994-03-08 Intel Corporation Cache subsystem for microprocessor based computer system with synchronous and asynchronous data path
US5630163A (en) * 1991-08-09 1997-05-13 Vadem Corporation Computer having a single bus supporting multiple bus architectures operating with different bus parameters
JP2599539B2 (ja) * 1991-10-15 1997-04-09 インターナショナル・ビジネス・マシーンズ・コーポレイション 直接メモリ・アクセス装置及びルック・アヘッド装置
JP2836321B2 (ja) * 1991-11-05 1998-12-14 三菱電機株式会社 データ処理装置
US5317712A (en) * 1991-12-19 1994-05-31 Intel Corporation Method and apparatus for testing and configuring the width of portions of a memory
JPH07504773A (ja) * 1992-03-18 1995-05-25 セイコーエプソン株式会社 マルチ幅のメモリ・サブシステムをサポートするためのシステム並びに方法
US5307475A (en) * 1992-06-29 1994-04-26 The United States Of America As Represented By The Secretary Of The Navy Slave controller utilizing eight least/most significant bits for accessing sixteen bit data words
US5313593A (en) * 1992-09-17 1994-05-17 International Business Machines Corp. Personal computer system with bus noise rejection
JPH0827773B2 (ja) * 1992-10-23 1996-03-21 インターナショナル・ビジネス・マシーンズ・コーポレイション データ経路を使用可能にする方法、装置およびデータ処理システム
JP3369227B2 (ja) * 1992-11-09 2003-01-20 株式会社東芝 プロセッサ
JP3904244B2 (ja) 1993-09-17 2007-04-11 株式会社ルネサステクノロジ シングル・チップ・データ処理装置
JPH07210537A (ja) * 1993-12-10 1995-08-11 Advanced Micro Devicds Inc コンピュータシステム
US5835960A (en) * 1994-01-07 1998-11-10 Cirrus Logic, Inc. Apparatus and method for interfacing a peripheral device having a ROM BIOS to a PCI bus
US5548733A (en) * 1994-03-01 1996-08-20 Intel Corporation Method and apparatus for dynamically controlling the current maximum depth of a pipe lined computer bus system
US5784579A (en) * 1994-03-01 1998-07-21 Intel Corporation Method and apparatus for dynamically controlling bus access from a bus agent based on bus pipeline depth
US5842041A (en) * 1994-05-20 1998-11-24 Advanced Micro Devices, Inc. Computer system employing a control signal indicative of whether address is within address space of devices on processor local bus
JP3153078B2 (ja) * 1994-09-09 2001-04-03 日本電気株式会社 データ処理装置
JP2630271B2 (ja) * 1994-09-14 1997-07-16 日本電気株式会社 情報処理装置
US5890216A (en) * 1995-04-21 1999-03-30 International Business Machines Corporation Apparatus and method for decreasing the access time to non-cacheable address space in a computer system
US5758188A (en) * 1995-11-21 1998-05-26 Quantum Corporation Synchronous DMA burst transfer protocol having the peripheral device toggle the strobe signal such that data is latched using both edges of the strobe signal
US6504854B1 (en) 1998-04-10 2003-01-07 International Business Machines Corporation Multiple frequency communications
US6725348B1 (en) * 1999-10-13 2004-04-20 International Business Machines Corporation Data storage device and method for reducing write misses by completing transfer to a dual-port cache before initiating a disk write of the data from the cache
JP3857661B2 (ja) * 2003-03-13 2006-12-13 インターナショナル・ビジネス・マシーンズ・コーポレーション 情報処理装置、プログラム、及び記録媒体
US7366864B2 (en) * 2004-03-08 2008-04-29 Micron Technology, Inc. Memory hub architecture having programmable lane widths
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CN113514408B (zh) * 2021-06-28 2024-06-11 杭州谱育科技发展有限公司 具有校正功能的臭氧检测装置及方法

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US4257095A (en) * 1978-06-30 1981-03-17 Intel Corporation System bus arbitration, circuitry and methodology
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US4503534A (en) * 1982-06-30 1985-03-05 Intel Corporation Apparatus for redundant operation of modules in a multiprocessing system
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JPS6240555A (ja) * 1985-08-16 1987-02-21 Fujitsu Ltd プリフエツチ制御方式
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Also Published As

Publication number Publication date
AU615055B2 (en) 1991-09-19
AU3409989A (en) 1989-11-30
KR890017604A (ko) 1989-12-16
BE1002768A4 (fr) 1991-06-04
EP0343988A2 (en) 1989-11-29
HK11492A (en) 1992-02-21
IT8920648A0 (it) 1989-05-25
FI95175B (fi) 1995-09-15
ES2063818T3 (es) 1995-01-16
DE3914265C2 (nl) 1992-01-09
CN1037976A (zh) 1989-12-13
DK169492B1 (da) 1994-11-07
DK189489D0 (da) 1989-04-19
KR930002321B1 (ko) 1993-03-29
JPH02146645A (ja) 1990-06-05
MX173139B (es) 1994-02-02
AR242671A1 (es) 1993-04-30
SE8901307L (sv) 1989-11-27
GB2219110B (en) 1991-02-20
EP0343988A3 (en) 1991-01-30
EP0343988B1 (en) 1994-10-12
BR8902393A (pt) 1990-01-16
NO891584D0 (no) 1989-04-18
GB8904921D0 (en) 1989-04-12
NO891584L (no) 1989-11-27
NO174788C (nl) 1994-07-13
JPH0623960B2 (ja) 1994-03-30
NL8901326A (nl) 1989-12-18
IT1230207B (it) 1991-10-18
CN1009589B (zh) 1990-09-12
GB8912018D0 (en) 1989-07-12
CA1313274C (en) 1993-01-26
DE68918754D1 (de) 1994-11-17
FR2632090A1 (fr) 1989-12-01
MY104738A (en) 1994-05-31
SE8901307D0 (sv) 1989-04-11
DK189489A (da) 1989-11-27
GB2219110A (en) 1989-11-29
NO174788B (no) 1994-03-28
ATE112869T1 (de) 1994-10-15
FI891787A (fi) 1989-11-27
FI891787A0 (fi) 1989-04-14
FI95175C (fi) 1995-12-27
US5125084A (en) 1992-06-23
DE68918754T2 (de) 1995-04-27
DE3914265A1 (de) 1989-11-30

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