MX173139B - Sistema de microcomputadora con una señal de instruccion entubada - Google Patents

Sistema de microcomputadora con una señal de instruccion entubada

Info

Publication number
MX173139B
MX173139B MX016142A MX1614289A MX173139B MX 173139 B MX173139 B MX 173139B MX 016142 A MX016142 A MX 016142A MX 1614289 A MX1614289 A MX 1614289A MX 173139 B MX173139 B MX 173139B
Authority
MX
Mexico
Prior art keywords
address
bit width
piped
range associated
responds
Prior art date
Application number
MX016142A
Other languages
English (en)
Inventor
Ralph Murray Begun
Patrick Maurice Bland
Mark Edward Dean
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of MX173139B publication Critical patent/MX173139B/es

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0888—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Bus Control (AREA)
  • Microcomputers (AREA)
  • Debugging And Monitoring (AREA)

Abstract

La presente invención se refiere a un sistema de microcomputadora con una señal de instrucción entubada que responde a una señal de la siguiente dirección, antes de completarse una operación pendiente; caracterizado porque comprende: un procesador de un ancho de bits dado; un subsistema de memoria de reserva del ancho de bits dado y acoplado al procesador por un bus lucal; un bus adicional que conecta al bus local con otros componentes que tienen el ancho de bits dado y con por lo menos un componente de un ancho de bits reducido, en donde por lo menos algunos de los componentes tienen un ancho de bits dado con una dirección en un margen de dirección asociado con el subsistema de reserva y teniendo por lo menos un componente de un ancho de bits reducido, una dirección fuera de un margen de dirección asociada con el subsistema de reserva; comprendiendo adicionalmente: un elemento decodificador de dirección que responde a una dirección aseverada en el bus local para generar una señal que indica si la dirección aseverada está o no dentro del margen de dirección asociado con el subsistema de memoria de reserva; y un elemento lógico que responde al elemento decodificador de dirección, para generar una señal de la siguiente dirección, para la operación entubada, a menos que el elemento decodificador de dirección indique una dirección aseverada fuera de un margen asociado con el subsistema de reserva.
MX016142A 1988-05-26 1989-05-22 Sistema de microcomputadora con una señal de instruccion entubada MX173139B (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/198,894 US5125084A (en) 1988-05-26 1988-05-26 Control of pipelined operation in a microcomputer system employing dynamic bus sizing with 80386 processor and 82385 cache controller

Publications (1)

Publication Number Publication Date
MX173139B true MX173139B (es) 1994-02-02

Family

ID=22735315

Family Applications (1)

Application Number Title Priority Date Filing Date
MX016142A MX173139B (es) 1988-05-26 1989-05-22 Sistema de microcomputadora con una señal de instruccion entubada

Country Status (25)

Country Link
US (1) US5125084A (es)
EP (1) EP0343988B1 (es)
JP (1) JPH0623960B2 (es)
KR (1) KR930002321B1 (es)
CN (1) CN1009589B (es)
AR (1) AR242671A1 (es)
AT (1) ATE112869T1 (es)
AU (1) AU615055B2 (es)
BE (1) BE1002768A4 (es)
BR (1) BR8902393A (es)
CA (1) CA1313274C (es)
DE (2) DE3914265A1 (es)
DK (1) DK169492B1 (es)
ES (1) ES2063818T3 (es)
FI (1) FI95175C (es)
FR (1) FR2632090A1 (es)
GB (2) GB8904921D0 (es)
HK (1) HK11492A (es)
IT (1) IT1230207B (es)
MX (1) MX173139B (es)
MY (1) MY104738A (es)
NL (1) NL8901326A (es)
NO (1) NO174788B (es)
SE (1) SE8901307L (es)
SG (1) SG110691G (es)

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JPH0827773B2 (ja) * 1992-10-23 1996-03-21 インターナショナル・ビジネス・マシーンズ・コーポレイション データ経路を使用可能にする方法、装置およびデータ処理システム
JP3369227B2 (ja) * 1992-11-09 2003-01-20 株式会社東芝 プロセッサ
JP3904244B2 (ja) 1993-09-17 2007-04-11 株式会社ルネサステクノロジ シングル・チップ・データ処理装置
JPH07210537A (ja) * 1993-12-10 1995-08-11 Advanced Micro Devicds Inc コンピュータシステム
US5835960A (en) * 1994-01-07 1998-11-10 Cirrus Logic, Inc. Apparatus and method for interfacing a peripheral device having a ROM BIOS to a PCI bus
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US5784579A (en) * 1994-03-01 1998-07-21 Intel Corporation Method and apparatus for dynamically controlling bus access from a bus agent based on bus pipeline depth
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JP3153078B2 (ja) * 1994-09-09 2001-04-03 日本電気株式会社 データ処理装置
JP2630271B2 (ja) * 1994-09-14 1997-07-16 日本電気株式会社 情報処理装置
US5890216A (en) * 1995-04-21 1999-03-30 International Business Machines Corporation Apparatus and method for decreasing the access time to non-cacheable address space in a computer system
US5758188A (en) * 1995-11-21 1998-05-26 Quantum Corporation Synchronous DMA burst transfer protocol having the peripheral device toggle the strobe signal such that data is latched using both edges of the strobe signal
US6504854B1 (en) 1998-04-10 2003-01-07 International Business Machines Corporation Multiple frequency communications
US6725348B1 (en) * 1999-10-13 2004-04-20 International Business Machines Corporation Data storage device and method for reducing write misses by completing transfer to a dual-port cache before initiating a disk write of the data from the cache
JP3857661B2 (ja) * 2003-03-13 2006-12-13 インターナショナル・ビジネス・マシーンズ・コーポレーション 情報処理装置、プログラム、及び記録媒体
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Also Published As

Publication number Publication date
AU615055B2 (en) 1991-09-19
AU3409989A (en) 1989-11-30
KR890017604A (ko) 1989-12-16
BE1002768A4 (fr) 1991-06-04
EP0343988A2 (en) 1989-11-29
HK11492A (en) 1992-02-21
IT8920648A0 (it) 1989-05-25
FI95175B (fi) 1995-09-15
ES2063818T3 (es) 1995-01-16
DE3914265C2 (es) 1992-01-09
CN1037976A (zh) 1989-12-13
DK169492B1 (da) 1994-11-07
DK189489D0 (da) 1989-04-19
KR930002321B1 (ko) 1993-03-29
JPH02146645A (ja) 1990-06-05
AR242671A1 (es) 1993-04-30
SE8901307L (sv) 1989-11-27
GB2219110B (en) 1991-02-20
EP0343988A3 (en) 1991-01-30
EP0343988B1 (en) 1994-10-12
BR8902393A (pt) 1990-01-16
NO891584D0 (no) 1989-04-18
GB8904921D0 (en) 1989-04-12
NO891584L (no) 1989-11-27
NO174788C (es) 1994-07-13
JPH0623960B2 (ja) 1994-03-30
NL8901326A (nl) 1989-12-18
IT1230207B (it) 1991-10-18
CN1009589B (zh) 1990-09-12
GB8912018D0 (en) 1989-07-12
CA1313274C (en) 1993-01-26
DE68918754D1 (de) 1994-11-17
FR2632090A1 (fr) 1989-12-01
SG110691G (en) 1992-02-14
MY104738A (en) 1994-05-31
SE8901307D0 (sv) 1989-04-11
DK189489A (da) 1989-11-27
GB2219110A (en) 1989-11-29
NO174788B (no) 1994-03-28
ATE112869T1 (de) 1994-10-15
FI891787A (fi) 1989-11-27
FI891787A0 (fi) 1989-04-14
FI95175C (fi) 1995-12-27
US5125084A (en) 1992-06-23
DE68918754T2 (de) 1995-04-27
DE3914265A1 (de) 1989-11-30

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