SG10201808373QA - Wafer dicing method - Google Patents

Wafer dicing method

Info

Publication number
SG10201808373QA
SG10201808373QA SG10201808373QA SG10201808373QA SG10201808373QA SG 10201808373Q A SG10201808373Q A SG 10201808373QA SG 10201808373Q A SG10201808373Q A SG 10201808373QA SG 10201808373Q A SG10201808373Q A SG 10201808373QA SG 10201808373Q A SG10201808373Q A SG 10201808373QA
Authority
SG
Singapore
Prior art keywords
dies
wafer
metal layer
dicing method
procedure
Prior art date
Application number
SG10201808373QA
Other languages
English (en)
Inventor
Tu Chia-Jung
Chen Chih-Lung
Liao Wen-Hsiang
Wei Chung-Hsiang
Liu Yung-Chi
Original Assignee
Chipbond Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chipbond Technology Corp filed Critical Chipbond Technology Corp
Publication of SG10201808373QA publication Critical patent/SG10201808373QA/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67028—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like
    • H01L21/6704—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like for wet cleaning or washing
    • H01L21/67046—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like for wet cleaning or washing using mainly scrubbing means, e.g. brushes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
    • H01L2021/60022—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process using bump connectors, e.g. for flip chip mounting
    • H01L2021/60097—Applying energy, e.g. for the soldering or alloying process
    • H01L2021/60172—Applying energy, e.g. for the soldering or alloying process using static pressure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Dicing (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
SG10201808373QA 2016-09-23 2016-11-18 Wafer dicing method SG10201808373QA (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW105130694A TW201812887A (zh) 2016-09-23 2016-09-23 晶圓切割方法

Publications (1)

Publication Number Publication Date
SG10201808373QA true SG10201808373QA (en) 2018-10-30

Family

ID=61629247

Family Applications (2)

Application Number Title Priority Date Filing Date
SG10201609698PA SG10201609698PA (en) 2016-09-23 2016-11-18 Wafer dicing method
SG10201808373QA SG10201808373QA (en) 2016-09-23 2016-11-18 Wafer dicing method

Family Applications Before (1)

Application Number Title Priority Date Filing Date
SG10201609698PA SG10201609698PA (en) 2016-09-23 2016-11-18 Wafer dicing method

Country Status (6)

Country Link
US (1) US9929051B1 (zh)
JP (1) JP2018050020A (zh)
KR (1) KR101847948B1 (zh)
CN (1) CN107871707A (zh)
SG (2) SG10201609698PA (zh)
TW (1) TW201812887A (zh)

Family Cites Families (37)

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US3735483A (en) * 1970-03-20 1973-05-29 Gen Electric Semiconductor passivating process
JPS61181615A (ja) 1985-02-07 1986-08-14 三菱電機株式会社 半導体ウエ−ハ切断装置
JPH02155611A (ja) 1988-12-07 1990-06-14 Mitsubishi Electric Corp ダイシング装置
JP2680453B2 (ja) * 1989-12-11 1997-11-19 株式会社東京精密 ダイシング方法
US6165813A (en) * 1995-04-03 2000-12-26 Xerox Corporation Replacing semiconductor chips in a full-width chip array
JP3496347B2 (ja) * 1995-07-13 2004-02-09 株式会社デンソー 半導体装置及びその製造方法
JP2000173952A (ja) * 1998-12-03 2000-06-23 Fujitsu Quantum Device Kk 半導体装置及びその製造方法
JP2001326193A (ja) 2000-05-15 2001-11-22 Sony Corp ダイシング装置および方法
US6423565B1 (en) * 2000-05-30 2002-07-23 Kurt L. Barth Apparatus and processes for the massproduction of photovotaic modules
JP2002043474A (ja) * 2000-07-21 2002-02-08 Nakamura Seisakusho Kk 電子部品用パッケージの形成方法
WO2002074686A2 (en) * 2000-12-05 2002-09-26 Analog Devices, Inc. A method and device for protecting micro electromechanical systems structures during dicing of a wafer
JP2002224929A (ja) * 2001-01-30 2002-08-13 Takemoto Denki Seisakusho:Kk 板状被加工物の切削装置
JP2003133256A (ja) 2001-10-23 2003-05-09 Sharp Corp ダイシング装置
JP2003209089A (ja) 2002-01-17 2003-07-25 Sony Corp ウェハの洗浄方法、洗浄装置およびダイシング装置
CN100477139C (zh) * 2002-12-27 2009-04-08 富士通株式会社 凸块形成方法、半导体器件及其制造方法、基板处理装置和半导体制造装置
JP3945415B2 (ja) * 2003-02-14 2007-07-18 セイコーエプソン株式会社 半導体装置の製造方法
JP2005142399A (ja) 2003-11-07 2005-06-02 Tokyo Seimitsu Co Ltd ダイシング方法
JP2005191332A (ja) * 2003-12-26 2005-07-14 Matsushita Electric Ind Co Ltd 半導体装置の製造方法および半導体装置製造装置
US6974726B2 (en) * 2003-12-30 2005-12-13 Intel Corporation Silicon wafer with soluble protective coating
KR100630698B1 (ko) * 2004-08-17 2006-10-02 삼성전자주식회사 솔더볼 접착 신뢰도를 높이는 반도체 패키지 및 그 제조방법
JP2007125667A (ja) * 2005-11-07 2007-05-24 Disco Abrasive Syst Ltd 基板の切断装置
JP4777072B2 (ja) 2006-01-11 2011-09-21 株式会社東京精密 ダイシング装置
KR20090024408A (ko) 2007-09-04 2009-03-09 삼성전자주식회사 스크라이브 래인 내의 금속 버를 제거하는 노즐을 갖는웨이퍼 소잉 장치, 웨이퍼 소잉 방법 및 이를 이용하여제작된 반도체 패키지
US7951688B2 (en) * 2007-10-01 2011-05-31 Fairchild Semiconductor Corporation Method and structure for dividing a substrate into individual devices
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GB2464549B (en) * 2008-10-22 2013-03-27 Cambridge Silicon Radio Ltd Improved wafer level chip scale packaging
US9548240B2 (en) * 2010-03-15 2017-01-17 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming repassivation layer for robust low cost fan-out semiconductor package
DE102010040062B4 (de) * 2010-08-31 2014-05-22 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Eine Substratzerteilungstechnik für das Separieren von Halbleiterchips mit geringerem Flächenverbrauch
US8365398B2 (en) * 2011-01-26 2013-02-05 Jeng-Jye Shau Accurate alignment for stacked substrates
DE102012111358A1 (de) * 2012-11-23 2014-05-28 Osram Opto Semiconductors Gmbh Verfahren zum Vereinzeln eines Verbundes in Halbleiterchips und Halbleiterchip
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JP2015220240A (ja) 2014-05-14 2015-12-07 株式会社ディスコ ウェーハの加工方法
JP6338478B2 (ja) 2014-07-18 2018-06-06 Ｔｏｗａ株式会社 切断方法及び製品の製造方法
JP5976055B2 (ja) 2014-08-21 2016-08-23 力晶科技股▲ふん▼有限公司 半導体ウエハ、半導体チップ及び半導体装置とそれらの製造方法
JP2016134433A (ja) 2015-01-16 2016-07-25 株式会社東芝 ダイシング装置
KR20160057966A (ko) * 2014-11-14 2016-05-24 가부시끼가이샤 도시바 처리 장치, 노즐 및 다이싱 장치

Also Published As

Publication number Publication date
JP2018050020A (ja) 2018-03-29
SG10201609698PA (en) 2018-04-27
KR20180033028A (ko) 2018-04-02
TW201812887A (zh) 2018-04-01
CN107871707A (zh) 2018-04-03
US9929051B1 (en) 2018-03-27
US20180090379A1 (en) 2018-03-29
KR101847948B1 (ko) 2018-04-11

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