US20180090379A1 - Wafer dicing method - Google Patents

Wafer dicing method Download PDF

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Publication number
US20180090379A1
US20180090379A1 US15/342,241 US201615342241A US2018090379A1 US 20180090379 A1 US20180090379 A1 US 20180090379A1 US 201615342241 A US201615342241 A US 201615342241A US 2018090379 A1 US2018090379 A1 US 2018090379A1
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Prior art keywords
wafer
cutting
contacting
cutter
dies
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US15/342,241
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US9929051B1 (en
Inventor
Chia-Jung Tu
Chih-Lung Chen
Wen-Hsiang Liao
Chung-Hsiang Wei
Yung-Chi Liu
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Chipbond Technology Corp
Intel Corp
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Chipbond Technology Corp
Intel Corp
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Assigned to CHIPBOND TECHNOLOGY CORPORATION reassignment CHIPBOND TECHNOLOGY CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHEN, CHIH-LUNG, LIAO, WEN-HSIANG, LIU, YUNG-CHI, TU, CHIA-JUNG, WEI, CHUNG-HSIANG
Assigned to INTEL CORPORATION reassignment INTEL CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ALPERT, YARON, MOSHE, MOSHE
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Publication of US9929051B1 publication Critical patent/US9929051B1/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304Mechanical treatment, e.g. grinding, polishing, cutting
    • H01L21/3043Making grooves, e.g. cutting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67017Apparatus for fluid treatment
    • H01L21/67028Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like
    • H01L21/6704Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like for wet cleaning or washing
    • H01L21/67046Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like for wet cleaning or washing using mainly scrubbing means, e.g. brushes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/544Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H01L2021/60007Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
    • H01L2021/60022Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process using bump connectors, e.g. for flip chip mounting
    • H01L2021/60097Applying energy, e.g. for the soldering or alloying process
    • H01L2021/60172Applying energy, e.g. for the soldering or alloying process using static pressure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544Marks applied to semiconductor devices or parts
    • H01L2223/54453Marks applied to semiconductor devices or parts for use prior to dicing
    • H01L2223/5446Located in scribe lines
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto

Definitions

  • This invention generally relates to a wafer dicing method, more particularly to a wafer dicing method able to prevent metal burrs from protruding on die surface.
  • a wafer 400 is firstly fixed on a carrier 600 by a tape 500 in conventional wafer dicing method, and then using a cutter (not shown) to cut the wafer 400 to form a plurality of chips 410 .
  • a plurality of metal burrs 411 will be formed protruded from the surface of the chip 410 during cutting.
  • FIG. 12 when the chip 410 interconnects with a plurality of bumps 710 on a substrate 700 which is made of flexible material, glass or other materials by flip-chip technology, the metal burrs 411 protruded from the surface of the chip 410 will contact with the substrate 700 to cause leakage or short circuit of semiconductor structure, or affect electric signal input or output.
  • the primary object of the present invention is to use a brush to contact with metal burrs formed result from cutting metal layer to prevent the metal burrs from protruding on die surface.
  • a wafer dicing method of the present invention comprises providing a wafer including a plurality of dies and a metal layer, wherein each of the dies includes a surface and there is a scribe line formed between adjacent dies, and wherein the metal layer is formed on the scribe line; and performing a cutting procedure and a contacting procedure, wherein a cutter is used to cut the metal layer along the scribe line during the cutting procedure to form a plurality of cutting slots on the wafer, and the metal layer cut by the cutter remains a plurality of metal burrs on the dies, and wherein a contacting portion of a brush is used to contact with each of the metal burrs along the cutting slot during the contacting procedure to prevent each of the metal burrs from protruding from the surface of each of the dies.
  • the present invention uses the brush to contact with the metal burrs during the contacting procedure for preventing the metal burrs formed during the cutting procedure from protruding on the surface of the die.
  • the purpose of preventing the metal burrs from protruding on the die surface is to prevent the metal burrs from contacting with other components during follow-up package process to cause leakage/short circuit or affect electric signal transmission, and also prevent the metal burrs from damaging other components during follow-up package process.
  • FIG. 1 is a flow chart illustrating a wafer dicing method in accordance with a first embodiment of the present invention.
  • FIG. 2 is a perspective diagram illustrating a wafer and a wafer dicing device in accordance with the first embodiment of the present invention.
  • FIG. 3 is a lateral view diagram illustrating the wafer and the wafer dicing device in accordance with the first embodiment of the present invention.
  • FIG. 4 is a lateral view diagram illustrating the wafer and the wafer dicing device in accordance with the first embodiment of the present invention.
  • FIG. 5 is a lateral view diagram illustrating the wafer and the wafer dicing device in accordance with the first embodiment of the present invention.
  • FIG. 6 is a cross-sectional view diagram along A-A line in FIG. 5 .
  • FIG. 7 is a cross-sectional view diagram along B-B line in FIG. 5 .
  • FIG. 8 is a cross-sectional view diagram along C-C line in FIG. 5 .
  • FIG. 9 is a lateral view diagram illustrating a wafer and a wafer dicing device in accordance with a second embodiment of the present invention.
  • FIG. 10 is a lateral view diagram illustrating the wafer and the wafer dicing device in accordance with the second embodiment of the present invention.
  • FIG. 11 is a diagram illustrating a wafer after cutting.
  • FIG. 12 is a diagram illustrating a chip after flip-chip interconnection.
  • a wafer dicing method 10 in accordance with a first embodiment of the present invention includes step 11 of providing wafer and step 12 of performing cutting procedure and contacting procedure.
  • a wafer 100 is provided in step 11 , preferably, the wafer 100 is made of silicon (Si) or group III-V compound semiconductor materials (e.g. GaAs).
  • the wafer 100 includes a plurality of dies 110 arranged in array and a metal layer 120 , wherein each of the dies 110 includes a surface 111 which can be the active or inactive surface of the die 110 .
  • There is a scribe line 130 formed between adjacent dies 110 and the metal layer 120 is formed on the scribe line 130 , wherein the metal layer 120 can electrically connect to the dies 110 for electric test, or the metal layer 120 can be used for cutter aligning in cutting procedure.
  • the wafer 100 is cut by a wafer dicing device 200 in the present invention, wherein the wafer dicing device 200 includes a carrier 210 , a cutter 210 and a brush 230 .
  • the cutter 220 and the brush 230 are located above the carrier 210 and faced toward the surface 111 of each of the dies 110 .
  • the wafer 100 is placed on a bearing surface 211 of the carrier 210 , and the carrier 210 is used to carry the wafer 100 for movement relative to the cutter 220 and the brush 230 in this embodiment, wherein the movement includes horizontal and vertical movement.
  • the cutter 220 and the brush 230 can be moved relative to the wafer 100 , wherein the movement also includes horizontal and vertical movement.
  • the cutter 220 is a cutting wheel, and a contacting portion 231 of the brush 230 is made of flexible material so that the wafer 100 will not be damaged.
  • the contacting portion 231 of the brush 230 can be selected from artificial filament, animal filament or plant filament.
  • the contacting portion 231 of the brush 230 is DuPont 612 nylon filament.
  • fixing tape 300 between the wafer 100 and the carrier 210 , wherein the fixing tape 300 is used to fix the wafer 100 for preventing the wafer 100 from moving during cutting.
  • the cutter 220 includes a terminal 221
  • the contacting portion 231 of the brush 230 includes a contacting end 231 a , wherein the terminal 221 of the cutter 220 and the contacting end 231 a of the contacting portion 231 both face toward the bearing surface 211 of the carrier 210 .
  • a first height H 1 is defined between the terminal 221 of the cutter 220 and the bearing surface 211
  • a second height H 2 is defined between the contacting end 231 a of the contacting portion 231 and the bearing surface 211
  • the first height H 1 is equal to or higher than the second height H 2 before step 12 of performing cutting procedure and contacting procedure so that the contacting portion 231 of the brush 230 cannot contact with the wafer 100 is preventable when the carrier 210 is moved upwardly to make the cutter 220 contacting with the wafer 100 .
  • the first height H 1 is higher than the second height H 2 .
  • a cutting procedure and a contacting procedure are performed in step 12 .
  • the cutter 220 is used to cut the metal layer 120 along the scribe line 130 to form a plurality of cutting slots 140 on the wafer 110 , wherein the dies 110 located at both sides of the cutting slot 140 are electrically disconnected with each other.
  • the wafer 100 is moved upwardly by the carrier 210 to contact with the cutter 220 in this embodiment, and then the wafer 100 is horizontally moved relative to the cutter 220 by the carrier 210 to cut the metal layer 120 along the scribe line 130 for forming the cutting slot 140 .
  • the contacting portion 231 of the brush 230 following the cutter 220 contacts with the surface 111 of the die 110 and at least one cutting slot 140 when the cutter 220 cuts the metal layer 120 along the scribe line 130 .
  • FIG. 6 is a cross-sectional view diagram along A-A line in FIG. 5 .
  • the metal layer 120 will remain a plurality of metal burrs 121 on the dies 110 when the cutter 220 cuts the metal layer 120 along the scribe line 130 , and the metal burrs 121 will protrude from the surface 111 of each of the dies 110 because of cutting stress.
  • FIG. 7 is a cross-sectional view diagram along B-B line in FIG. 5 .
  • the contacting portion 231 of the brush 230 can touch the surface 111 of each of the dies 110 and the cutting slot 140 along the cutting slot 140 , and contact with each of the metal burrs 121 , wherein deformation of the contacting portion 231 will occur during the contacting procedure because the contacting portion 231 is made of flexible material.
  • FIG. 8 is a cross-sectional view diagram along C-C line in FIG. 5 .
  • the contacting procedure can prevent the metal burrs 121 from protruding on the surface 111 of each of the dies 110 .
  • each of the metal burrs 121 will be divided from the dies 110 or bent downwardly toward the cutting slot 140 by horizontal push force or vertical press force from the contacting portion 231 of the brush 230 , so the problem that the metal burrs 121 protrude from the surface 111 of each of the dies 110 can be effectively solved.
  • the contacting procedure can prevent the metal burrs 121 from electrically connecting with other elements in the follow-up package processes to cause leakage or short circuit, and can prevent the metal burrs 121 from affecting electric signal input or output, or damaging other elements to affect semiconductor efficacy.
  • the cutting procedure and the contacting procedure are performed simultaneously in this embodiment, so the wafer 100 can be cleaned by air or water curtain to remove wafer fragment formed during the cutting procedure and the metal burrs 121 divided during the contacting procedure for preventing the wafer fragment or the metal burrs 121 from remaining on the wafer 100 .
  • the contacting portion 231 of the brush 230 is placed behind the cutter 220 along with the cutting direction of the cutter 220 , and the cutter 220 and the contacting portion 231 of the brush 230 are located on the same scribe line 130 .
  • the contacting portion 231 of the brush 230 can immediately contact with the metal burrs 121 along the cutting slot 140 formed newly to divide the metal burrs 121 from the dies 110 or bend the metal burrs 121 downwardly toward the cutting slot 140 when the cutter 220 cuts the metal layer 120 along the scribe line 130 to form the cutting slot 140 , to prevent the metal burrs 121 from protruding from the surface 111 of the die 110 .
  • the contacting procedure can be performed after completing the cutting procedure. That means the contacting portion 231 of the brush 230 contacts with the metal burrs 121 along each of the cutting slots 140 to divide the metal burrs 121 from the die 110 or bend the metal burrs 121 downwardly toward the cutting slot 140 after the cutter 220 cuts the wafer 100 to make all the dies 110 electrically disconnecting with each other.
  • FIGS. 9 and 10 Second embodiment of the present invention is illustrated in FIGS. 9 and 10 , the difference between the second embodiment and the first embodiment is the contacting portion 231 of the brush 230 is placed on the side of the cutter 220 along with the cutting direction of the cutter 220 , and the cutter 220 and the contacting portion 231 of the brush 230 are located on the different scribe lines 130 .
  • the brush 230 located on the side of the cutter 220 can contact with the metal burrs 121 along the cutting slot 140 formed previously to divide the metal burrs 121 from the die 110 or bend the metal burrs 121 downwardly toward the cutting slot 140 when the cutter 220 cuts the wafer 100 to form new cutting slot 140 .
  • the contacting portion 231 of the brush 230 is separated from the cutter 220 by at least one scribe line 130 preferably to prevent interference between the contacting portion 231 of the brush 230 and the cutter 220 .

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Dicing (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

A wafer dicing method comprises providing a wafer and performing a cutting procedure and a contacting procedure. The wafer includes a plurality of dies and a metal layer, wherein the metal layer is formed on a scribe line which is formed between adjacent dies. A cutter is used to cut the metal layer along the scribe line during the cutting procedure to form a plurality of dies on the wafer, and the metal layer cut by the cutter remains a plurality of metal burrs on the dies. A brush is used to contact with the metal burrs along the cutting slot during the contracting procedure to prevent each of the metal burrs from protruding from a surface of each of the dies.

Description

    FIELD OF THE INVENTION
  • This invention generally relates to a wafer dicing method, more particularly to a wafer dicing method able to prevent metal burrs from protruding on die surface.
  • BACKGROUND OF THE INVENTION
  • With reference to FIG. 11, a wafer 400 is firstly fixed on a carrier 600 by a tape 500 in conventional wafer dicing method, and then using a cutter (not shown) to cut the wafer 400 to form a plurality of chips 410. However, a plurality of metal burrs 411 will be formed protruded from the surface of the chip 410 during cutting. With reference to FIG. 12, when the chip 410 interconnects with a plurality of bumps 710 on a substrate 700 which is made of flexible material, glass or other materials by flip-chip technology, the metal burrs 411 protruded from the surface of the chip 410 will contact with the substrate 700 to cause leakage or short circuit of semiconductor structure, or affect electric signal input or output.
  • SUMMARY
  • The primary object of the present invention is to use a brush to contact with metal burrs formed result from cutting metal layer to prevent the metal burrs from protruding on die surface.
  • A wafer dicing method of the present invention comprises providing a wafer including a plurality of dies and a metal layer, wherein each of the dies includes a surface and there is a scribe line formed between adjacent dies, and wherein the metal layer is formed on the scribe line; and performing a cutting procedure and a contacting procedure, wherein a cutter is used to cut the metal layer along the scribe line during the cutting procedure to form a plurality of cutting slots on the wafer, and the metal layer cut by the cutter remains a plurality of metal burrs on the dies, and wherein a contacting portion of a brush is used to contact with each of the metal burrs along the cutting slot during the contacting procedure to prevent each of the metal burrs from protruding from the surface of each of the dies.
  • The present invention uses the brush to contact with the metal burrs during the contacting procedure for preventing the metal burrs formed during the cutting procedure from protruding on the surface of the die. The purpose of preventing the metal burrs from protruding on the die surface is to prevent the metal burrs from contacting with other components during follow-up package process to cause leakage/short circuit or affect electric signal transmission, and also prevent the metal burrs from damaging other components during follow-up package process.
  • DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a flow chart illustrating a wafer dicing method in accordance with a first embodiment of the present invention.
  • FIG. 2 is a perspective diagram illustrating a wafer and a wafer dicing device in accordance with the first embodiment of the present invention.
  • FIG. 3 is a lateral view diagram illustrating the wafer and the wafer dicing device in accordance with the first embodiment of the present invention.
  • FIG. 4 is a lateral view diagram illustrating the wafer and the wafer dicing device in accordance with the first embodiment of the present invention.
  • FIG. 5 is a lateral view diagram illustrating the wafer and the wafer dicing device in accordance with the first embodiment of the present invention.
  • FIG. 6 is a cross-sectional view diagram along A-A line in FIG. 5.
  • FIG. 7 is a cross-sectional view diagram along B-B line in FIG. 5.
  • FIG. 8 is a cross-sectional view diagram along C-C line in FIG. 5.
  • FIG. 9 is a lateral view diagram illustrating a wafer and a wafer dicing device in accordance with a second embodiment of the present invention.
  • FIG. 10 is a lateral view diagram illustrating the wafer and the wafer dicing device in accordance with the second embodiment of the present invention.
  • FIG. 11 is a diagram illustrating a wafer after cutting.
  • FIG. 12 is a diagram illustrating a chip after flip-chip interconnection.
  • DETAILED DESCRIPTION OF THE INVENTION
  • With reference to FIG. 1, a wafer dicing method 10 in accordance with a first embodiment of the present invention includes step 11 of providing wafer and step 12 of performing cutting procedure and contacting procedure.
  • With reference to FIGS. 1, 2 and 3, a wafer 100 is provided in step 11, preferably, the wafer 100 is made of silicon (Si) or group III-V compound semiconductor materials (e.g. GaAs). The wafer 100 includes a plurality of dies 110 arranged in array and a metal layer 120, wherein each of the dies 110 includes a surface 111 which can be the active or inactive surface of the die 110. There is a scribe line 130 formed between adjacent dies 110, and the metal layer 120 is formed on the scribe line 130, wherein the metal layer 120 can electrically connect to the dies 110 for electric test, or the metal layer 120 can be used for cutter aligning in cutting procedure.
  • With reference to FIGS. 2 and 3, the wafer 100 is cut by a wafer dicing device 200 in the present invention, wherein the wafer dicing device 200 includes a carrier 210, a cutter 210 and a brush 230. The cutter 220 and the brush 230 are located above the carrier 210 and faced toward the surface 111 of each of the dies 110. The wafer 100 is placed on a bearing surface 211 of the carrier 210, and the carrier 210 is used to carry the wafer 100 for movement relative to the cutter 220 and the brush 230 in this embodiment, wherein the movement includes horizontal and vertical movement. In other embodiment, the cutter 220 and the brush 230 can be moved relative to the wafer 100, wherein the movement also includes horizontal and vertical movement. Preferably, the cutter 220 is a cutting wheel, and a contacting portion 231 of the brush 230 is made of flexible material so that the wafer 100 will not be damaged. The contacting portion 231 of the brush 230 can be selected from artificial filament, animal filament or plant filament. In this embodiment, the contacting portion 231 of the brush 230 is DuPont 612 nylon filament.
  • With reference to FIGS. 2 and 3, there is a fixing tape 300 between the wafer 100 and the carrier 210, wherein the fixing tape 300 is used to fix the wafer 100 for preventing the wafer 100 from moving during cutting.
  • With reference to FIG. 3, the cutter 220 includes a terminal 221, and the contacting portion 231 of the brush 230 includes a contacting end 231 a, wherein the terminal 221 of the cutter 220 and the contacting end 231 a of the contacting portion 231 both face toward the bearing surface 211 of the carrier 210. A first height H1 is defined between the terminal 221 of the cutter 220 and the bearing surface 211, and a second height H2 is defined between the contacting end 231 a of the contacting portion 231 and the bearing surface 211, wherein the first height H1 is equal to or higher than the second height H2 before step 12 of performing cutting procedure and contacting procedure so that the contacting portion 231 of the brush 230 cannot contact with the wafer 100 is preventable when the carrier 210 is moved upwardly to make the cutter 220 contacting with the wafer 100. In this embodiment, the first height H1 is higher than the second height H2.
  • With reference to FIGS. 1, 4 and 5, a cutting procedure and a contacting procedure are performed in step 12. The cutter 220 is used to cut the metal layer 120 along the scribe line 130 to form a plurality of cutting slots 140 on the wafer 110, wherein the dies 110 located at both sides of the cutting slot 140 are electrically disconnected with each other. With reference to FIG. 5, the wafer 100 is moved upwardly by the carrier 210 to contact with the cutter 220 in this embodiment, and then the wafer 100 is horizontally moved relative to the cutter 220 by the carrier 210 to cut the metal layer 120 along the scribe line 130 for forming the cutting slot 140. In this embodiment, the contacting portion 231 of the brush 230 following the cutter 220 contacts with the surface 111 of the die 110 and at least one cutting slot 140 when the cutter 220 cuts the metal layer 120 along the scribe line 130.
  • With reference to FIGS. 5 and 6, FIG. 6 is a cross-sectional view diagram along A-A line in FIG. 5. The metal layer 120 will remain a plurality of metal burrs 121 on the dies 110 when the cutter 220 cuts the metal layer 120 along the scribe line 130, and the metal burrs 121 will protrude from the surface 111 of each of the dies 110 because of cutting stress.
  • With reference to FIGS. 5 and 7, FIG. 7 is a cross-sectional view diagram along B-B line in FIG. 5. In the contacting procedure, the contacting portion 231 of the brush 230 can touch the surface 111 of each of the dies 110 and the cutting slot 140 along the cutting slot 140, and contact with each of the metal burrs 121, wherein deformation of the contacting portion 231 will occur during the contacting procedure because the contacting portion 231 is made of flexible material.
  • With reference to FIGS. 5 and 8, FIG. 8 is a cross-sectional view diagram along C-C line in FIG. 5. The contacting procedure can prevent the metal burrs 121 from protruding on the surface 111 of each of the dies 110. Preferably, each of the metal burrs 121 will be divided from the dies 110 or bent downwardly toward the cutting slot 140 by horizontal push force or vertical press force from the contacting portion 231 of the brush 230, so the problem that the metal burrs 121 protrude from the surface 111 of each of the dies 110 can be effectively solved. Therefore, the contacting procedure can prevent the metal burrs 121 from electrically connecting with other elements in the follow-up package processes to cause leakage or short circuit, and can prevent the metal burrs 121 from affecting electric signal input or output, or damaging other elements to affect semiconductor efficacy.
  • The cutting procedure and the contacting procedure are performed simultaneously in this embodiment, so the wafer 100 can be cleaned by air or water curtain to remove wafer fragment formed during the cutting procedure and the metal burrs 121 divided during the contacting procedure for preventing the wafer fragment or the metal burrs 121 from remaining on the wafer 100.
  • With reference to FIG. 5, in this embodiment, the contacting portion 231 of the brush 230 is placed behind the cutter 220 along with the cutting direction of the cutter 220, and the cutter 220 and the contacting portion 231 of the brush 230 are located on the same scribe line 130. Owing to the cutting procedure and the contacting procedure are performed simultaneously, the contacting portion 231 of the brush 230 can immediately contact with the metal burrs 121 along the cutting slot 140 formed newly to divide the metal burrs 121 from the dies 110 or bend the metal burrs 121 downwardly toward the cutting slot 140 when the cutter 220 cuts the metal layer 120 along the scribe line 130 to form the cutting slot 140, to prevent the metal burrs 121 from protruding from the surface 111 of the die 110.
  • In other embodiment, the contacting procedure can be performed after completing the cutting procedure. That means the contacting portion 231 of the brush 230 contacts with the metal burrs 121 along each of the cutting slots 140 to divide the metal burrs 121 from the die 110 or bend the metal burrs 121 downwardly toward the cutting slot 140 after the cutter 220 cuts the wafer 100 to make all the dies 110 electrically disconnecting with each other.
  • Second embodiment of the present invention is illustrated in FIGS. 9 and 10, the difference between the second embodiment and the first embodiment is the contacting portion 231 of the brush 230 is placed on the side of the cutter 220 along with the cutting direction of the cutter 220, and the cutter 220 and the contacting portion 231 of the brush 230 are located on the different scribe lines 130. Owing to the cutting procedure and the contacting procedure are performed simultaneously, the brush 230 located on the side of the cutter 220 can contact with the metal burrs 121 along the cutting slot 140 formed previously to divide the metal burrs 121 from the die 110 or bend the metal burrs 121 downwardly toward the cutting slot 140 when the cutter 220 cuts the wafer 100 to form new cutting slot 140. With reference to FIG. 10, the contacting portion 231 of the brush 230 is separated from the cutter 220 by at least one scribe line 130 preferably to prevent interference between the contacting portion 231 of the brush 230 and the cutter 220.
  • While this invention has been particularly illustrated and described in detail with respect to the preferred embodiments thereof, it will be clearly understood by those skilled in the art that is not limited to the specific features shown and described and various modified and changed in form and details may be made without departing from the spirit and scope of this invention.

Claims (4)

1. A wafer dicing method comprising:
providing a wafer including a plurality of dies and a metal layer, layer, wherein each of the dies includes a surface and there is a scribe line formed between adjacent dies, and wherein the metal layer is formed on the scribe line;
placing the wafer on a bearing surface of a carrier; and
performing a cutting procedure and a contacting procedure simultaneously, wherein a cutter is used to cut the metal layer along the scribe line during the cutting procedure to form a plurality of cutting slots on the wafer such that a plurality of metal burrs remain on the cutting slots of the dies, and using a contacting portion of a brush to contact with each of the metal burrs along the cutting slot during the contacting procedure to prevent each of the metal burrs from protruding from the surface of each of the dies wherein, during the simultaneous cutting and contacting procedures, the contacting portion of the brush is arranged behind the cutter along a cutting direction of the cutter and the cutter and the contacting portion are located on the same scribe line and wherein, before performing the simultaneous cutting and contacting procedures, a first height exists between a terminal of the cutter and the bearing surface of the carrier and a second height exists between a contacting portion of the brush and the bearing surface of the carrier and wherein the first height is equal to or higher than the second height.
2. The wafer dicing method in accordance with claim 1, wherein each of the metal burrs is separated from the die or bent downwardly toward the cutting slot when the contacting portion of the brush contacts with each of the metal burrs.
3-8. (canceled)
9. The wafer dicing method in accordance with claim 1, wherein the contacting portion of the brush is made of flexible material, and deformation of the contacting portion occurs during the contacting procedure.
US15/342,241 2016-09-23 2016-11-03 Wafer dicing method Active US9929051B1 (en)

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Family Cites Families (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3735483A (en) * 1970-03-20 1973-05-29 Gen Electric Semiconductor passivating process
JPS61181615A (en) 1985-02-07 1986-08-14 三菱電機株式会社 Cutter for semiconductor wafer
JPH02155611A (en) 1988-12-07 1990-06-14 Mitsubishi Electric Corp Dicing apparatus
JP2680453B2 (en) * 1989-12-11 1997-11-19 株式会社東京精密 Dicing method
US6165813A (en) * 1995-04-03 2000-12-26 Xerox Corporation Replacing semiconductor chips in a full-width chip array
JP3496347B2 (en) * 1995-07-13 2004-02-09 株式会社デンソー Semiconductor device and manufacturing method thereof
JP2000173952A (en) * 1998-12-03 2000-06-23 Fujitsu Quantum Device Kk Semiconductor device and its manufacture
JP2001326193A (en) 2000-05-15 2001-11-22 Sony Corp Dicing device and dicing method
US6423565B1 (en) * 2000-05-30 2002-07-23 Kurt L. Barth Apparatus and processes for the massproduction of photovotaic modules
JP2002043474A (en) * 2000-07-21 2002-02-08 Nakamura Seisakusho Kk Forming method of package for electronic component
US6946326B2 (en) * 2000-12-05 2005-09-20 Analog Devices, Inc. Method and device for protecting micro electromechanical systems structures during dicing of a wafer
JP2002224929A (en) * 2001-01-30 2002-08-13 Takemoto Denki Seisakusho:Kk Device for cutting plate-like workpiece
JP2003133256A (en) 2001-10-23 2003-05-09 Sharp Corp Dicing device
JP2003209089A (en) 2002-01-17 2003-07-25 Sony Corp Cleaning method, cleaning device and dicing device for wafer
WO2004061935A1 (en) * 2002-12-27 2004-07-22 Fujitsu Limited Method for forming bump, semiconductor devcie and its manufacturing method, substrate treatment device, and semiconductor manufacturing apparatus
JP3945415B2 (en) * 2003-02-14 2007-07-18 セイコーエプソン株式会社 Manufacturing method of semiconductor device
JP2005142399A (en) 2003-11-07 2005-06-02 Tokyo Seimitsu Co Ltd Dicing method
JP2005191332A (en) * 2003-12-26 2005-07-14 Matsushita Electric Ind Co Ltd Method for manufacturing semiconductor device and semiconductor device manufacturing equipment
US6974726B2 (en) * 2003-12-30 2005-12-13 Intel Corporation Silicon wafer with soluble protective coating
KR100630698B1 (en) * 2004-08-17 2006-10-02 삼성전자주식회사 Semiconductor package improving a solder joint reliability and method for manufacturing the same
JP2007125667A (en) * 2005-11-07 2007-05-24 Disco Abrasive Syst Ltd Cutting device of substrate
JP4777072B2 (en) 2006-01-11 2011-09-21 株式会社東京精密 Dicing machine
KR20090024408A (en) 2007-09-04 2009-03-09 삼성전자주식회사 Appratus for sawing a wafer having a nozzle eliminating a metal burr in a scribe lane, method of sawing the wafer and semiconductor package fabricated thereby the same
US7951688B2 (en) * 2007-10-01 2011-05-31 Fairchild Semiconductor Corporation Method and structure for dividing a substrate into individual devices
JP5156459B2 (en) 2008-04-09 2013-03-06 Towa株式会社 Substrate cutting method and apparatus
GB2464549B (en) * 2008-10-22 2013-03-27 Cambridge Silicon Radio Ltd Improved wafer level chip scale packaging
US9548240B2 (en) * 2010-03-15 2017-01-17 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming repassivation layer for robust low cost fan-out semiconductor package
DE102010040062B4 (en) * 2010-08-31 2014-05-22 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg A substrate distribution technique for separating semiconductor chips with less area consumption
US8365398B2 (en) * 2011-01-26 2013-02-05 Jeng-Jye Shau Accurate alignment for stacked substrates
DE102012111358A1 (en) * 2012-11-23 2014-05-28 Osram Opto Semiconductors Gmbh Method for separating a composite into semiconductor chips and semiconductor chip
US9355906B2 (en) * 2013-03-12 2016-05-31 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging devices and methods of manufacture thereof
US9458012B2 (en) * 2014-02-18 2016-10-04 Freescale Semiconductor, Inc. Method for shielding MEMS structures during front side wafer dicing
JP2015220240A (en) 2014-05-14 2015-12-07 株式会社ディスコ Processing method for wafer
JP6338478B2 (en) 2014-07-18 2018-06-06 Towa株式会社 Cutting method and product manufacturing method
JP5976055B2 (en) 2014-08-21 2016-08-23 力晶科技股▲ふん▼有限公司 Semiconductor wafer, semiconductor chip, semiconductor device and manufacturing method thereof
KR20160057966A (en) * 2014-11-14 2016-05-24 가부시끼가이샤 도시바 Processing apparatus, nozzle and dicing apparatus
JP2016134433A (en) 2015-01-16 2016-07-25 株式会社東芝 Dicing machine

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TW201812887A (en) 2018-04-01
KR20180033028A (en) 2018-04-02
SG10201808373QA (en) 2018-10-30
KR101847948B1 (en) 2018-04-11
JP2018050020A (en) 2018-03-29
US9929051B1 (en) 2018-03-27
SG10201609698PA (en) 2018-04-27

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